i945: fix tsc udelay()

[coreboot.git] / src / northbridge / intel / i945 / udelay.c

diff --git a/src/northbridge/intel/i945/udelay.c b/src/northbridge/intel/i945/udelay.c
index 3a96c79aae337bfc58d38226cf37008775d7d78d..9170335bd58c56c5c5736a225a847904012c7739 100644 (file)
--- a/src/northbridge/intel/i945/udelay.c
+++ b/src/northbridge/intel/i945/udelay.c
@@ -17,6 +17,8 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
+#include <delay.h>
+#include <stdint.h>
 #include <cpu/x86/tsc.h>
 #include <cpu/x86/msr.h>
 
@@ -24,7 +26,7 @@
  * Intel Core(tm) cpus always run the TSC at the maximum possible CPU clock
  */
 
-static void udelay(u32 us)
+void udelay(u32 us)
 {
        u32 dword;
        tsc_t tsc, tsc1, tscd;
@@ -44,6 +46,18 @@ static void udelay(u32 us)
        case 3:
                fsb = 667;
                break;
+       case 2:
+               fsb = 800;
+               break;
+       case 0:
+               fsb = 1067;
+               break;
+       case 4:
+               fsb = 1333;
+               break;
+       case 6:
+               fsb = 1600;
+               break;
        }
 
        msr = rdmsr(0x198);
@@ -64,7 +78,7 @@ static void udelay(u32 us)
 
        do {
                tsc = rdtsc();
-       } while ((tsc.hi > tsc1.hi)
-                || ((tsc.hi == tsc1.hi) && (tsc.lo > tsc1.lo)));
+       } while ((tsc.hi < tsc1.hi)
+                || ((tsc.hi == tsc1.hi) && (tsc.lo < tsc1.lo)));
 
 }