pci1x2x: remove latency/bridge control/cacheline size settings

[coreboot.git] / src / mainboard / nokia / ip530 / devicetree.cb

diff --git a/src/mainboard/nokia/ip530/devicetree.cb b/src/mainboard/nokia/ip530/devicetree.cb
index ac6d78ed75208d76a400676d0d8e045db131fa2e..f89d1cd9fec18bea17395153dc3f0ce9cb75306a 100644 (file)
--- a/src/mainboard/nokia/ip530/devicetree.cb
+++ b/src/mainboard/nokia/ip530/devicetree.cb
@@ -31,10 +31,8 @@ chip northbridge/intel/i440bx                # Northbridge
       device pci f.0 on
         chip southbridge/ti/pci1x2x
             device pci 00.0 on
-
+                       subsystemid 0x13b8 0x0000
             end
-            register "cltr" = "0x40"
-            register "bcr" = "0x7c0"
             register "scr" = "0x08449060"
             register "mrr" = "0x00007522"
        end