removed 7seg from DT

[calu.git] / cpu / src / r2_w_ram_b.vhd

diff --git a/cpu/src/r2_w_ram_b.vhd b/cpu/src/r2_w_ram_b.vhd
index a0b163939bd2667f73fc2311d1a82e5211a62d50..64c8da4e21f0ca689be0f3853d5acddfbcc893b3 100644 (file)
--- a/cpu/src/r2_w_ram_b.vhd
+++ b/cpu/src/r2_w_ram_b.vhd
@@ -12,10 +12,10 @@ architecture behaviour of r2_w_ram is
        
        signal ram : RAM_TYPE := (
                                0 => x"00000000",
-                               1 => x"00000001",
-                               2 => x"FFFFFFFF",
-                               3 => x"00000003",
-                               others=> x"00000000");
+                               1 => x"00000000",
+                               2 => x"00000000",
+                               3 => x"00000000",
+                               others=> (others => '0'));
 
 begin
        process(clk)