library ieee;

use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

use work.mem_pkg.all;

architecture behaviour of r2_w_ram is

	subtype RAM_ENTRY_TYPE is std_logic_vector(DATA_WIDTH -1 downto 0);
	type RAM_TYPE is array (0 to (2**ADDR_WIDTH)-1) of RAM_ENTRY_TYPE;
	
	signal ram : RAM_TYPE := (
				0 => x"00000000",
				1 => x"00000000",
				2 => x"00000000",
				3 => x"00000000",
				others=> (others => '0'));

begin
	process(clk)
	begin
		if rising_edge(clk) then
			data_out1 <= ram(to_integer(UNSIGNED(rd_addr1)));
			data_out2 <= ram(to_integer(UNSIGNED(rd_addr2)));
			
			if wr_en = '1' then
				ram(to_integer(UNSIGNED(wr_addr))) <= data_in;
			end if;
		end if;
	end process;
end architecture behaviour;