allgemein: components fuer die module

[hwmod.git] / src / beh_uart_rx_tb.vhd

diff --git a/src/beh_uart_rx_tb.vhd b/src/beh_uart_rx_tb.vhd
index f5e3c6936b654edb597ee135df99669ab119517a..e6d2ad55c4d7986ed43ff54a6ea2bd9f4833c86b 100644 (file)
--- a/src/beh_uart_rx_tb.vhd
+++ b/src/beh_uart_rx_tb.vhd
@@ -15,7 +15,7 @@ architecture sim of beh_uart_rx_tb is
        signal rx_data : std_logic_vector (7 downto 0);
        signal stop : boolean := false;
 begin
-       inst : entity work.uart_rx(beh)
+       inst : uart_rx
        generic map (
                CLK_FREQ => CLK_FREQ,
                BAUDRATE => BAUDRATE