allgemein: components fuer die module

[hwmod.git] / src / beh_history_tb.vhd

diff --git a/src/beh_history_tb.vhd b/src/beh_history_tb.vhd
index 87115c724c2ed37b7ed3faa0634838bea4ee4250..f249361c03d3f9869e405015187fe99d630ecb42 100644 (file)
--- a/src/beh_history_tb.vhd
+++ b/src/beh_history_tb.vhd
@@ -52,7 +52,7 @@ architecture sim of beh_history_tb is
        signal stop : boolean := false;
 begin
        -- history
-       inst : entity work.history(beh)
+       inst : history
        port map (
                sys_clk => sys_clk,
                sys_res_n => sys_res_n,
@@ -87,7 +87,7 @@ begin
        );
 
        -- display
-       inst_disp : entity work.display(beh)
+       inst_disp : display
        port map (
                sys_clk => sys_clk,
                sys_res_n => sys_res_n,
@@ -107,7 +107,7 @@ begin
        );
 
        -- parser
-       inst_parser : entity work.parser(beh)
+       inst_parser : parser
        port map (
                sys_clk => sys_clk,
                sys_res_n => sys_res_n,
@@ -125,7 +125,7 @@ begin
        );
 
        -- scanner
-       inst_scan : entity work.scanner(beh)
+       inst_scan : scanner
        port map (
                sys_clk => sys_clk,
                sys_res_n => sys_res_n,
@@ -142,7 +142,7 @@ begin
                finished => finished
        );
        --uart_tx
-       inst_uart : entity work.uart_tx(beh)
+       inst_uart : uart_tx
        port map (
                sys_clk => sys_clk,
                sys_res_n => sys_res_n,
@@ -153,7 +153,7 @@ begin
        );
 
        --pc_communication
-       inst_pc_com : entity work.pc_communication(beh)
+       inst_pc_com : pc_communication
        port map(
                sys_clk => sys_clk,
                sys_res_n => sys_res_n,