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4er slot (3. bsp fertig)
[dide_16.git]
/
bsp3
/
Designflow
/
ppr
/
sim
/
simulation
/
modelsim
/
vga.sft
diff --git a/bsp3/Designflow/ppr/sim/simulation/modelsim/vga.sft
b/bsp3/Designflow/ppr/sim/simulation/modelsim/vga.sft
new file mode 100644
(file)
index 0000000..
d306a9b
--- /dev/null
+++ b/
bsp3/Designflow/ppr/sim/simulation/modelsim/vga.sft
@@ -0,0
+1,4
@@
+set tool_name "ModelSim-Altera (VHDL)"
+set corner_file_list {
+ {{"Slow Model"} {vga.vho vga_vhd.sdo}}
+}