X-Git-Url: http://wien.tomnetworks.com/gitweb/?p=dide_16.git;a=blobdiff_plain;f=bsp3%2FDesignflow%2Fppr%2Fsim%2Fsimulation%2Fmodelsim%2Fvga.sft;fp=bsp3%2FDesignflow%2Fppr%2Fsim%2Fsimulation%2Fmodelsim%2Fvga.sft;h=d306a9b182212881c062463ee9686e5c969ab2da;hp=0000000000000000000000000000000000000000;hb=2e69ab76da77197b041789f8d0d8908d3ded918e;hpb=5094f38dc303ffb483f21916399e293a56c5ac99

diff --git a/bsp3/Designflow/ppr/sim/simulation/modelsim/vga.sft b/bsp3/Designflow/ppr/sim/simulation/modelsim/vga.sft
new file mode 100644
index 0000000..d306a9b
--- /dev/null
+++ b/bsp3/Designflow/ppr/sim/simulation/modelsim/vga.sft
@@ -0,0 +1,4 @@
+set tool_name "ModelSim-Altera (VHDL)"
+set corner_file_list {
+	{{"Slow Model"} {vga.vho vga_vhd.sdo}}
+}