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d306a9b182212881c062463ee9686e5c969ab2da
[dide_16.git]
/
bsp3
/
Designflow
/
ppr
/
sim
/
simulation
/
modelsim
/
vga.sft
1
set tool_name "ModelSim-Altera (VHDL)"
2
set corner_file_list {
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{{"Slow Model"} {vga.vho vga_vhd.sdo}}
4
}