bsp2 fail :(

[dide_16.git] / bsp2 / Designflow / syn / rev_1 / syntmp / sap.log

diff --git a/bsp2/Designflow/syn/rev_1/syntmp/sap.log b/bsp2/Designflow/syn/rev_1/syntmp/sap.log
new file mode 100644 (file)
index 0000000..4b5d11a
--- /dev/null
+++ b/bsp2/Designflow/syn/rev_1/syntmp/sap.log
@@ -0,0 +1,13 @@
+Synopsys Altera Technology Mapper, Version map450rc, Build 029R, Built May 22 2009 13:59:53
+Copyright (C) 1994-2009, Synopsys Inc.  All Rights Reserved
+Product Version C-2009.06
+@N: MF249 |Running in 32-bit mode.
+@N: MF257 |Gated clock conversion enabled 
+@N|Running in logic synthesis mode without enhanced optimization
+@W|Ignoring synthesis effort setting for the design. This is not supported by the current technology.
+
+@N: BN225 |Writing default property annotation file /homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.sap.
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Wed Oct 21 17:26:30 2009
+
+###########################################################]