Synopsys Altera Technology Mapper, Version map450rc, Build 029R, Built May 22 2009 13:59:53
Copyright (C) 1994-2009, Synopsys Inc.  All Rights Reserved
Product Version C-2009.06
@N: MF249 |Running in 32-bit mode.
@N: MF257 |Gated clock conversion enabled 
@N|Running in logic synthesis mode without enhanced optimization
@W|Ignoring synthesis effort setting for the design. This is not supported by the current technology.

@N: BN225 |Writing default property annotation file /homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.sap.
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Oct 21 17:26:30 2009

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