Fixed some bugs.

[calu.git] / cpu / src / execute_stage_b.vhd

diff --git a/cpu/src/execute_stage_b.vhd b/cpu/src/execute_stage_b.vhd
index 080fb00accba7186704cd9e474927f4c8c5a4beb..1f2c194ac263470f6bfa560da6ae9c9abd1bdfb9 100644 (file)
--- a/cpu/src/execute_stage_b.vhd
+++ b/cpu/src/execute_stage_b.vhd
@@ -4,6 +4,7 @@ use IEEE.numeric_std.all;
 
 use work.common_pkg.all;
 use work.alu_pkg.all;
+use work.gpm_pkg.all;
 
 architecture behav of execute_stage is
 
@@ -28,14 +29,18 @@ begin
 
 alu_inst : alu
 port map(clk, reset, condition, op_group, 
-        op_detail, left_operand, right_operand, alu_state, alu_nxt,addr,data);
+         left_operand, right_operand, op_detail, alu_state, alu_nxt,addr,data);
+
+gpm_inst : gpm
+        generic map(RESET_VALUE)
+        port map(clk,reset,alu_nxt,psw);
 
 syn: process(clk, reset)
 
 begin
 
        if reset = RESET_VALUE then
-               reg.alu_jmp <= '0';
+               reg.alu_jump <= '0';
                 reg.brpr <= '0';
                 reg.wr_en <= '0';
                 reg.result <= (others =>'0');
@@ -69,14 +74,14 @@ begin
         reg_nxt.alu_jump <= alu_nxt.alu_jump;
         reg_nxt.wr_en <= alu_nxt.reg_op;
         reg_nxt.result <= alu_nxt.result;
-        reg_nxt.reg_addr <= alu_nxt.result_addr;
+        reg_nxt.res_addr <= alu_nxt.result_addr;
 
 end process asyn;
 
 result <= reg.result;
 result_addr <= reg.res_addr;
-alu_jmp <= reg.alu_jump;
-brbr <= reg.brpr;
+alu_jump <= reg.alu_jump;
+brpr <= reg.brpr;
 wr_en <= reg.wr_en;
 dmem <= alu_nxt.mem_op;
 dmem_write_en <= alu_nxt.mem_en;