dispi_write(VBE_DISPI_INDEX_ID, VBE_DISPI_ID5);
- u32 lfb_addr;
- if (CONFIG_VGA_PCI)
- lfb_addr = (pci_config_readl(GET_GLOBAL(VgaBDF), PCI_BASE_ADDRESS_0)
+ u32 lfb_addr = VBE_DISPI_LFB_PHYSICAL_ADDRESS;
+ int bdf = GET_GLOBAL(VgaBDF);
+ if (CONFIG_VGA_PCI && bdf >= 0)
+ lfb_addr = (pci_config_readl(bdf, PCI_BASE_ADDRESS_0)
& PCI_BASE_ADDRESS_MEM_MASK);
- else
- lfb_addr = VBE_DISPI_LFB_PHYSICAL_ADDRESS;
SET_VGA(VBE_framebuffer, lfb_addr);
u16 totalmem = dispi_read(VBE_DISPI_INDEX_VIDEO_MEMORY_64K);
dprintf(1, "cirrus init 2\n");
u32 lfb_addr = 0;
- if (CONFIG_VGA_PCI)
- lfb_addr = (pci_config_readl(GET_GLOBAL(VgaBDF), PCI_BASE_ADDRESS_0)
+ int bdf = GET_GLOBAL(VgaBDF);
+ if (CONFIG_VGA_PCI && bdf >= 0)
+ lfb_addr = (pci_config_readl(bdf, PCI_BASE_ADDRESS_0)
& PCI_BASE_ADDRESS_MEM_MASK);
SET_VGA(VBE_framebuffer, lfb_addr);
u16 totalmem = cirrus_get_memsize();
stdvga_override_crtc(i, crtc);
}
+ if (GET_GLOBAL(VgaBDF) < 0)
+ // Device should be at 00:01.1
+ SET_VGA(VgaBDF, pci_to_bdf(0, 1, 1));
ret |= vp_setup();
ret |= dc_setup();
#include "stdvga.h" // stdvga_set_cursor_shape
#include "clext.h" // clext_1012
#include "vgahw.h" // vgahw_set_mode
+#include "pci.h" // pci_config_readw
+#include "pci_regs.h" // PCI_VENDOR_ID
// XXX
#define DEBUG_VGA_POST 1
SET_BDA(video_msr, 0x09);
}
-u16 VgaBDF VAR16;
+int VgaBDF VAR16 = -1;
void VISIBLE16
vga_post(struct bregs *regs)
{
debug_enter(regs, DEBUG_VGA_POST);
- SET_VGA(VgaBDF, regs->ax);
+ if (CONFIG_VGA_PCI) {
+ u16 bdf = regs->ax;
+ if (pci_config_readw(bdf, PCI_VENDOR_ID) == CONFIG_VGA_VID
+ && pci_config_readw(bdf, PCI_DEVICE_ID) == CONFIG_VGA_DID)
+ SET_VGA(VgaBDF, bdf);
+ }
int ret = vgahw_init();
if (ret) {
extern u8 vgafont16alt[];
// vgabios.c
-extern u16 VgaBDF;
+extern int VgaBDF;
#define SET_VGA(var, val) SET_FARVAR(get_global_seg(), (var), (val))
struct carattr {
u8 car, attr, use_attr;