#define PCI_DEVICE_ID_INTEL_82441 0x1237
#define PCI_DEVICE_ID_INTEL_82371SB_0 0x7000
#define PCI_DEVICE_ID_INTEL_82371SB_1 0x7010
+#define PCI_DEVICE_ID_INTEL_82371AB_0 0x7110
+#define PCI_DEVICE_ID_INTEL_82371AB 0x7111
#define PCI_DEVICE_ID_INTEL_82371AB_3 0x7113
device_id = pci_config_readw(d, PCI_DEVICE_ID);
if (vendor_id == PCI_VENDOR_ID_INTEL
- && device_id == PCI_DEVICE_ID_INTEL_82371SB_0) {
+ && (device_id == PCI_DEVICE_ID_INTEL_82371SB_0
+ || device_id == PCI_DEVICE_ID_INTEL_82371AB_0)) {
int i, irq;
u8 elcr[2];
- /* PIIX3 bridge */
+ /* PIIX3/PIIX4 PCI to ISA bridge */
elcr[0] = 0x00;
elcr[1] = 0x00;
}
outb(elcr[0], 0x4d0);
outb(elcr[1], 0x4d1);
- dprintf(1, "PIIX3 init: elcr=%02x %02x\n",
+ dprintf(1, "PIIX3/PIIX4 init: elcr=%02x %02x\n",
elcr[0], elcr[1]);
}
}
switch(class) {
case 0x0101:
if (vendor_id == PCI_VENDOR_ID_INTEL
- && device_id == PCI_DEVICE_ID_INTEL_82371SB_1) {
- /* PIIX3 IDE */
+ && (device_id == PCI_DEVICE_ID_INTEL_82371SB_1
+ || device_id == PCI_DEVICE_ID_INTEL_82371AB)) {
+ /* PIIX3/PIIX4 IDE */
pci_config_writew(d, 0x40, 0x8000); // enable IDE0
pci_config_writew(d, 0x42, 0x8000); // enable IDE1
goto default_map;