u8 status = inb(base+ATA_CB_STAT);
if ((status & mask) == flags)
return status;
- if (check_time(end)) {
+ if (check_tsc(end)) {
warn_timeout();
return -1;
}
if (inb(iobase1 + ATA_CB_DH) == ATA_CB_DH_DEV1)
break;
// Change drive request failed to take effect - retry.
- if (check_time(end)) {
+ if (check_tsc(end)) {
warn_timeout();
goto done;
}
if (status & BM_STATUS_IRQ)
break;
// Transfer in progress
- if (check_time(end)) {
+ if (check_tsc(end)) {
// Timeout.
warn_timeout();
break;
dprintf(4, "powerup IDE floating\n");
return orstatus;
}
- if (check_time(SpinupEnd)) {
+ if (check_tsc(SpinupEnd)) {
warn_timeout();
return -1;
}
int in_progress = 0;
u64 end = calc_future_tsc(5000);
for (;;) {
- if (check_time(end)) {
+ if (check_tsc(end)) {
dprintf(1, "read capacity failed\n");
return -1;
}
{
u64 start = rdtscll();
u64 end = start + diff;
- while (!check_time(end))
+ while (!check_tsc(end))
cpu_relax();
}
{
u64 start = rdtscll();
u64 end = start + diff;
- while (!check_time(end))
+ while (!check_tsc(end))
yield();
}
for (;;) {
if ((inb_cmos(CMOS_STATUS_A) & RTC_A_UIP) == 0)
return 0;
- if (check_time(end))
+ if (check_tsc(end))
// update-in-progress never transitioned to 0
return -1;
yield();
dprintf(1, "Discarding ps2 data %02x (status=%02x)\n", data, status);
}
- if (check_time(end)) {
+ if (check_tsc(end)) {
// Don't warn on second byte of a reset
if (timeout > 100)
warn_timeout();
cmd = readl(&cntl->regs->usbcmd);
if (!(cmd & CMD_HCRESET))
break;
- if (check_time(end)) {
+ if (check_tsc(end)) {
warn_timeout();
goto fail;
}
if (qh->qtd_next & EHCI_PTR_TERM)
// XXX - confirm
return 0;
- if (check_time(end)) {
+ if (check_tsc(end)) {
warn_timeout();
return -1;
}
if (!(cmd & CMD_IAAD))
break;
}
- if (check_time(end)) {
+ if (check_tsc(end)) {
warn_timeout();
return;
}
sts = readl(&cntl->regs->usbsts);
if (sts & STS_IAA)
break;
- if (check_time(end)) {
+ if (check_tsc(end)) {
warn_timeout();
return;
}
status = td->token;
if (!(status & QTD_STS_ACTIVE))
break;
- if (check_time(end)) {
+ if (check_tsc(end)) {
warn_timeout();
return -1;
}
if (sts.wPortStatus & USB_PORT_STAT_CONNECTION)
// Device connected.
break;
- if (check_time(end))
+ if (check_tsc(end))
// No device found.
return -1;
msleep(5);
goto fail;
if (!(sts.wPortStatus & USB_PORT_STAT_RESET))
break;
- if (check_time(end)) {
+ if (check_tsc(end)) {
warn_timeout();
goto fail;
}
if (!(sts & RH_PS_PRS))
// XXX - need to ensure USB_TIME_DRSTR time in reset?
break;
- if (check_time(end)) {
+ if (check_tsc(end)) {
// Timeout.
warn_timeout();
ohci_hub_disconnect(hub, port);
u32 status = readl(&cntl->regs->cmdstatus);
if (! status & OHCI_HCR)
break;
- if (check_time(end)) {
+ if (check_tsc(end)) {
warn_timeout();
return -1;
}
for (;;) {
if (ed->hwHeadP == ed->hwTailP)
return 0;
- if (check_time(end)) {
+ if (check_tsc(end)) {
warn_timeout();
return -1;
}
for (;;) {
if (hcca->frame_no != startframe)
break;
- if (check_time(end)) {
+ if (check_tsc(end)) {
warn_timeout();
return;
}
for (;;) {
if (qh->element & UHCI_PTR_TERM)
return 0;
- if (check_time(end)) {
+ if (check_tsc(end)) {
warn_timeout();
struct uhci_td *td = (void*)(qh->element & ~UHCI_PTR_BITS);
dprintf(1, "Timeout on wait_qh %p (td=%p s=%x c=%x/%x)\n"
for (;;) {
if (inw(iobase + USBFRNUM) != startframe)
break;
- if (check_time(end)) {
+ if (check_tsc(end)) {
warn_timeout();
return;
}
status = td->status;
if (!(status & TD_CTRL_ACTIVE))
break;
- if (check_time(end)) {
+ if (check_tsc(end)) {
warn_timeout();
return -1;
}
// clock.c
#define PIT_TICK_RATE 1193180 // Underlying HZ of PIT
#define PIT_TICK_INTERVAL 65536 // Default interval for 18.2Hz timer
-static inline int check_time(u64 end) {
+static inline int check_tsc(u64 end) {
return (s64)(rdtscll() - end) > 0;
}
void timer_setup(void);