#include "bregs.h" // struct bregs
#include "vbe.h" // struct vbe_info
#include "stdvga.h" // VGAREG_SEQU_ADDRESS
+#include "pci.h" // pci_config_readl
+#include "pci_regs.h" // PCI_BASE_ADDRESS_0
/****************************************************************
0x2c11,
0x5f00,0x4f01,0x4f02,0x8003,0x5204,0x1e05,0x0b06,0x3e07,
0x4009,0x000c,0x000d,
- 0xea10,0xdf12,0x0013,0x4014,0xdf15,0x0b16,0xc317,0xff18,
- 0x001a,0x321b,0x001d,
+ 0xea10,0xdf12,0xf013,0x4014,0xdf15,0x0b16,0xc317,0xff18,
+ 0x001a,0x221b,0x001d,
0xffff
};
/* 800x600x8 */
static u16 ccrtc_1600x1200x8[] VAR16 = {
0x2911,0xc300,0x9f01,0x9f02,0x8603,0x8304,0x9405,0x2406,0xf707,
0x6009,0x000c,0x000d,
- 0x0310,0xff12,0xa013,0x4014,0xff15,0x2416,0xc317,0xff18,
+ 0x0310,0xff12,0xc813,0x4014,0xff15,0x2416,0xc317,0xff18,
0x001a,0x221b,0x001d,
0xffff
};
outb(0xff, VGAREG_PEL_MASK);
u8 memmodel = GET_GLOBAL(table->info.memmodel);
- u8 v = stdvga_get_single_palette_reg(0x10) & 0xfe;
+ u8 on = 0;
if (memmodel == MM_PLANAR)
- v |= 0x41;
+ on = 0x41;
else if (memmodel != MM_TEXT)
- v |= 0x01;
- stdvga_set_single_palette_reg(0x10, v);
+ on = 0x01;
+ stdvga_attr_mask(0x10, 0x01, on);
}
static u8
int
clext_set_mode(int mode, int flags)
{
- dprintf(1, "cirrus mode %d\n", mode);
+ dprintf(1, "cirrus mode %x\n", mode);
SET_BDA(vbe_mode, 0);
struct cirrus_mode_s *table_g = cirrus_get_modeentry(mode);
if (table_g) {
****************************************************************/
static void
-cirrus_extbios_80h(struct bregs *regs)
+clext_101280(struct bregs *regs)
{
u16 crtc_addr = stdvga_get_crtc();
outb(0x27, crtc_addr);
}
static void
-cirrus_extbios_81h(struct bregs *regs)
+clext_101281(struct bregs *regs)
{
// XXX
regs->ax = 0x0100;
}
static void
-cirrus_extbios_82h(struct bregs *regs)
+clext_101282(struct bregs *regs)
{
u16 crtc_addr = stdvga_get_crtc();
outb(0x27, crtc_addr);
}
static void
-cirrus_extbios_85h(struct bregs *regs)
+clext_101285(struct bregs *regs)
{
regs->al = cirrus_get_memsize();
}
static void
-cirrus_extbios_9Ah(struct bregs *regs)
+clext_10129a(struct bregs *regs)
{
regs->ax = 0x4060;
regs->cx = 0x1132;
"retf");
static void
-cirrus_extbios_A0h(struct bregs *regs)
+clext_1012a0(struct bregs *regs)
{
struct cirrus_mode_s *table_g = cirrus_get_modeentry(regs->al & 0x7f);
regs->ah = (table_g ? 1 : 0);
}
static void
-cirrus_extbios_A1h(struct bregs *regs)
+clext_1012a1(struct bregs *regs)
{
regs->bx = 0x0e00; // IBM 8512/8513, color
}
static void
-cirrus_extbios_A2h(struct bregs *regs)
+clext_1012a2(struct bregs *regs)
{
regs->al = 0x07; // HSync 31.5 - 64.0 kHz
}
static void
-cirrus_extbios_AEh(struct bregs *regs)
+clext_1012ae(struct bregs *regs)
{
regs->al = 0x01; // High Refresh 75Hz
}
+static void
+clext_1012XX(struct bregs *regs)
+{
+ debug_stub(regs);
+}
+
void
-cirrus_extbios(struct bregs *regs)
+clext_1012(struct bregs *regs)
{
- // XXX - regs->bl < 0x80 or > 0xaf call regular handlers.
switch (regs->bl) {
- case 0x80: cirrus_extbios_80h(regs); break;
- case 0x81: cirrus_extbios_81h(regs); break;
- case 0x82: cirrus_extbios_82h(regs); break;
- case 0x85: cirrus_extbios_85h(regs); break;
- case 0x9a: cirrus_extbios_9Ah(regs); break;
- case 0xa0: cirrus_extbios_A0h(regs); break;
- case 0xa1: cirrus_extbios_A1h(regs); break;
- case 0xa2: cirrus_extbios_A2h(regs); break;
- case 0xae: cirrus_extbios_AEh(regs); break;
- default: break;
+ case 0x80: clext_101280(regs); break;
+ case 0x81: clext_101281(regs); break;
+ case 0x82: clext_101282(regs); break;
+ case 0x85: clext_101285(regs); break;
+ case 0x9a: clext_10129a(regs); break;
+ case 0xa0: clext_1012a0(regs); break;
+ case 0xa1: clext_1012a1(regs); break;
+ case 0xa2: clext_1012a2(regs); break;
+ case 0xae: clext_1012ae(regs); break;
+ default: clext_1012XX(regs); break;
}
}
static void
cirrus_set_line_offset(u16 new_line_offset)
{
+ new_line_offset /= 8;
u16 crtc_addr = stdvga_get_crtc();
outb(0x13, crtc_addr);
- outb(new_line_offset / 8, crtc_addr + 1);
+ outb(new_line_offset, crtc_addr + 1);
outb(0x1b, crtc_addr);
u8 v = inb(crtc_addr + 1);
- outb((((new_line_offset / 8) & 0x100) >> 4) | (v & 0xef), crtc_addr + 1);
+ outb(((new_line_offset & 0x100) >> 4) | (v & 0xef), crtc_addr + 1);
}
static u16
outb(0x1b, crtc_addr);
u8 reg1b = inb(crtc_addr + 1);
- return (((reg1b << 4) & 0x100) + reg13) * 8;
-}
-
-u16
-cirrus_get_line_offset_entry(struct cirrus_mode_s *table_g)
-{
- u16 *crtc = GET_GLOBAL(table_g->crtc);
-
- u16 *c = crtc;
- u16 reg13;
- for (;;) {
- reg13 = GET_GLOBAL(*c);
- if ((reg13 & 0xff) == 0x13)
- break;
- c++;
- }
- reg13 >>= 8;
-
- c = crtc;
- u16 reg1b;
- for (;;) {
- reg1b = GET_GLOBAL(*c);
- if ((reg1b & 0xff) == 0x1b)
- break;
- c++;
- }
- reg1b >>= 8;
-
- return (((reg1b << 4) & 0x100) + reg13) * 8;
+ return (((reg1b & 0x10) << 4) + reg13) * 8;
}
static void
return -1;
dprintf(1, "cirrus init 2\n");
+ SET_VGA(VBE_enabled, 1);
+ u32 lfb_addr = 0;
+ if (CONFIG_VGA_PCI)
+ lfb_addr = (pci_config_readl(GET_GLOBAL(VgaBDF), PCI_BASE_ADDRESS_0)
+ & PCI_BASE_ADDRESS_MEM_MASK);
+ SET_VGA(VBE_framebuffer, lfb_addr);
u16 totalmem = cirrus_get_memsize();
SET_VGA(VBE_total_memory, totalmem * 64 * 1024);
SET_VGA(VBE_win_granularity, 16);