1 // QEMU Cirrus CLGD 54xx VGABIOS Extension.
3 // Copyright (C) 2009 Kevin O'Connor <kevin@koconnor.net>
4 // Copyright (c) 2004 Makoto Suzuki (suzu)
6 // This file may be distributed under the terms of the GNU LGPLv3 license.
8 #include "clext.h" // clext_init
9 #include "vgabios.h" // VBE_VENDOR_STRING
10 #include "biosvar.h" // GET_GLOBAL
11 #include "util.h" // dprintf
12 #include "bregs.h" // struct bregs
13 #include "vbe.h" // struct vbe_info
14 #include "stdvga.h" // VGAREG_SEQU_ADDRESS
17 /****************************************************************
19 ****************************************************************/
22 static u16 cseq_vga[] VAR16 = {0x0007,0xffff};
23 static u16 cgraph_vga[] VAR16 = {0x0009,0x000a,0x000b,0xffff};
24 static u16 ccrtc_vga[] VAR16 = {0x001a,0x001b,0x001d,0xffff};
27 static u16 cgraph_svgacolor[] VAR16 = {
28 0x0000,0x0001,0x0002,0x0003,0x0004,0x4005,0x0506,0x0f07,0xff08,
33 static u16 cseq_640x480x8[] VAR16 = {
34 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
35 0x580b,0x580c,0x580d,0x580e,
37 0x331b,0x331c,0x331d,0x331e,
40 static u16 ccrtc_640x480x8[] VAR16 = {
42 0x5f00,0x4f01,0x4f02,0x8003,0x5204,0x1e05,0x0b06,0x3e07,
44 0xea10,0xdf12,0x5013,0x4014,0xdf15,0x0b16,0xc317,0xff18,
49 static u16 cseq_640x480x16[] VAR16 = {
50 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1707,
51 0x580b,0x580c,0x580d,0x580e,
53 0x331b,0x331c,0x331d,0x331e,
56 static u16 ccrtc_640x480x16[] VAR16 = {
58 0x5f00,0x4f01,0x4f02,0x8003,0x5204,0x1e05,0x0b06,0x3e07,
60 0xea10,0xdf12,0xa013,0x4014,0xdf15,0x0b16,0xc317,0xff18,
65 static u16 cseq_640x480x24[] VAR16 = {
66 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1507,
67 0x580b,0x580c,0x580d,0x580e,
69 0x331b,0x331c,0x331d,0x331e,
72 static u16 ccrtc_640x480x24[] VAR16 = {
74 0x5f00,0x4f01,0x4f02,0x8003,0x5204,0x1e05,0x0b06,0x3e07,
76 0xea10,0xdf12,0x0013,0x4014,0xdf15,0x0b16,0xc317,0xff18,
81 static u16 cseq_800x600x8[] VAR16 = {
82 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
83 0x230b,0x230c,0x230d,0x230e,
85 0x141b,0x141c,0x141d,0x141e,
88 static u16 ccrtc_800x600x8[] VAR16 = {
89 0x2311,0x7d00,0x6301,0x6302,0x8003,0x6b04,0x1a05,0x9806,0xf007,
91 0x7d10,0x5712,0x6413,0x4014,0x5715,0x9816,0xc317,0xff18,
96 static u16 cseq_800x600x16[] VAR16 = {
97 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1707,
98 0x230b,0x230c,0x230d,0x230e,
100 0x141b,0x141c,0x141d,0x141e,
103 static u16 ccrtc_800x600x16[] VAR16 = {
104 0x2311,0x7d00,0x6301,0x6302,0x8003,0x6b04,0x1a05,0x9806,0xf007,
105 0x6009,0x000c,0x000d,
106 0x7d10,0x5712,0xc813,0x4014,0x5715,0x9816,0xc317,0xff18,
107 0x001a,0x221b,0x001d,
111 static u16 cseq_800x600x24[] VAR16 = {
112 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1507,
113 0x230b,0x230c,0x230d,0x230e,
114 0x0412,0x0013,0x2017,
115 0x141b,0x141c,0x141d,0x141e,
118 static u16 ccrtc_800x600x24[] VAR16 = {
119 0x2311,0x7d00,0x6301,0x6302,0x8003,0x6b04,0x1a05,0x9806,0xf007,
120 0x6009,0x000c,0x000d,
121 0x7d10,0x5712,0x2c13,0x4014,0x5715,0x9816,0xc317,0xff18,
122 0x001a,0x321b,0x001d,
126 static u16 cseq_1024x768x8[] VAR16 = {
127 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
128 0x760b,0x760c,0x760d,0x760e,
129 0x0412,0x0013,0x2017,
130 0x341b,0x341c,0x341d,0x341e,
133 static u16 ccrtc_1024x768x8[] VAR16 = {
134 0x2911,0xa300,0x7f01,0x7f02,0x8603,0x8304,0x9405,0x2406,0xf507,
135 0x6009,0x000c,0x000d,
136 0x0310,0xff12,0x8013,0x4014,0xff15,0x2416,0xc317,0xff18,
137 0x001a,0x221b,0x001d,
141 static u16 cseq_1024x768x16[] VAR16 = {
142 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1707,
143 0x760b,0x760c,0x760d,0x760e,
144 0x0412,0x0013,0x2017,
145 0x341b,0x341c,0x341d,0x341e,
148 static u16 ccrtc_1024x768x16[] VAR16 = {
149 0x2911,0xa300,0x7f01,0x7f02,0x8603,0x8304,0x9405,0x2406,0xf507,
150 0x6009,0x000c,0x000d,
151 0x0310,0xff12,0x0013,0x4014,0xff15,0x2416,0xc317,0xff18,
152 0x001a,0x321b,0x001d,
156 static u16 cseq_1024x768x24[] VAR16 = {
157 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1507,
158 0x760b,0x760c,0x760d,0x760e,
159 0x0412,0x0013,0x2017,
160 0x341b,0x341c,0x341d,0x341e,
163 static u16 ccrtc_1024x768x24[] VAR16 = {
164 0x2911,0xa300,0x7f01,0x7f02,0x8603,0x8304,0x9405,0x2406,0xf507,
165 0x6009,0x000c,0x000d,
166 0x0310,0xff12,0x8013,0x4014,0xff15,0x2416,0xc317,0xff18,
167 0x001a,0x321b,0x001d,
171 static u16 cseq_1280x1024x8[] VAR16 = {
172 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
173 0x760b,0x760c,0x760d,0x760e,
174 0x0412,0x0013,0x2017,
175 0x341b,0x341c,0x341d,0x341e,
178 static u16 ccrtc_1280x1024x8[] VAR16 = {
179 0x2911,0xc300,0x9f01,0x9f02,0x8603,0x8304,0x9405,0x2406,0xf707,
180 0x6009,0x000c,0x000d,
181 0x0310,0xff12,0xa013,0x4014,0xff15,0x2416,0xc317,0xff18,
182 0x001a,0x221b,0x001d,
186 static u16 cseq_1280x1024x16[] VAR16 = {
187 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1707,
188 0x760b,0x760c,0x760d,0x760e,
189 0x0412,0x0013,0x2017,
190 0x341b,0x341c,0x341d,0x341e,
193 static u16 ccrtc_1280x1024x16[] VAR16 = {
194 0x2911,0xc300,0x9f01,0x9f02,0x8603,0x8304,0x9405,0x2406,0xf707,
195 0x6009,0x000c,0x000d,
196 0x0310,0xff12,0x4013,0x4014,0xff15,0x2416,0xc317,0xff18,
197 0x001a,0x321b,0x001d,
202 static u16 cseq_1600x1200x8[] VAR16 = {
203 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
204 0x760b,0x760c,0x760d,0x760e,
205 0x0412,0x0013,0x2017,
206 0x341b,0x341c,0x341d,0x341e,
209 static u16 ccrtc_1600x1200x8[] VAR16 = {
210 0x2911,0xc300,0x9f01,0x9f02,0x8603,0x8304,0x9405,0x2406,0xf707,
211 0x6009,0x000c,0x000d,
212 0x0310,0xff12,0xa013,0x4014,0xff15,0x2416,0xc317,0xff18,
213 0x001a,0x221b,0x001d,
217 struct cirrus_mode_s {
219 struct vgamode_s info;
221 u16 hidden_dac; /* 0x3c6 */
222 u16 *seq; /* 0x3c4 */
223 u16 *graph; /* 0x3ce */
224 u16 *crtc; /* 0x3d4 */
227 static struct cirrus_mode_s cirrus_modes[] VAR16 = {
228 {0x5f,{MM_PACKED,640,480,8},0x00,
229 cseq_640x480x8,cgraph_svgacolor,ccrtc_640x480x8},
230 {0x64,{MM_DIRECT,640,480,16},0xe1,
231 cseq_640x480x16,cgraph_svgacolor,ccrtc_640x480x16},
232 {0x66,{MM_DIRECT,640,480,15},0xf0,
233 cseq_640x480x16,cgraph_svgacolor,ccrtc_640x480x16},
234 {0x71,{MM_DIRECT,640,480,24},0xe5,
235 cseq_640x480x24,cgraph_svgacolor,ccrtc_640x480x24},
237 {0x5c,{MM_PACKED,800,600,8},0x00,
238 cseq_800x600x8,cgraph_svgacolor,ccrtc_800x600x8},
239 {0x65,{MM_DIRECT,800,600,16},0xe1,
240 cseq_800x600x16,cgraph_svgacolor,ccrtc_800x600x16},
241 {0x67,{MM_DIRECT,800,600,15},0xf0,
242 cseq_800x600x16,cgraph_svgacolor,ccrtc_800x600x16},
244 {0x60,{MM_PACKED,1024,768,8},0x00,
245 cseq_1024x768x8,cgraph_svgacolor,ccrtc_1024x768x8},
246 {0x74,{MM_DIRECT,1024,768,16},0xe1,
247 cseq_1024x768x16,cgraph_svgacolor,ccrtc_1024x768x16},
248 {0x68,{MM_DIRECT,1024,768,15},0xf0,
249 cseq_1024x768x16,cgraph_svgacolor,ccrtc_1024x768x16},
251 {0x78,{MM_DIRECT,800,600,24},0xe5,
252 cseq_800x600x24,cgraph_svgacolor,ccrtc_800x600x24},
253 {0x79,{MM_DIRECT,1024,768,24},0xe5,
254 cseq_1024x768x24,cgraph_svgacolor,ccrtc_1024x768x24},
256 {0x6d,{MM_PACKED,1280,1024,8},0x00,
257 cseq_1280x1024x8,cgraph_svgacolor,ccrtc_1280x1024x8},
258 {0x69,{MM_DIRECT,1280,1024,15},0xf0,
259 cseq_1280x1024x16,cgraph_svgacolor,ccrtc_1280x1024x16},
260 {0x75,{MM_DIRECT,1280,1024,16},0xe1,
261 cseq_1280x1024x16,cgraph_svgacolor,ccrtc_1280x1024x16},
263 {0x7b,{MM_PACKED,1600,1200,8},0x00,
264 cseq_1600x1200x8,cgraph_svgacolor,ccrtc_1600x1200x8},
267 static struct cirrus_mode_s mode_switchback VAR16 =
268 {0xfe,{0xff},0,cseq_vga,cgraph_vga,ccrtc_vga};
272 } cirrus_vesa_modelist[] VAR16 = {
306 /****************************************************************
308 ****************************************************************/
311 cirrus_vesamode_to_mode(u16 vesamode)
314 for (i=0; i<ARRAY_SIZE(cirrus_vesa_modelist); i++)
315 if (GET_GLOBAL(cirrus_vesa_modelist[i].vesamode) == vesamode)
316 return GET_GLOBAL(cirrus_vesa_modelist[i].mode);
320 static struct cirrus_mode_s *
321 cirrus_get_modeentry(int mode)
323 int transmode = cirrus_vesamode_to_mode(mode);
326 struct cirrus_mode_s *table_g = cirrus_modes;
327 while (table_g < &cirrus_modes[ARRAY_SIZE(cirrus_modes)]) {
328 u16 tmode = GET_GLOBAL(table_g->mode);
337 clext_find_mode(int mode)
339 struct cirrus_mode_s *table_g = cirrus_get_modeentry(mode);
341 return &table_g->info;
342 return stdvga_find_mode(mode);
346 cirrus_switch_mode_setregs(u16 *data, u16 port)
349 u16 val = GET_GLOBAL(*data);
358 cirrus_switch_mode(struct cirrus_mode_s *table)
360 // Unlock cirrus special
361 outw(0x1206, VGAREG_SEQU_ADDRESS);
362 cirrus_switch_mode_setregs(GET_GLOBAL(table->seq), VGAREG_SEQU_ADDRESS);
363 cirrus_switch_mode_setregs(GET_GLOBAL(table->graph), VGAREG_GRDC_ADDRESS);
364 cirrus_switch_mode_setregs(GET_GLOBAL(table->crtc), stdvga_get_crtc());
366 outb(0x00, VGAREG_PEL_MASK);
367 inb(VGAREG_PEL_MASK);
368 inb(VGAREG_PEL_MASK);
369 inb(VGAREG_PEL_MASK);
370 inb(VGAREG_PEL_MASK);
371 outb(GET_GLOBAL(table->hidden_dac), VGAREG_PEL_MASK);
372 outb(0xff, VGAREG_PEL_MASK);
374 u8 memmodel = GET_GLOBAL(table->info.memmodel);
375 u8 v = stdvga_get_single_palette_reg(0x10) & 0xfe;
376 if (memmodel == MM_PLANAR)
378 else if (memmodel != MM_TEXT)
380 stdvga_set_single_palette_reg(0x10, v);
384 cirrus_get_memsize(void)
386 // get DRAM band width
387 outb(0x0f, VGAREG_SEQU_ADDRESS);
388 u8 v = inb(VGAREG_SEQU_DATA);
389 u8 x = (v >> 3) & 0x03;
401 cirrus_enable_16k_granularity(void)
403 outb(0x0b, VGAREG_GRDC_ADDRESS);
404 u8 v = inb(VGAREG_GRDC_DATA);
405 outb(v | 0x20, VGAREG_GRDC_DATA);
409 cirrus_clear_vram(u16 param)
411 cirrus_enable_16k_granularity();
412 u8 count = cirrus_get_memsize() * 4;
414 for (i=0; i<count; i++) {
415 outw((i<<8) | 0x09, VGAREG_GRDC_ADDRESS);
416 memset16_far(SEG_GRAPH, 0, param, 16 * 1024);
418 outw(0x0009, VGAREG_GRDC_ADDRESS);
422 clext_set_mode(int mode, int flags)
424 dprintf(1, "cirrus mode %d\n", mode);
425 SET_BDA(vbe_mode, 0);
426 struct cirrus_mode_s *table_g = cirrus_get_modeentry(mode);
428 cirrus_switch_mode(table_g);
429 if (!(flags & MF_LINEARFB))
430 cirrus_enable_16k_granularity();
431 if (!(flags & MF_NOCLEARMEM))
432 cirrus_clear_vram(0);
433 SET_BDA(video_mode, mode);
434 SET_BDA(vbe_mode, mode | flags);
437 cirrus_switch_mode(&mode_switchback);
438 dprintf(1, "cirrus mode switch regular\n");
439 return stdvga_set_mode(mode, flags);
445 outw(0x9206, VGAREG_SEQU_ADDRESS);
446 return inb(VGAREG_SEQU_DATA) == 0x12;
450 /****************************************************************
452 ****************************************************************/
455 cirrus_extbios_80h(struct bregs *regs)
457 u16 crtc_addr = stdvga_get_crtc();
458 outb(0x27, crtc_addr);
459 u8 v = inb(crtc_addr + 1);
473 cirrus_extbios_81h(struct bregs *regs)
480 cirrus_extbios_82h(struct bregs *regs)
482 u16 crtc_addr = stdvga_get_crtc();
483 outb(0x27, crtc_addr);
484 regs->al = inb(crtc_addr + 1) & 0x03;
489 cirrus_extbios_85h(struct bregs *regs)
491 regs->al = cirrus_get_memsize();
495 cirrus_extbios_9Ah(struct bregs *regs)
501 extern void a0h_callback(void);
503 // fatal: not implemented yet
510 cirrus_extbios_A0h(struct bregs *regs)
512 struct cirrus_mode_s *table_g = cirrus_get_modeentry(regs->al & 0x7f);
513 regs->ah = (table_g ? 1 : 0);
515 regs->di = regs->ds = regs->es = regs->bx = (u32)a0h_callback;
519 cirrus_extbios_A1h(struct bregs *regs)
521 regs->bx = 0x0e00; // IBM 8512/8513, color
525 cirrus_extbios_A2h(struct bregs *regs)
527 regs->al = 0x07; // HSync 31.5 - 64.0 kHz
531 cirrus_extbios_AEh(struct bregs *regs)
533 regs->al = 0x01; // High Refresh 75Hz
537 cirrus_extbios(struct bregs *regs)
539 // XXX - regs->bl < 0x80 or > 0xaf call regular handlers.
541 case 0x80: cirrus_extbios_80h(regs); break;
542 case 0x81: cirrus_extbios_81h(regs); break;
543 case 0x82: cirrus_extbios_82h(regs); break;
544 case 0x85: cirrus_extbios_85h(regs); break;
545 case 0x9a: cirrus_extbios_9Ah(regs); break;
546 case 0xa0: cirrus_extbios_A0h(regs); break;
547 case 0xa1: cirrus_extbios_A1h(regs); break;
548 case 0xa2: cirrus_extbios_A2h(regs); break;
549 case 0xae: cirrus_extbios_AEh(regs); break;
555 /****************************************************************
557 ****************************************************************/
560 clext_list_modes(u16 seg, u16 *dest, u16 *last)
563 for (i=0; i<ARRAY_SIZE(cirrus_vesa_modelist) && dest<last; i++) {
564 SET_FARVAR(seg, *dest, GET_GLOBAL(cirrus_vesa_modelist[i].vesamode));
567 stdvga_list_modes(seg, dest, last);
571 cirrus_get_bpp_bytes(void)
573 outb(0x07, VGAREG_SEQU_ADDRESS);
574 u8 v = inb(VGAREG_SEQU_DATA) & 0x0e;
584 cirrus_set_line_offset(u16 new_line_offset)
586 u16 crtc_addr = stdvga_get_crtc();
587 outb(0x13, crtc_addr);
588 outb(new_line_offset / 8, crtc_addr + 1);
590 outb(0x1b, crtc_addr);
591 u8 v = inb(crtc_addr + 1);
592 outb((((new_line_offset / 8) & 0x100) >> 4) | (v & 0xef), crtc_addr + 1);
596 cirrus_get_line_offset(void)
598 u16 crtc_addr = stdvga_get_crtc();
599 outb(0x13, crtc_addr);
600 u8 reg13 = inb(crtc_addr + 1);
601 outb(0x1b, crtc_addr);
602 u8 reg1b = inb(crtc_addr + 1);
604 return (((reg1b << 4) & 0x100) + reg13) * 8;
608 cirrus_get_line_offset_entry(struct cirrus_mode_s *table_g)
610 u16 *crtc = GET_GLOBAL(table_g->crtc);
615 reg13 = GET_GLOBAL(*c);
616 if ((reg13 & 0xff) == 0x13)
625 reg1b = GET_GLOBAL(*c);
626 if ((reg1b & 0xff) == 0x1b)
632 return (((reg1b << 4) & 0x100) + reg13) * 8;
636 cirrus_set_start_addr(u32 addr)
638 u16 crtc_addr = stdvga_get_crtc();
639 outb(0x0d, crtc_addr);
640 outb(addr, crtc_addr + 1);
642 outb(0x0c, crtc_addr);
643 outb(addr>>8, crtc_addr + 1);
645 outb(0x1d, crtc_addr);
646 u8 v = inb(crtc_addr + 1);
647 outb(((addr & 0x0800) >> 4) | (v & 0x7f), crtc_addr + 1);
649 outb(0x1b, crtc_addr);
650 v = inb(crtc_addr + 1);
651 outb(((addr & 0x0100) >> 8) | ((addr & 0x0600) >> 7) | (v & 0xf2)
656 cirrus_get_start_addr(void)
658 u16 crtc_addr = stdvga_get_crtc();
659 outb(0x0c, crtc_addr);
660 u8 b2 = inb(crtc_addr + 1);
662 outb(0x0d, crtc_addr);
663 u8 b1 = inb(crtc_addr + 1);
665 outb(0x1b, crtc_addr);
666 u8 b3 = inb(crtc_addr + 1);
668 outb(0x1d, crtc_addr);
669 u8 b4 = inb(crtc_addr + 1);
671 return (b1 | (b2<<8) | ((b3 & 0x01) << 16) | ((b3 & 0x0c) << 15)
672 | ((b4 & 0x80) << 12));
676 cirrus_vesa_05h(struct bregs *regs)
682 if (regs->dx >= 0x100)
684 outw((regs->dx << 8) | (regs->bl + 9), VGAREG_GRDC_ADDRESS);
685 } else if (regs->bh == 1) {
687 outb(regs->bl + 9, VGAREG_GRDC_ADDRESS);
688 regs->dx = inb(VGAREG_GRDC_DATA);
699 cirrus_vesa_06h(struct bregs *regs)
706 if (regs->bl == 0x00) {
707 cirrus_set_line_offset(cirrus_get_bpp_bytes() * regs->cx);
708 } else if (regs->bl == 0x02) {
709 cirrus_set_line_offset(regs->cx);
712 u32 v = cirrus_get_line_offset();
713 regs->cx = v / cirrus_get_bpp_bytes();
715 regs->dx = (cirrus_get_memsize() * 64 * 1024) / v;
720 cirrus_vesa_07h(struct bregs *regs)
722 if (regs->bl == 0x80 || regs->bl == 0x00) {
723 u32 addr = (cirrus_get_bpp_bytes() * regs->cx
724 + cirrus_get_line_offset() * regs->dx);
725 cirrus_set_start_addr(addr / 4);
726 } else if (regs->bl == 0x01) {
727 u32 addr = cirrus_get_start_addr() * 4;
728 u32 linelength = cirrus_get_line_offset();
729 regs->dx = addr / linelength;
730 regs->cx = (addr % linelength) / cirrus_get_bpp_bytes();
740 cirrus_vesa_10h(struct bregs *regs)
742 if (regs->bl == 0x00) {
747 if (regs->bl == 0x01) {
748 SET_BDA(vbe_flag, regs->bh);
752 if (regs->bl == 0x02) {
753 regs->bh = GET_BDA(vbe_flag);
761 cirrus_vesa_not_handled(struct bregs *regs)
768 cirrus_vesa(struct bregs *regs)
771 case 0x05: cirrus_vesa_05h(regs); break;
772 case 0x06: cirrus_vesa_06h(regs); break;
773 case 0x07: cirrus_vesa_07h(regs); break;
774 case 0x10: cirrus_vesa_10h(regs); break;
775 default: cirrus_vesa_not_handled(regs); break;
780 /****************************************************************
782 ****************************************************************/
787 int ret = stdvga_init();
791 dprintf(1, "cirrus init\n");
792 if (! cirrus_check())
794 dprintf(1, "cirrus init 2\n");
796 u16 totalmem = cirrus_get_memsize();
797 SET_VGA(VBE_total_memory, totalmem * 64 * 1024);
798 SET_VGA(VBE_win_granularity, 16);
801 outb(0x0f, VGAREG_SEQU_ADDRESS);
802 u8 v = inb(VGAREG_SEQU_DATA);
803 outb(((v & 0x18) << 8) | 0x0a, VGAREG_SEQU_ADDRESS);
805 outw(0x0007, VGAREG_SEQU_ADDRESS);
807 outw(0x0431, VGAREG_GRDC_ADDRESS);
808 outw(0x0031, VGAREG_GRDC_ADDRESS);