#include "bregs.h" // struct bregs
#include "vbe.h" // struct vbe_info
#include "stdvga.h" // VGAREG_SEQU_ADDRESS
+#include "pci.h" // pci_config_readl
+#include "pci_regs.h" // PCI_BASE_ADDRESS_0
/****************************************************************
0x2c11,
0x5f00,0x4f01,0x4f02,0x8003,0x5204,0x1e05,0x0b06,0x3e07,
0x4009,0x000c,0x000d,
- 0xea10,0xdf12,0x0013,0x4014,0xdf15,0x0b16,0xc317,0xff18,
- 0x001a,0x321b,0x001d,
+ 0xea10,0xdf12,0xf013,0x4014,0xdf15,0x0b16,0xc317,0xff18,
+ 0x001a,0x221b,0x001d,
0xffff
};
/* 800x600x8 */
static u16 ccrtc_1600x1200x8[] VAR16 = {
0x2911,0xc300,0x9f01,0x9f02,0x8603,0x8304,0x9405,0x2406,0xf707,
0x6009,0x000c,0x000d,
- 0x0310,0xff12,0xa013,0x4014,0xff15,0x2416,0xc317,0xff18,
+ 0x0310,0xff12,0xc813,0x4014,0xff15,0x2416,0xc317,0xff18,
0x001a,0x221b,0x001d,
0xffff
};
cirrus_switch_mode(struct cirrus_mode_s *table)
{
// Unlock cirrus special
- outw(0x1206, VGAREG_SEQU_ADDRESS);
+ stdvga_sequ_write(0x06, 0x12);
cirrus_switch_mode_setregs(GET_GLOBAL(table->seq), VGAREG_SEQU_ADDRESS);
cirrus_switch_mode_setregs(GET_GLOBAL(table->graph), VGAREG_GRDC_ADDRESS);
cirrus_switch_mode_setregs(GET_GLOBAL(table->crtc), stdvga_get_crtc());
- outb(0x00, VGAREG_PEL_MASK);
- inb(VGAREG_PEL_MASK);
- inb(VGAREG_PEL_MASK);
- inb(VGAREG_PEL_MASK);
- inb(VGAREG_PEL_MASK);
- outb(GET_GLOBAL(table->hidden_dac), VGAREG_PEL_MASK);
- outb(0xff, VGAREG_PEL_MASK);
+ stdvga_pelmask_write(0x00);
+ stdvga_pelmask_read();
+ stdvga_pelmask_read();
+ stdvga_pelmask_read();
+ stdvga_pelmask_read();
+ stdvga_pelmask_write(GET_GLOBAL(table->hidden_dac));
+ stdvga_pelmask_write(0xff);
u8 memmodel = GET_GLOBAL(table->info.memmodel);
- u8 v = stdvga_get_single_palette_reg(0x10) & 0xfe;
+ u8 on = 0;
if (memmodel == MM_PLANAR)
- v |= 0x41;
+ on = 0x41;
else if (memmodel != MM_TEXT)
- v |= 0x01;
- stdvga_set_single_palette_reg(0x10, v);
+ on = 0x01;
+ stdvga_attr_mask(0x10, 0x01, on);
}
static u8
cirrus_get_memsize(void)
{
// get DRAM band width
- outb(0x0f, VGAREG_SEQU_ADDRESS);
- u8 v = inb(VGAREG_SEQU_DATA);
+ u8 v = stdvga_sequ_read(0x0f);
u8 x = (v >> 3) & 0x03;
- if (x == 0x03) {
- if (v & 0x80)
- // 4MB
- return 0x40;
- // 2MB
- return 0x20;
- }
+ if (x == 0x03 && v & 0x80)
+ // 4MB
+ return 0x40;
return 0x04 << x;
}
static void
cirrus_enable_16k_granularity(void)
{
- outb(0x0b, VGAREG_GRDC_ADDRESS);
- u8 v = inb(VGAREG_GRDC_DATA);
- outb(v | 0x20, VGAREG_GRDC_DATA);
+ stdvga_grdc_mask(0x0b, 0x00, 0x20);
}
static void
cirrus_clear_vram(u16 param)
{
cirrus_enable_16k_granularity();
- u8 count = cirrus_get_memsize() * 4;
+ u8 count = GET_GLOBAL(VBE_total_memory) / (16 * 1024);
u8 i;
for (i=0; i<count; i++) {
- outw((i<<8) | 0x09, VGAREG_GRDC_ADDRESS);
+ stdvga_grdc_write(0x09, i);
memset16_far(SEG_GRAPH, 0, param, 16 * 1024);
}
- outw(0x0009, VGAREG_GRDC_ADDRESS);
+ stdvga_grdc_write(0x09, 0x00);
}
int
clext_set_mode(int mode, int flags)
{
- dprintf(1, "cirrus mode %d\n", mode);
+ dprintf(1, "cirrus mode %x\n", mode);
SET_BDA(vbe_mode, 0);
struct cirrus_mode_s *table_g = cirrus_get_modeentry(mode);
if (table_g) {
static int
cirrus_check(void)
{
- outw(0x9206, VGAREG_SEQU_ADDRESS);
- return inb(VGAREG_SEQU_DATA) == 0x12;
+ stdvga_sequ_write(0x06, 0x92);
+ return stdvga_sequ_read(0x06) == 0x12;
}
****************************************************************/
static void
-cirrus_extbios_80h(struct bregs *regs)
+clext_101280(struct bregs *regs)
{
- u16 crtc_addr = stdvga_get_crtc();
- outb(0x27, crtc_addr);
- u8 v = inb(crtc_addr + 1);
+ u8 v = stdvga_crtc_read(stdvga_get_crtc(), 0x27);
if (v == 0xa0)
// 5430
regs->ax = 0x0032;
}
static void
-cirrus_extbios_81h(struct bregs *regs)
+clext_101281(struct bregs *regs)
{
// XXX
regs->ax = 0x0100;
}
static void
-cirrus_extbios_82h(struct bregs *regs)
+clext_101282(struct bregs *regs)
{
- u16 crtc_addr = stdvga_get_crtc();
- outb(0x27, crtc_addr);
- regs->al = inb(crtc_addr + 1) & 0x03;
+ regs->al = stdvga_crtc_read(stdvga_get_crtc(), 0x27) & 0x03;
regs->ah = 0xAF;
}
static void
-cirrus_extbios_85h(struct bregs *regs)
+clext_101285(struct bregs *regs)
{
- regs->al = cirrus_get_memsize();
+ regs->al = GET_GLOBAL(VBE_total_memory) / (64*1024);
}
static void
-cirrus_extbios_9Ah(struct bregs *regs)
+clext_10129a(struct bregs *regs)
{
regs->ax = 0x4060;
regs->cx = 0x1132;
"retf");
static void
-cirrus_extbios_A0h(struct bregs *regs)
+clext_1012a0(struct bregs *regs)
{
struct cirrus_mode_s *table_g = cirrus_get_modeentry(regs->al & 0x7f);
regs->ah = (table_g ? 1 : 0);
}
static void
-cirrus_extbios_A1h(struct bregs *regs)
+clext_1012a1(struct bregs *regs)
{
regs->bx = 0x0e00; // IBM 8512/8513, color
}
static void
-cirrus_extbios_A2h(struct bregs *regs)
+clext_1012a2(struct bregs *regs)
{
regs->al = 0x07; // HSync 31.5 - 64.0 kHz
}
static void
-cirrus_extbios_AEh(struct bregs *regs)
+clext_1012ae(struct bregs *regs)
{
regs->al = 0x01; // High Refresh 75Hz
}
+static void
+clext_1012XX(struct bregs *regs)
+{
+ debug_stub(regs);
+}
+
void
-cirrus_extbios(struct bregs *regs)
+clext_1012(struct bregs *regs)
{
- // XXX - regs->bl < 0x80 or > 0xaf call regular handlers.
switch (regs->bl) {
- case 0x80: cirrus_extbios_80h(regs); break;
- case 0x81: cirrus_extbios_81h(regs); break;
- case 0x82: cirrus_extbios_82h(regs); break;
- case 0x85: cirrus_extbios_85h(regs); break;
- case 0x9a: cirrus_extbios_9Ah(regs); break;
- case 0xa0: cirrus_extbios_A0h(regs); break;
- case 0xa1: cirrus_extbios_A1h(regs); break;
- case 0xa2: cirrus_extbios_A2h(regs); break;
- case 0xae: cirrus_extbios_AEh(regs); break;
- default: break;
+ case 0x80: clext_101280(regs); break;
+ case 0x81: clext_101281(regs); break;
+ case 0x82: clext_101282(regs); break;
+ case 0x85: clext_101285(regs); break;
+ case 0x9a: clext_10129a(regs); break;
+ case 0xa0: clext_1012a0(regs); break;
+ case 0xa1: clext_1012a1(regs); break;
+ case 0xa2: clext_1012a2(regs); break;
+ case 0xae: clext_1012ae(regs); break;
+ default: clext_1012XX(regs); break;
}
}
static u8
cirrus_get_bpp_bytes(void)
{
- outb(0x07, VGAREG_SEQU_ADDRESS);
- u8 v = inb(VGAREG_SEQU_DATA) & 0x0e;
+ u8 v = stdvga_sequ_read(0x07) & 0x0e;
if (v == 0x06)
v &= 0x02;
v >>= 1;
static void
cirrus_set_line_offset(u16 new_line_offset)
{
+ new_line_offset /= 8;
u16 crtc_addr = stdvga_get_crtc();
- outb(0x13, crtc_addr);
- outb(new_line_offset / 8, crtc_addr + 1);
-
- outb(0x1b, crtc_addr);
- u8 v = inb(crtc_addr + 1);
- outb((((new_line_offset / 8) & 0x100) >> 4) | (v & 0xef), crtc_addr + 1);
+ stdvga_crtc_write(crtc_addr, 0x13, new_line_offset);
+ stdvga_crtc_mask(crtc_addr, 0x1b, 0x10, (new_line_offset & 0x100) >> 4);
}
static u16
cirrus_get_line_offset(void)
{
u16 crtc_addr = stdvga_get_crtc();
- outb(0x13, crtc_addr);
- u8 reg13 = inb(crtc_addr + 1);
- outb(0x1b, crtc_addr);
- u8 reg1b = inb(crtc_addr + 1);
-
- return (((reg1b << 4) & 0x100) + reg13) * 8;
-}
-
-u16
-cirrus_get_line_offset_entry(struct cirrus_mode_s *table_g)
-{
- u16 *crtc = GET_GLOBAL(table_g->crtc);
-
- u16 *c = crtc;
- u16 reg13;
- for (;;) {
- reg13 = GET_GLOBAL(*c);
- if ((reg13 & 0xff) == 0x13)
- break;
- c++;
- }
- reg13 >>= 8;
-
- c = crtc;
- u16 reg1b;
- for (;;) {
- reg1b = GET_GLOBAL(*c);
- if ((reg1b & 0xff) == 0x1b)
- break;
- c++;
- }
- reg1b >>= 8;
-
- return (((reg1b << 4) & 0x100) + reg13) * 8;
+ u8 reg13 = stdvga_crtc_read(crtc_addr, 0x13);
+ u8 reg1b = stdvga_crtc_read(crtc_addr, 0x1b);
+ return (((reg1b & 0x10) << 4) + reg13) * 8;
}
static void
cirrus_set_start_addr(u32 addr)
{
u16 crtc_addr = stdvga_get_crtc();
- outb(0x0d, crtc_addr);
- outb(addr, crtc_addr + 1);
-
- outb(0x0c, crtc_addr);
- outb(addr>>8, crtc_addr + 1);
-
- outb(0x1d, crtc_addr);
- u8 v = inb(crtc_addr + 1);
- outb(((addr & 0x0800) >> 4) | (v & 0x7f), crtc_addr + 1);
-
- outb(0x1b, crtc_addr);
- v = inb(crtc_addr + 1);
- outb(((addr & 0x0100) >> 8) | ((addr & 0x0600) >> 7) | (v & 0xf2)
- , crtc_addr + 1);
+ stdvga_crtc_write(crtc_addr, 0x0d, addr);
+ stdvga_crtc_write(crtc_addr, 0x0c, addr >> 8);
+ stdvga_crtc_mask(crtc_addr, 0x1d, 0x80, (addr & 0x0800) >> 4);
+ stdvga_crtc_mask(crtc_addr, 0x1b, 0x0d
+ , ((addr & 0x0100) >> 8) | ((addr & 0x0600) >> 7));
}
static u32
cirrus_get_start_addr(void)
{
u16 crtc_addr = stdvga_get_crtc();
- outb(0x0c, crtc_addr);
- u8 b2 = inb(crtc_addr + 1);
-
- outb(0x0d, crtc_addr);
- u8 b1 = inb(crtc_addr + 1);
-
- outb(0x1b, crtc_addr);
- u8 b3 = inb(crtc_addr + 1);
-
- outb(0x1d, crtc_addr);
- u8 b4 = inb(crtc_addr + 1);
-
+ u8 b2 = stdvga_crtc_read(crtc_addr, 0x0c);
+ u8 b1 = stdvga_crtc_read(crtc_addr, 0x0d);
+ u8 b3 = stdvga_crtc_read(crtc_addr, 0x1b);
+ u8 b4 = stdvga_crtc_read(crtc_addr, 0x1d);
return (b1 | (b2<<8) | ((b3 & 0x01) << 16) | ((b3 & 0x0c) << 15)
| ((b4 & 0x80) << 12));
}
// set mempage
if (regs->dx >= 0x100)
goto fail;
- outw((regs->dx << 8) | (regs->bl + 9), VGAREG_GRDC_ADDRESS);
+ stdvga_grdc_write(regs->bl + 9, regs->dx);
} else if (regs->bh == 1) {
// get mempage
- outb(regs->bl + 9, VGAREG_GRDC_ADDRESS);
- regs->dx = inb(VGAREG_GRDC_DATA);
+ regs->dx = stdvga_grdc_read(regs->bl + 9);
} else
goto fail;
u32 v = cirrus_get_line_offset();
regs->cx = v / cirrus_get_bpp_bytes();
regs->bx = v;
- regs->dx = (cirrus_get_memsize() * 64 * 1024) / v;
+ regs->dx = GET_GLOBAL(VBE_total_memory) / v;
regs->ax = 0x004f;
}
return -1;
dprintf(1, "cirrus init 2\n");
+ u32 lfb_addr = 0;
+ int bdf = GET_GLOBAL(VgaBDF);
+ if (CONFIG_VGA_PCI && bdf >= 0)
+ lfb_addr = (pci_config_readl(bdf, PCI_BASE_ADDRESS_0)
+ & PCI_BASE_ADDRESS_MEM_MASK);
+ SET_VGA(VBE_framebuffer, lfb_addr);
u16 totalmem = cirrus_get_memsize();
SET_VGA(VBE_total_memory, totalmem * 64 * 1024);
SET_VGA(VBE_win_granularity, 16);
// memory setup
- outb(0x0f, VGAREG_SEQU_ADDRESS);
- u8 v = inb(VGAREG_SEQU_DATA);
- outb(((v & 0x18) << 8) | 0x0a, VGAREG_SEQU_ADDRESS);
+ stdvga_sequ_write(0x0a, stdvga_sequ_read(0x0f) & 0x18);
// set vga mode
- outw(0x0007, VGAREG_SEQU_ADDRESS);
+ stdvga_sequ_write(0x07, 0x00);
// reset bitblt
- outw(0x0431, VGAREG_GRDC_ADDRESS);
- outw(0x0031, VGAREG_GRDC_ADDRESS);
+ stdvga_grdc_write(0x31, 0x04);
+ stdvga_grdc_write(0x31, 0x00);
return 0;
}
projects / seabios.git / blobdiff