vgasrc/vgaio.c

   1 // VGA io port access
   2 //
   3 // Copyright (C) 2009  Kevin O'Connor <kevin@koconnor.net>
   4 // Copyright (C) 2001-2008 the LGPL VGABios developers Team
   5 //
   6 // This file may be distributed under the terms of the GNU LGPLv3 license.
   7
   8 #include "ioport.h" // outb
   9 #include "farptr.h" // SET_FARVAR
  10 #include "biosvar.h" // GET_BDA
  11 #include "vgatables.h" // VGAREG_*
  12
  13
  14 /****************************************************************
  15  * Attribute control
  16  ****************************************************************/
  17
  18 void
  19 vgahw_screen_disable()
  20 {
  21     inb(VGAREG_ACTL_RESET);
  22     outb(0x00, VGAREG_ACTL_ADDRESS);
  23 }
  24
  25 void
  26 vgahw_screen_enable()
  27 {
  28     inb(VGAREG_ACTL_RESET);
  29     outb(0x20, VGAREG_ACTL_ADDRESS);
  30 }
  31
  32 void
  33 vgahw_set_border_color(u8 color)
  34 {
  35     inb(VGAREG_ACTL_RESET);
  36     outb(0x00, VGAREG_ACTL_ADDRESS);
  37     u8 v1 = color & 0x0f;
  38     if (v1 & 0x08)
  39         v1 += 0x08;
  40     outb(v1, VGAREG_ACTL_WRITE_DATA);
  41
  42     u8 v2 = color & 0x10;
  43     int i;
  44     for (i = 1; i < 4; i++) {
  45         outb(i, VGAREG_ACTL_ADDRESS);
  46
  47         u8 cur = inb(VGAREG_ACTL_READ_DATA);
  48         cur &= 0xef;
  49         cur |= v2;
  50         outb(cur, VGAREG_ACTL_WRITE_DATA);
  51     }
  52     outb(0x20, VGAREG_ACTL_ADDRESS);
  53 }
  54
  55 void
  56 vgahw_set_overscan_border_color(u8 color)
  57 {
  58     inb(VGAREG_ACTL_RESET);
  59     outb(0x11, VGAREG_ACTL_ADDRESS);
  60     outb(color, VGAREG_ACTL_WRITE_DATA);
  61     outb(0x20, VGAREG_ACTL_ADDRESS);
  62 }
  63
  64 u8
  65 vgahw_get_overscan_border_color()
  66 {
  67     inb(VGAREG_ACTL_RESET);
  68     outb(0x11, VGAREG_ACTL_ADDRESS);
  69     u8 v = inb(VGAREG_ACTL_READ_DATA);
  70     inb(VGAREG_ACTL_RESET);
  71     outb(0x20, VGAREG_ACTL_ADDRESS);
  72     return v;
  73 }
  74
  75 void
  76 vgahw_set_palette(u8 palid)
  77 {
  78     inb(VGAREG_ACTL_RESET);
  79     palid &= 0x01;
  80     int i;
  81     for (i = 1; i < 4; i++) {
  82         outb(i, VGAREG_ACTL_ADDRESS);
  83
  84         u8 v = inb(VGAREG_ACTL_READ_DATA);
  85         v &= 0xfe;
  86         v |= palid;
  87         outb(v, VGAREG_ACTL_WRITE_DATA);
  88     }
  89     outb(0x20, VGAREG_ACTL_ADDRESS);
  90 }
  91
  92 void
  93 vgahw_set_single_palette_reg(u8 reg, u8 val)
  94 {
  95     inb(VGAREG_ACTL_RESET);
  96     outb(reg, VGAREG_ACTL_ADDRESS);
  97     outb(val, VGAREG_ACTL_WRITE_DATA);
  98     outb(0x20, VGAREG_ACTL_ADDRESS);
  99 }
 100
 101 u8
 102 vgahw_get_single_palette_reg(u8 reg)
 103 {
 104     inb(VGAREG_ACTL_RESET);
 105     outb(reg, VGAREG_ACTL_ADDRESS);
 106     u8 v = inb(VGAREG_ACTL_READ_DATA);
 107     inb(VGAREG_ACTL_RESET);
 108     outb(0x20, VGAREG_ACTL_ADDRESS);
 109     return v;
 110 }
 111
 112 void
 113 vgahw_set_all_palette_reg(u16 seg, u8 *data_far)
 114 {
 115     inb(VGAREG_ACTL_RESET);
 116     int i;
 117     for (i = 0; i < 0x10; i++) {
 118         outb(i, VGAREG_ACTL_ADDRESS);
 119         u8 val = GET_FARVAR(seg, *data_far);
 120         outb(val, VGAREG_ACTL_WRITE_DATA);
 121         data_far++;
 122     }
 123     outb(0x11, VGAREG_ACTL_ADDRESS);
 124     outb(GET_FARVAR(seg, *data_far), VGAREG_ACTL_WRITE_DATA);
 125     outb(0x20, VGAREG_ACTL_ADDRESS);
 126 }
 127
 128 void
 129 vgahw_get_all_palette_reg(u16 seg, u8 *data_far)
 130 {
 131     int i;
 132     for (i = 0; i < 0x10; i++) {
 133         inb(VGAREG_ACTL_RESET);
 134         outb(i, VGAREG_ACTL_ADDRESS);
 135         SET_FARVAR(seg, *data_far, inb(VGAREG_ACTL_READ_DATA));
 136         data_far++;
 137     }
 138     inb(VGAREG_ACTL_RESET);
 139     outb(0x11, VGAREG_ACTL_ADDRESS);
 140     SET_FARVAR(seg, *data_far, inb(VGAREG_ACTL_READ_DATA));
 141     inb(VGAREG_ACTL_RESET);
 142     outb(0x20, VGAREG_ACTL_ADDRESS);
 143 }
 144
 145 void
 146 vgahw_toggle_intensity(u8 flag)
 147 {
 148     inb(VGAREG_ACTL_RESET);
 149     outb(0x10, VGAREG_ACTL_ADDRESS);
 150     u8 val = (inb(VGAREG_ACTL_READ_DATA) & 0xf7) | ((flag & 0x01) << 3);
 151     outb(val, VGAREG_ACTL_WRITE_DATA);
 152     outb(0x20, VGAREG_ACTL_ADDRESS);
 153 }
 154
 155 void
 156 vgahw_select_video_dac_color_page(u8 flag, u8 data)
 157 {
 158     inb(VGAREG_ACTL_RESET);
 159     outb(0x10, VGAREG_ACTL_ADDRESS);
 160     u8 val = inb(VGAREG_ACTL_READ_DATA);
 161     if (!(flag & 0x01)) {
 162         // select paging mode
 163         val = (val & 0x7f) | (data << 7);
 164         outb(val, VGAREG_ACTL_WRITE_DATA);
 165         outb(0x20, VGAREG_ACTL_ADDRESS);
 166         return;
 167     }
 168     // select page
 169     inb(VGAREG_ACTL_RESET);
 170     outb(0x14, VGAREG_ACTL_ADDRESS);
 171     if (!(val & 0x80))
 172         data <<= 2;
 173     data &= 0x0f;
 174     outb(data, VGAREG_ACTL_WRITE_DATA);
 175     outb(0x20, VGAREG_ACTL_ADDRESS);
 176 }
 177
 178 void
 179 vgahw_read_video_dac_state(u8 *pmode, u8 *curpage)
 180 {
 181     inb(VGAREG_ACTL_RESET);
 182     outb(0x10, VGAREG_ACTL_ADDRESS);
 183     u8 val1 = inb(VGAREG_ACTL_READ_DATA) >> 7;
 184
 185     inb(VGAREG_ACTL_RESET);
 186     outb(0x14, VGAREG_ACTL_ADDRESS);
 187     u8 val2 = inb(VGAREG_ACTL_READ_DATA) & 0x0f;
 188     if (!(val1 & 0x01))
 189         val2 >>= 2;
 190
 191     inb(VGAREG_ACTL_RESET);
 192     outb(0x20, VGAREG_ACTL_ADDRESS);
 193
 194     *pmode = val1;
 195     *curpage = val2;
 196 }
 197
 198
 199 /****************************************************************
 200  * DAC control
 201  ****************************************************************/
 202
 203 void
 204 vgahw_set_dac_regs(u16 seg, u8 *data_far, u8 start, int count)
 205 {
 206     outb(start, VGAREG_DAC_WRITE_ADDRESS);
 207     while (count) {
 208         outb(GET_FARVAR(seg, *data_far), VGAREG_DAC_DATA);
 209         data_far++;
 210         outb(GET_FARVAR(seg, *data_far), VGAREG_DAC_DATA);
 211         data_far++;
 212         outb(GET_FARVAR(seg, *data_far), VGAREG_DAC_DATA);
 213         data_far++;
 214         count--;
 215     }
 216 }
 217
 218 void
 219 vgahw_get_dac_regs(u16 seg, u8 *data_far, u8 start, int count)
 220 {
 221     outb(start, VGAREG_DAC_READ_ADDRESS);
 222     while (count) {
 223         SET_FARVAR(seg, *data_far, inb(VGAREG_DAC_DATA));
 224         data_far++;
 225         SET_FARVAR(seg, *data_far, inb(VGAREG_DAC_DATA));
 226         data_far++;
 227         SET_FARVAR(seg, *data_far, inb(VGAREG_DAC_DATA));
 228         data_far++;
 229         count--;
 230     }
 231 }
 232
 233 void
 234 vgahw_set_pel_mask(u8 val)
 235 {
 236     outb(val, VGAREG_PEL_MASK);
 237 }
 238
 239 u8
 240 vgahw_get_pel_mask()
 241 {
 242     return inb(VGAREG_PEL_MASK);
 243 }
 244
 245
 246 /****************************************************************
 247  * Memory control
 248  ****************************************************************/
 249
 250 void
 251 vgahw_set_text_block_specifier(u8 spec)
 252 {
 253     outw((spec << 8) | 0x03, VGAREG_SEQU_ADDRESS);
 254 }
 255
 256 void
 257 get_font_access()
 258 {
 259     outw(0x0100, VGAREG_SEQU_ADDRESS);
 260     outw(0x0402, VGAREG_SEQU_ADDRESS);
 261     outw(0x0704, VGAREG_SEQU_ADDRESS);
 262     outw(0x0300, VGAREG_SEQU_ADDRESS);
 263     outw(0x0204, VGAREG_GRDC_ADDRESS);
 264     outw(0x0005, VGAREG_GRDC_ADDRESS);
 265     outw(0x0406, VGAREG_GRDC_ADDRESS);
 266 }
 267
 268 void
 269 release_font_access()
 270 {
 271     outw(0x0100, VGAREG_SEQU_ADDRESS);
 272     outw(0x0302, VGAREG_SEQU_ADDRESS);
 273     outw(0x0304, VGAREG_SEQU_ADDRESS);
 274     outw(0x0300, VGAREG_SEQU_ADDRESS);
 275     u16 v = (inw(VGAREG_READ_MISC_OUTPUT) & 0x01) ? 0x0e : 0x0a;
 276     outw((v << 8) | 0x06, VGAREG_GRDC_ADDRESS);
 277     outw(0x0004, VGAREG_GRDC_ADDRESS);
 278     outw(0x1005, VGAREG_GRDC_ADDRESS);
 279 }
 280
 281
 282 /****************************************************************
 283  * CRTC registers
 284  ****************************************************************/
 285
 286 static u16
 287 get_crtc()
 288 {
 289     return GET_BDA(crtc_address);
 290 }
 291
 292 void
 293 vgahw_set_cursor_shape(u8 start, u8 end)
 294 {
 295     u16 crtc_addr = get_crtc();
 296     outb(0x0a, crtc_addr);
 297     outb(start, crtc_addr + 1);
 298     outb(0x0b, crtc_addr);
 299     outb(end, crtc_addr + 1);
 300 }
 301
 302 void
 303 vgahw_set_active_page(u16 address)
 304 {
 305     u16 crtc_addr = get_crtc();
 306     outb(0x0c, crtc_addr);
 307     outb((address & 0xff00) >> 8, crtc_addr + 1);
 308     outb(0x0d, crtc_addr);
 309     outb(address & 0x00ff, crtc_addr + 1);
 310 }
 311
 312 void
 313 vgahw_set_cursor_pos(u16 address)
 314 {
 315     u16 crtc_addr = get_crtc();
 316     outb(0x0e, crtc_addr);
 317     outb((address & 0xff00) >> 8, crtc_addr + 1);
 318     outb(0x0f, crtc_addr);
 319     outb(address & 0x00ff, crtc_addr + 1);
 320 }
 321
 322 void
 323 vgahw_set_scan_lines(u8 lines)
 324 {
 325     u16 crtc_addr = get_crtc();
 326     outb(0x09, crtc_addr);
 327     u8 crtc_r9 = inb(crtc_addr + 1);
 328     crtc_r9 = (crtc_r9 & 0xe0) | (lines - 1);
 329     outb(crtc_r9, crtc_addr + 1);
 330 }
 331
 332 // Get vertical display end
 333 u16
 334 vgahw_get_vde()
 335 {
 336     u16 crtc_addr = get_crtc();
 337     outb(0x12, crtc_addr);
 338     u16 vde = inb(crtc_addr + 1);
 339     outb(0x07, crtc_addr);
 340     u8 ovl = inb(crtc_addr + 1);
 341     vde += (((ovl & 0x02) << 7) + ((ovl & 0x40) << 3) + 1);
 342     return vde;
 343 }
 344
 345
 346 /****************************************************************
 347  * Misc
 348  ****************************************************************/
 349
 350 void
 351 vgahw_enable_video_addressing(u8 disable)
 352 {
 353     u8 v = (disable & 1) ? 0x00 : 0x02;
 354     u8 v2 = inb(VGAREG_READ_MISC_OUTPUT) & ~0x02;
 355     outb(v | v2, VGAREG_WRITE_MISC_OUTPUT);
 356 }
 357
 358 void
 359 vgahw_init()
 360 {
 361     // switch to color mode and enable CPU access 480 lines
 362     outb(0xc3, VGAREG_WRITE_MISC_OUTPUT);
 363     // more than 64k 3C4/04
 364     outb(0x04, VGAREG_SEQU_ADDRESS);
 365     outb(0x02, VGAREG_SEQU_DATA);
 366 }