3 // Copyright (C) 2009 Kevin O'Connor <kevin@koconnor.net>
4 // Copyright (C) 2001-2008 the LGPL VGABios developers Team
6 // This file may be distributed under the terms of the GNU LGPLv3 license.
8 #include "ioport.h" // outb
9 #include "farptr.h" // SET_FARVAR
10 #include "biosvar.h" // GET_BDA
11 #include "vgatables.h" // VGAREG_*
14 /****************************************************************
16 ****************************************************************/
19 vgahw_screen_disable()
21 inb(VGAREG_ACTL_RESET);
22 outb(0x00, VGAREG_ACTL_ADDRESS);
28 inb(VGAREG_ACTL_RESET);
29 outb(0x20, VGAREG_ACTL_ADDRESS);
33 vgahw_set_border_color(u8 color)
35 inb(VGAREG_ACTL_RESET);
36 outb(0x00, VGAREG_ACTL_ADDRESS);
40 outb(v1, VGAREG_ACTL_WRITE_DATA);
44 for (i = 1; i < 4; i++) {
45 outb(i, VGAREG_ACTL_ADDRESS);
47 u8 cur = inb(VGAREG_ACTL_READ_DATA);
50 outb(cur, VGAREG_ACTL_WRITE_DATA);
52 outb(0x20, VGAREG_ACTL_ADDRESS);
56 vgahw_set_overscan_border_color(u8 color)
58 inb(VGAREG_ACTL_RESET);
59 outb(0x11, VGAREG_ACTL_ADDRESS);
60 outb(color, VGAREG_ACTL_WRITE_DATA);
61 outb(0x20, VGAREG_ACTL_ADDRESS);
65 vgahw_get_overscan_border_color()
67 inb(VGAREG_ACTL_RESET);
68 outb(0x11, VGAREG_ACTL_ADDRESS);
69 u8 v = inb(VGAREG_ACTL_READ_DATA);
70 inb(VGAREG_ACTL_RESET);
71 outb(0x20, VGAREG_ACTL_ADDRESS);
76 vgahw_set_palette(u8 palid)
78 inb(VGAREG_ACTL_RESET);
81 for (i = 1; i < 4; i++) {
82 outb(i, VGAREG_ACTL_ADDRESS);
84 u8 v = inb(VGAREG_ACTL_READ_DATA);
87 outb(v, VGAREG_ACTL_WRITE_DATA);
89 outb(0x20, VGAREG_ACTL_ADDRESS);
93 vgahw_set_single_palette_reg(u8 reg, u8 val)
95 inb(VGAREG_ACTL_RESET);
96 outb(reg, VGAREG_ACTL_ADDRESS);
97 outb(val, VGAREG_ACTL_WRITE_DATA);
98 outb(0x20, VGAREG_ACTL_ADDRESS);
102 vgahw_get_single_palette_reg(u8 reg)
104 inb(VGAREG_ACTL_RESET);
105 outb(reg, VGAREG_ACTL_ADDRESS);
106 u8 v = inb(VGAREG_ACTL_READ_DATA);
107 inb(VGAREG_ACTL_RESET);
108 outb(0x20, VGAREG_ACTL_ADDRESS);
113 vgahw_set_all_palette_reg(u16 seg, u8 *data_far)
115 inb(VGAREG_ACTL_RESET);
117 for (i = 0; i < 0x10; i++) {
118 outb(i, VGAREG_ACTL_ADDRESS);
119 u8 val = GET_FARVAR(seg, *data_far);
120 outb(val, VGAREG_ACTL_WRITE_DATA);
123 outb(0x11, VGAREG_ACTL_ADDRESS);
124 outb(GET_FARVAR(seg, *data_far), VGAREG_ACTL_WRITE_DATA);
125 outb(0x20, VGAREG_ACTL_ADDRESS);
129 vgahw_get_all_palette_reg(u16 seg, u8 *data_far)
132 for (i = 0; i < 0x10; i++) {
133 inb(VGAREG_ACTL_RESET);
134 outb(i, VGAREG_ACTL_ADDRESS);
135 SET_FARVAR(seg, *data_far, inb(VGAREG_ACTL_READ_DATA));
138 inb(VGAREG_ACTL_RESET);
139 outb(0x11, VGAREG_ACTL_ADDRESS);
140 SET_FARVAR(seg, *data_far, inb(VGAREG_ACTL_READ_DATA));
141 inb(VGAREG_ACTL_RESET);
142 outb(0x20, VGAREG_ACTL_ADDRESS);
146 vgahw_toggle_intensity(u8 flag)
148 inb(VGAREG_ACTL_RESET);
149 outb(0x10, VGAREG_ACTL_ADDRESS);
150 u8 val = (inb(VGAREG_ACTL_READ_DATA) & 0xf7) | ((flag & 0x01) << 3);
151 outb(val, VGAREG_ACTL_WRITE_DATA);
152 outb(0x20, VGAREG_ACTL_ADDRESS);
156 vgahw_select_video_dac_color_page(u8 flag, u8 data)
158 inb(VGAREG_ACTL_RESET);
159 outb(0x10, VGAREG_ACTL_ADDRESS);
160 u8 val = inb(VGAREG_ACTL_READ_DATA);
161 if (!(flag & 0x01)) {
162 // select paging mode
163 val = (val & 0x7f) | (data << 7);
164 outb(val, VGAREG_ACTL_WRITE_DATA);
165 outb(0x20, VGAREG_ACTL_ADDRESS);
169 inb(VGAREG_ACTL_RESET);
170 outb(0x14, VGAREG_ACTL_ADDRESS);
174 outb(data, VGAREG_ACTL_WRITE_DATA);
175 outb(0x20, VGAREG_ACTL_ADDRESS);
179 vgahw_read_video_dac_state(u8 *pmode, u8 *curpage)
181 inb(VGAREG_ACTL_RESET);
182 outb(0x10, VGAREG_ACTL_ADDRESS);
183 u8 val1 = inb(VGAREG_ACTL_READ_DATA) >> 7;
185 inb(VGAREG_ACTL_RESET);
186 outb(0x14, VGAREG_ACTL_ADDRESS);
187 u8 val2 = inb(VGAREG_ACTL_READ_DATA) & 0x0f;
191 inb(VGAREG_ACTL_RESET);
192 outb(0x20, VGAREG_ACTL_ADDRESS);
199 /****************************************************************
201 ****************************************************************/
204 vgahw_set_dac_regs(u16 seg, u8 *data_far, u8 start, int count)
206 outb(start, VGAREG_DAC_WRITE_ADDRESS);
208 outb(GET_FARVAR(seg, *data_far), VGAREG_DAC_DATA);
210 outb(GET_FARVAR(seg, *data_far), VGAREG_DAC_DATA);
212 outb(GET_FARVAR(seg, *data_far), VGAREG_DAC_DATA);
219 vgahw_get_dac_regs(u16 seg, u8 *data_far, u8 start, int count)
221 outb(start, VGAREG_DAC_READ_ADDRESS);
223 SET_FARVAR(seg, *data_far, inb(VGAREG_DAC_DATA));
225 SET_FARVAR(seg, *data_far, inb(VGAREG_DAC_DATA));
227 SET_FARVAR(seg, *data_far, inb(VGAREG_DAC_DATA));
234 vgahw_set_pel_mask(u8 val)
236 outb(val, VGAREG_PEL_MASK);
242 return inb(VGAREG_PEL_MASK);
246 vgahw_save_dac_state(u16 seg, struct saveDACcolors *info)
248 /* XXX: check this */
249 SET_FARVAR(seg, info->rwmode, inb(VGAREG_DAC_STATE));
250 SET_FARVAR(seg, info->peladdr, inb(VGAREG_DAC_WRITE_ADDRESS));
251 SET_FARVAR(seg, info->pelmask, inb(VGAREG_PEL_MASK));
252 vgahw_get_dac_regs(seg, info->dac, 0, 256);
253 SET_FARVAR(seg, info->color_select, 0);
257 vgahw_restore_dac_state(u16 seg, struct saveDACcolors *info)
259 outb(GET_FARVAR(seg, info->pelmask), VGAREG_PEL_MASK);
260 vgahw_set_dac_regs(seg, info->dac, 0, 256);
261 outb(GET_FARVAR(seg, info->peladdr), VGAREG_DAC_WRITE_ADDRESS);
265 /****************************************************************
267 ****************************************************************/
270 vgahw_set_text_block_specifier(u8 spec)
272 outw((spec << 8) | 0x03, VGAREG_SEQU_ADDRESS);
278 outw(0x0100, VGAREG_SEQU_ADDRESS);
279 outw(0x0402, VGAREG_SEQU_ADDRESS);
280 outw(0x0704, VGAREG_SEQU_ADDRESS);
281 outw(0x0300, VGAREG_SEQU_ADDRESS);
282 outw(0x0204, VGAREG_GRDC_ADDRESS);
283 outw(0x0005, VGAREG_GRDC_ADDRESS);
284 outw(0x0406, VGAREG_GRDC_ADDRESS);
288 release_font_access()
290 outw(0x0100, VGAREG_SEQU_ADDRESS);
291 outw(0x0302, VGAREG_SEQU_ADDRESS);
292 outw(0x0304, VGAREG_SEQU_ADDRESS);
293 outw(0x0300, VGAREG_SEQU_ADDRESS);
294 u16 v = (inw(VGAREG_READ_MISC_OUTPUT) & 0x01) ? 0x0e : 0x0a;
295 outw((v << 8) | 0x06, VGAREG_GRDC_ADDRESS);
296 outw(0x0004, VGAREG_GRDC_ADDRESS);
297 outw(0x1005, VGAREG_GRDC_ADDRESS);
301 /****************************************************************
303 ****************************************************************/
308 return GET_BDA(crtc_address);
312 vgahw_set_cursor_shape(u8 start, u8 end)
314 u16 crtc_addr = get_crtc();
315 outb(0x0a, crtc_addr);
316 outb(start, crtc_addr + 1);
317 outb(0x0b, crtc_addr);
318 outb(end, crtc_addr + 1);
322 vgahw_set_active_page(u16 address)
324 u16 crtc_addr = get_crtc();
325 outb(0x0c, crtc_addr);
326 outb((address & 0xff00) >> 8, crtc_addr + 1);
327 outb(0x0d, crtc_addr);
328 outb(address & 0x00ff, crtc_addr + 1);
332 vgahw_set_cursor_pos(u16 address)
334 u16 crtc_addr = get_crtc();
335 outb(0x0e, crtc_addr);
336 outb((address & 0xff00) >> 8, crtc_addr + 1);
337 outb(0x0f, crtc_addr);
338 outb(address & 0x00ff, crtc_addr + 1);
342 vgahw_set_scan_lines(u8 lines)
344 u16 crtc_addr = get_crtc();
345 outb(0x09, crtc_addr);
346 u8 crtc_r9 = inb(crtc_addr + 1);
347 crtc_r9 = (crtc_r9 & 0xe0) | (lines - 1);
348 outb(crtc_r9, crtc_addr + 1);
351 // Get vertical display end
355 u16 crtc_addr = get_crtc();
356 outb(0x12, crtc_addr);
357 u16 vde = inb(crtc_addr + 1);
358 outb(0x07, crtc_addr);
359 u8 ovl = inb(crtc_addr + 1);
360 vde += (((ovl & 0x02) << 7) + ((ovl & 0x40) << 3) + 1);
365 /****************************************************************
366 * Save/Restore/Set state
367 ****************************************************************/
370 vgahw_save_state(u16 seg, struct saveVideoHardware *info)
372 u16 crtc_addr = get_crtc();
373 SET_FARVAR(seg, info->sequ_index, inb(VGAREG_SEQU_ADDRESS));
374 SET_FARVAR(seg, info->crtc_index, inb(crtc_addr));
375 SET_FARVAR(seg, info->grdc_index, inb(VGAREG_GRDC_ADDRESS));
376 inb(VGAREG_ACTL_RESET);
377 u16 ar_index = inb(VGAREG_ACTL_ADDRESS);
378 SET_FARVAR(seg, info->actl_index, ar_index);
379 SET_FARVAR(seg, info->feature, inb(VGAREG_READ_FEATURE_CTL));
382 for (i=0; i<4; i++) {
383 outb(i+1, VGAREG_SEQU_ADDRESS);
384 SET_FARVAR(seg, info->sequ_regs[i], inb(VGAREG_SEQU_DATA));
386 outb(0, VGAREG_SEQU_ADDRESS);
387 SET_FARVAR(seg, info->sequ0, inb(VGAREG_SEQU_DATA));
389 for (i=0; i<25; i++) {
391 SET_FARVAR(seg, info->crtc_regs[i], inb(crtc_addr + 1));
394 for (i=0; i<20; i++) {
395 inb(VGAREG_ACTL_RESET);
396 outb(i | (ar_index & 0x20), VGAREG_ACTL_ADDRESS);
397 SET_FARVAR(seg, info->actl_regs[i], inb(VGAREG_ACTL_READ_DATA));
399 inb(VGAREG_ACTL_RESET);
401 for (i=0; i<9; i++) {
402 outb(i, VGAREG_GRDC_ADDRESS);
403 SET_FARVAR(seg, info->grdc_regs[i], inb(VGAREG_GRDC_DATA));
406 SET_FARVAR(seg, info->crtc_addr, crtc_addr);
408 /* XXX: read plane latches */
410 SET_FARVAR(seg, info->plane_latch[i], 0);
414 vgahw_restore_state(u16 seg, struct saveVideoHardware *info)
416 // Reset Attribute Ctl flip-flop
417 inb(VGAREG_ACTL_RESET);
419 u16 crtc_addr = GET_FARVAR(seg, info->crtc_addr);
422 for (i=0; i<4; i++) {
423 outb(i+1, VGAREG_SEQU_ADDRESS);
424 outb(GET_FARVAR(seg, info->sequ_regs[i]), VGAREG_SEQU_DATA);
426 outb(0, VGAREG_SEQU_ADDRESS);
427 outb(GET_FARVAR(seg, info->sequ0), VGAREG_SEQU_DATA);
429 // Disable CRTC write protection
430 outw(0x0011, crtc_addr);
435 outb(GET_FARVAR(seg, info->crtc_regs[i]), crtc_addr + 1);
437 // select crtc base address
438 u16 v = inb(VGAREG_READ_MISC_OUTPUT) & ~0x01;
439 if (crtc_addr == VGAREG_VGA_CRTC_ADDRESS)
441 outb(v, VGAREG_WRITE_MISC_OUTPUT);
443 // enable write protection if needed
444 outb(0x11, crtc_addr);
445 outb(GET_FARVAR(seg, info->crtc_regs[0x11]), crtc_addr + 1);
448 u16 ar_index = GET_FARVAR(seg, info->actl_index);
449 inb(VGAREG_ACTL_RESET);
450 for (i=0; i<20; i++) {
451 outb(i | (ar_index & 0x20), VGAREG_ACTL_ADDRESS);
452 outb(GET_FARVAR(seg, info->actl_regs[i]), VGAREG_ACTL_WRITE_DATA);
454 outb(ar_index, VGAREG_ACTL_ADDRESS);
455 inb(VGAREG_ACTL_RESET);
457 for (i=0; i<9; i++) {
458 outb(i, VGAREG_GRDC_ADDRESS);
459 outb(GET_FARVAR(seg, info->grdc_regs[i]), VGAREG_GRDC_DATA);
462 outb(GET_FARVAR(seg, info->sequ_index), VGAREG_SEQU_ADDRESS);
463 outb(GET_FARVAR(seg, info->crtc_index), crtc_addr);
464 outb(GET_FARVAR(seg, info->grdc_index), VGAREG_GRDC_ADDRESS);
465 outb(GET_FARVAR(seg, info->feature), crtc_addr - 0x4 + 0xa);
469 vgahw_set_mode(struct VideoParam_s *vparam_g)
471 // Reset Attribute Ctl flip-flop
472 inb(VGAREG_ACTL_RESET);
476 for (i = 0; i <= 0x13; i++) {
477 outb(i, VGAREG_ACTL_ADDRESS);
478 outb(GET_GLOBAL(vparam_g->actl_regs[i]), VGAREG_ACTL_WRITE_DATA);
480 outb(0x14, VGAREG_ACTL_ADDRESS);
481 outb(0x00, VGAREG_ACTL_WRITE_DATA);
484 outb(0, VGAREG_SEQU_ADDRESS);
485 outb(0x03, VGAREG_SEQU_DATA);
486 for (i = 1; i <= 4; i++) {
487 outb(i, VGAREG_SEQU_ADDRESS);
488 outb(GET_GLOBAL(vparam_g->sequ_regs[i - 1]), VGAREG_SEQU_DATA);
492 for (i = 0; i <= 8; i++) {
493 outb(i, VGAREG_GRDC_ADDRESS);
494 outb(GET_GLOBAL(vparam_g->grdc_regs[i]), VGAREG_GRDC_DATA);
497 // Set CRTC address VGA or MDA
498 u8 miscreg = GET_GLOBAL(vparam_g->miscreg);
499 u16 crtc_addr = VGAREG_VGA_CRTC_ADDRESS;
501 crtc_addr = VGAREG_MDA_CRTC_ADDRESS;
503 // Disable CRTC write protection
504 outw(0x0011, crtc_addr);
506 for (i = 0; i <= 0x18; i++) {
508 outb(GET_GLOBAL(vparam_g->crtc_regs[i]), crtc_addr + 1);
511 // Set the misc register
512 outb(miscreg, VGAREG_WRITE_MISC_OUTPUT);
515 outb(0x20, VGAREG_ACTL_ADDRESS);
516 inb(VGAREG_ACTL_RESET);
520 /****************************************************************
522 ****************************************************************/
525 vgahw_enable_video_addressing(u8 disable)
527 u8 v = (disable & 1) ? 0x00 : 0x02;
528 u8 v2 = inb(VGAREG_READ_MISC_OUTPUT) & ~0x02;
529 outb(v | v2, VGAREG_WRITE_MISC_OUTPUT);
535 // switch to color mode and enable CPU access 480 lines
536 outb(0xc3, VGAREG_WRITE_MISC_OUTPUT);
537 // more than 64k 3C4/04
538 outb(0x04, VGAREG_SEQU_ADDRESS);
539 outb(0x02, VGAREG_SEQU_DATA);