1 // VGA bios implementation
3 // Copyright (C) 2009 Kevin O'Connor <kevin@koconnor.net>
4 // Copyright (C) 2001-2008 the LGPL VGABios developers Team
6 // This file may be distributed under the terms of the GNU LGPLv3 license.
10 // * introduce "struct vregs", or add ebp to struct bregs.
11 // * Integrate vga_modes/pallete?/line_to_vpti/dac_regs/video_param_table
12 // * define structs for save/restore state
13 // * review correctness of converted asm by comparing with RBIL
14 // * eliminate unimplemented() calls
15 // * eliminate DEBUG defs
16 // * more syntax cleanups
17 // * refactor redundant code into sub-functions
18 // * See if there is a method to the in/out stuff that can be encapsulated.
19 // * remove "biosfn" prefixes
20 // * don't hardcode 0xc000
21 // * add defs for 0xa000/0xb800
22 // * verify all funcs static
24 // * separate code into separate files
25 // * extract hw code from bios interfaces
27 // * convert vbe/clext code
29 #include "bregs.h" // struct bregs
30 #include "biosvar.h" // GET_BDA
31 #include "util.h" // memset
32 #include "vgatables.h" // vga_modes
36 #define CONFIG_CIRRUS 0
39 #define DEBUG_VGA_POST 1
40 #define DEBUG_VGA_10 3
42 #define SET_VGA(var, val) SET_FARVAR(0xc000, (var), (val))
45 // ===================================================================
49 // ===================================================================
51 // -------------------------------------------------------------------
53 find_vga_entry(u8 mode)
56 for (i = 0; i <= MODE_MAX; i++)
57 if (GET_GLOBAL(vga_modes[i].svgamode) == mode)
63 call16_vgaint(u32 eax, u32 ebx)
76 memcpy16_far(u16 d_seg, void *d_far, u16 s_seg, const void *s_far, size_t len)
78 memcpy_far(d_seg, d_far, s_seg, s_far, len);
82 // ===================================================================
86 // ===================================================================
88 // -------------------------------------------------------------------
90 biosfn_perform_gray_scale_summing(u16 start, u16 count)
96 inb(VGAREG_ACTL_RESET);
97 outb(0x00, VGAREG_ACTL_ADDRESS);
99 for (index = 0; index < count; index++) {
100 // set read address and switch to read mode
101 outb(start, VGAREG_DAC_READ_ADDRESS);
102 // get 6-bit wide RGB data values
103 r = inb(VGAREG_DAC_DATA);
104 g = inb(VGAREG_DAC_DATA);
105 b = inb(VGAREG_DAC_DATA);
107 // intensity = ( 0.3 * Red ) + ( 0.59 * Green ) + ( 0.11 * Blue )
108 i = ((77 * r + 151 * g + 28 * b) + 0x80) >> 8;
113 // set write address and switch to write mode
114 outb(start, VGAREG_DAC_WRITE_ADDRESS);
115 // write new intensity value
116 outb(i & 0xff, VGAREG_DAC_DATA);
117 outb(i & 0xff, VGAREG_DAC_DATA);
118 outb(i & 0xff, VGAREG_DAC_DATA);
121 inb(VGAREG_ACTL_RESET);
122 outb(0x20, VGAREG_ACTL_ADDRESS);
125 // -------------------------------------------------------------------
127 biosfn_set_cursor_shape(u8 CH, u8 CL)
129 u16 cheight, curs, crtc_addr;
135 curs = (CH << 8) + CL;
136 SET_BDA(cursor_type, curs);
138 modeset_ctl = GET_BDA(modeset_ctl);
139 cheight = GET_BDA(char_height);
140 if ((modeset_ctl & 0x01) && (cheight > 8) && (CL < 8) && (CH < 0x20)) {
141 if (CL != (CH + 1)) {
142 CH = ((CH + 1) * cheight / 8) - 1;
144 CH = ((CL + 1) * cheight / 8) - 2;
146 CL = ((CL + 1) * cheight / 8) - 1;
148 // CTRC regs 0x0a and 0x0b
149 crtc_addr = GET_BDA(crtc_address);
150 outb(0x0a, crtc_addr);
151 outb(CH, crtc_addr + 1);
152 outb(0x0b, crtc_addr);
153 outb(CL, crtc_addr + 1);
156 // -------------------------------------------------------------------
158 biosfn_set_cursor_pos(u8 page, u16 cursor)
160 u8 xcurs, ycurs, current;
161 u16 nbcols, nbrows, address, crtc_addr;
163 // Should not happen...
168 SET_BDA(cursor_pos[page], cursor);
170 // Set the hardware cursor
171 current = GET_BDA(video_page);
172 if (page == current) {
173 // Get the dimensions
174 nbcols = GET_BDA(video_cols);
175 nbrows = GET_BDA(video_rows) + 1;
177 xcurs = cursor & 0x00ff;
178 ycurs = (cursor & 0xff00) >> 8;
180 // Calculate the address knowing nbcols nbrows and page num
182 SCREEN_IO_START(nbcols, nbrows, page) + xcurs + ycurs * nbcols;
184 // CRTC regs 0x0e and 0x0f
185 crtc_addr = GET_BDA(crtc_address);
186 outb(0x0e, crtc_addr);
187 outb((address & 0xff00) >> 8, crtc_addr + 1);
188 outb(0x0f, crtc_addr);
189 outb(address & 0x00ff, crtc_addr + 1);
193 // -------------------------------------------------------------------
195 biosfn_get_cursor_pos(u8 page, u16 *shape, u16 *pos)
203 // FIXME should handle VGA 14/16 lines
204 *shape = GET_BDA(cursor_type);
205 *pos = GET_BDA(cursor_pos[page]);
208 // -------------------------------------------------------------------
210 biosfn_set_active_page(u8 page)
212 u16 cursor, dummy, crtc_addr;
213 u16 nbcols, nbrows, address;
220 mode = GET_BDA(video_mode);
221 line = find_vga_entry(mode);
225 // Get pos curs pos for the right page
226 biosfn_get_cursor_pos(page, &dummy, &cursor);
228 if (GET_GLOBAL(vga_modes[line].class) == TEXT) {
229 // Get the dimensions
230 nbcols = GET_BDA(video_cols);
231 nbrows = GET_BDA(video_rows) + 1;
233 // Calculate the address knowing nbcols nbrows and page num
234 address = SCREEN_MEM_START(nbcols, nbrows, page);
235 SET_BDA(video_pagestart, address);
238 address = SCREEN_IO_START(nbcols, nbrows, page);
240 address = page * GET_GLOBAL(video_param_table[GET_GLOBAL(line_to_vpti[line])].slength);
243 // CRTC regs 0x0c and 0x0d
244 crtc_addr = GET_BDA(crtc_address);
245 outb(0x0c, crtc_addr);
246 outb((address & 0xff00) >> 8, crtc_addr + 1);
247 outb(0x0d, crtc_addr);
248 outb(address & 0x00ff, crtc_addr + 1);
250 // And change the BIOS page
251 SET_BDA(video_page, page);
254 printf("Set active page %02x address %04x\n", page, address);
257 // Display the cursor, now the page is active
258 biosfn_set_cursor_pos(page, cursor);
262 biosfn_set_video_mode(u8 mode)
263 { // mode: Bit 7 is 1 if no clear screen
264 // Should we clear the screen ?
265 u8 noclearmem = mode & 0x80;
266 u8 line, mmask, *palette, vpti;
267 u16 i, twidth, theightm1, cheight;
268 u8 modeset_ctl, video_ctl, vga_switches;
271 cirrus_set_video_mode(mode);
274 if (vbe_has_vbe_display())
275 dispi_set_enable(VBE_DISPI_DISABLED);
281 // find the entry in the video modes
282 line = find_vga_entry(mode);
285 printf("mode search %02x found line %02x\n", mode, line);
291 vpti = GET_GLOBAL(line_to_vpti[line]);
292 twidth = GET_GLOBAL(video_param_table[vpti].twidth);
293 theightm1 = GET_GLOBAL(video_param_table[vpti].theightm1);
294 cheight = GET_GLOBAL(video_param_table[vpti].cheight);
296 // Read the bios vga control
297 video_ctl = GET_BDA(video_ctl);
299 // Read the bios vga switches
300 vga_switches = GET_BDA(video_switches);
302 // Read the bios mode set control
303 modeset_ctl = GET_BDA(modeset_ctl);
305 // Then we know the number of lines
308 // if palette loading (bit 3 of modeset ctl = 0)
309 if ((modeset_ctl & 0x08) == 0) { // Set the PEL mask
310 outb(GET_GLOBAL(vga_modes[line].pelmask), VGAREG_PEL_MASK);
312 // Set the whole dac always, from 0
313 outb(0x00, VGAREG_DAC_WRITE_ADDRESS);
315 // From which palette
316 switch (GET_GLOBAL(vga_modes[line].dacmodel)) {
331 // Always 256*3 values
332 for (i = 0; i < 0x0100; i++) {
333 if (i <= GET_GLOBAL(dac_regs[GET_GLOBAL(vga_modes[line].dacmodel)])) {
334 outb(GET_GLOBAL(palette[(i * 3) + 0]), VGAREG_DAC_DATA);
335 outb(GET_GLOBAL(palette[(i * 3) + 1]), VGAREG_DAC_DATA);
336 outb(GET_GLOBAL(palette[(i * 3) + 2]), VGAREG_DAC_DATA);
338 outb(0, VGAREG_DAC_DATA);
339 outb(0, VGAREG_DAC_DATA);
340 outb(0, VGAREG_DAC_DATA);
343 if ((modeset_ctl & 0x02) == 0x02)
344 biosfn_perform_gray_scale_summing(0x00, 0x100);
346 // Reset Attribute Ctl flip-flop
347 inb(VGAREG_ACTL_RESET);
350 for (i = 0; i <= 0x13; i++) {
351 outb(i, VGAREG_ACTL_ADDRESS);
352 outb(GET_GLOBAL(video_param_table[vpti].actl_regs[i])
353 , VGAREG_ACTL_WRITE_DATA);
355 outb(0x14, VGAREG_ACTL_ADDRESS);
356 outb(0x00, VGAREG_ACTL_WRITE_DATA);
359 outb(0, VGAREG_SEQU_ADDRESS);
360 outb(0x03, VGAREG_SEQU_DATA);
361 for (i = 1; i <= 4; i++) {
362 outb(i, VGAREG_SEQU_ADDRESS);
363 outb(GET_GLOBAL(video_param_table[vpti].sequ_regs[i - 1])
368 for (i = 0; i <= 8; i++) {
369 outb(i, VGAREG_GRDC_ADDRESS);
370 outb(GET_GLOBAL(video_param_table[vpti].grdc_regs[i])
374 // Set CRTC address VGA or MDA
375 u16 crtc_addr = VGAREG_VGA_CRTC_ADDRESS;
376 if (GET_GLOBAL(vga_modes[line].memmodel) == MTEXT)
377 crtc_addr = VGAREG_MDA_CRTC_ADDRESS;
379 // Disable CRTC write protection
380 outw(0x0011, crtc_addr);
382 for (i = 0; i <= 0x18; i++) {
384 outb(GET_GLOBAL(video_param_table[vpti].crtc_regs[i]), crtc_addr + 1);
387 // Set the misc register
388 outb(GET_GLOBAL(video_param_table[vpti].miscreg), VGAREG_WRITE_MISC_OUTPUT);
391 outb(0x20, VGAREG_ACTL_ADDRESS);
392 inb(VGAREG_ACTL_RESET);
394 if (noclearmem == 0x00) {
395 if (GET_GLOBAL(vga_modes[line].class) == TEXT) {
396 memset16_far(GET_GLOBAL(vga_modes[line].sstart)
397 , 0, 0x0720, 0x4000); // 32k
400 memset16_far(GET_GLOBAL(vga_modes[line].sstart)
401 , 0, 0x0000, 0x4000); // 32k
403 outb(0x02, VGAREG_SEQU_ADDRESS);
404 mmask = inb(VGAREG_SEQU_DATA);
405 outb(0x0f, VGAREG_SEQU_DATA); // all planes
406 memset16_far(GET_GLOBAL(vga_modes[line].sstart)
407 , 0, 0x0000, 0x8000); // 64k
408 outb(mmask, VGAREG_SEQU_DATA);
413 SET_BDA(video_mode, mode);
414 SET_BDA(video_cols, twidth);
415 SET_BDA(video_pagesize, GET_GLOBAL(video_param_table[vpti].slength));
416 SET_BDA(crtc_address, crtc_addr);
417 SET_BDA(video_rows, theightm1);
418 SET_BDA(char_height, cheight);
419 SET_BDA(video_ctl, (0x60 | noclearmem));
420 SET_BDA(video_switches, 0xF9);
421 SET_BDA(modeset_ctl, GET_BDA(modeset_ctl) & 0x7f);
423 // FIXME We nearly have the good tables. to be reworked
424 SET_BDA(dcc_index, 0x08); // 8 is VGA should be ok for now
425 SET_BDA(video_savetable_ptr, (u32)video_save_pointer_table);
426 SET_BDA(video_savetable_seg, 0xc000);
429 SET_BDA(video_msr, 0x00); // Unavailable on vanilla vga, but...
430 SET_BDA(video_pal, 0x00); // Unavailable on vanilla vga, but...
433 if (GET_GLOBAL(vga_modes[line].class) == TEXT)
434 biosfn_set_cursor_shape(0x06, 0x07);
435 // Set cursor pos for page 0..7
436 for (i = 0; i < 8; i++)
437 biosfn_set_cursor_pos(i, 0x0000);
440 biosfn_set_active_page(0x00);
442 // Write the fonts in memory
443 if (GET_GLOBAL(vga_modes[line].class) == TEXT) {
444 call16_vgaint(0x1104, 0);
445 call16_vgaint(0x1103, 0);
447 // Set the ints 0x1F and 0x43
448 SET_IVT(0x1f, 0xC000, (u32)&vgafont8[128 * 8]);
452 SET_IVT(0x43, 0xC000, (u32)vgafont8);
455 SET_IVT(0x43, 0xC000, (u32)vgafont14);
458 SET_IVT(0x43, 0xC000, (u32)vgafont16);
463 // -------------------------------------------------------------------
465 vgamem_copy_pl4(u8 xstart, u8 ysrc, u8 ydest, u8 cols, u8 nbcols,
468 u16 src = ysrc * cheight * nbcols + xstart;
469 u16 dest = ydest * cheight * nbcols + xstart;
470 outw(0x0105, VGAREG_GRDC_ADDRESS);
472 for (i = 0; i < cheight; i++)
473 memcpy_far(0xa000, (void*)(dest + i * nbcols)
474 , 0xa000, (void*)(src + i * nbcols), cols);
475 outw(0x0005, VGAREG_GRDC_ADDRESS);
478 // -------------------------------------------------------------------
480 vgamem_fill_pl4(u8 xstart, u8 ystart, u8 cols, u8 nbcols, u8 cheight,
483 u16 dest = ystart * cheight * nbcols + xstart;
484 outw(0x0205, VGAREG_GRDC_ADDRESS);
486 for (i = 0; i < cheight; i++)
487 memset_far(0xa000, (void*)(dest + i * nbcols), attr, cols);
488 outw(0x0005, VGAREG_GRDC_ADDRESS);
491 // -------------------------------------------------------------------
493 vgamem_copy_cga(u8 xstart, u8 ysrc, u8 ydest, u8 cols, u8 nbcols,
496 u16 src = ((ysrc * cheight * nbcols) >> 1) + xstart;
497 u16 dest = ((ydest * cheight * nbcols) >> 1) + xstart;
499 for (i = 0; i < cheight; i++)
501 memcpy_far(0xb800, (void*)(0x2000 + dest + (i >> 1) * nbcols)
502 , 0xb800, (void*)(0x2000 + src + (i >> 1) * nbcols)
505 memcpy_far(0xb800, (void*)(dest + (i >> 1) * nbcols)
506 , 0xb800, (void*)(src + (i >> 1) * nbcols), cols);
509 // -------------------------------------------------------------------
511 vgamem_fill_cga(u8 xstart, u8 ystart, u8 cols, u8 nbcols, u8 cheight,
514 u16 dest = ((ystart * cheight * nbcols) >> 1) + xstart;
516 for (i = 0; i < cheight; i++)
518 memset_far(0xb800, (void*)(0x2000 + dest + (i >> 1) * nbcols)
521 memset_far(0xb800, (void*)(dest + (i >> 1) * nbcols), attr, cols);
524 // -------------------------------------------------------------------
526 biosfn_scroll(u8 nblines, u8 attr, u8 rul, u8 cul, u8 rlr, u8 clr, u8 page,
529 // page == 0xFF if current
531 u8 mode, line, cheight, bpp, cols;
532 u16 nbcols, nbrows, i;
540 mode = GET_BDA(video_mode);
541 line = find_vga_entry(mode);
545 // Get the dimensions
546 nbrows = GET_BDA(video_rows) + 1;
547 nbcols = GET_BDA(video_cols);
549 // Get the current page
551 page = GET_BDA(video_page);
557 if (nblines > nbrows)
559 cols = clr - cul + 1;
561 if (GET_GLOBAL(vga_modes[line].class) == TEXT) {
562 // Compute the address
563 void *address = (void*)(SCREEN_MEM_START(nbcols, nbrows, page));
565 printf("Scroll, address %04x (%04x %04x %02x)\n", address, nbrows,
569 if (nblines == 0 && rul == 0 && cul == 0 && rlr == nbrows - 1
570 && clr == nbcols - 1) {
571 memset16_far(GET_GLOBAL(vga_modes[line].sstart), address
572 , (u16)attr * 0x100 + ' ', nbrows * nbcols);
573 } else { // if Scroll up
574 if (dir == SCROLL_UP) {
575 for (i = rul; i <= rlr; i++) {
576 if ((i + nblines > rlr) || (nblines == 0))
577 memset16_far(GET_GLOBAL(vga_modes[line].sstart)
578 , address + (i * nbcols + cul) * 2
579 , (u16)attr * 0x100 + ' ', cols);
581 memcpy16_far(GET_GLOBAL(vga_modes[line].sstart)
582 , address + (i * nbcols + cul) * 2
583 , GET_GLOBAL(vga_modes[line].sstart)
584 , (void*)(((i + nblines) * nbcols + cul) * 2)
588 for (i = rlr; i >= rul; i--) {
589 if ((i < rul + nblines) || (nblines == 0))
590 memset16_far(GET_GLOBAL(vga_modes[line].sstart)
591 , address + (i * nbcols + cul) * 2
592 , (u16)attr * 0x100 + ' ', cols);
594 memcpy16_far(GET_GLOBAL(vga_modes[line].sstart)
595 , address + (i * nbcols + cul) * 2
596 , GET_GLOBAL(vga_modes[line].sstart)
597 , (void*)(((i - nblines) * nbcols + cul) * 2)
605 // FIXME gfx mode not complete
606 cheight = GET_GLOBAL(video_param_table[GET_GLOBAL(line_to_vpti[line])].cheight);
607 switch (GET_GLOBAL(vga_modes[line].memmodel)) {
610 if (nblines == 0 && rul == 0 && cul == 0 && rlr == nbrows - 1
611 && clr == nbcols - 1) {
612 outw(0x0205, VGAREG_GRDC_ADDRESS);
613 memset_far(GET_GLOBAL(vga_modes[line].sstart), 0, attr,
614 nbrows * nbcols * cheight);
615 outw(0x0005, VGAREG_GRDC_ADDRESS);
616 } else { // if Scroll up
617 if (dir == SCROLL_UP) {
618 for (i = rul; i <= rlr; i++) {
619 if ((i + nblines > rlr) || (nblines == 0))
620 vgamem_fill_pl4(cul, i, cols, nbcols, cheight,
623 vgamem_copy_pl4(cul, i + nblines, i, cols,
627 for (i = rlr; i >= rul; i--) {
628 if ((i < rul + nblines) || (nblines == 0))
629 vgamem_fill_pl4(cul, i, cols, nbcols, cheight,
632 vgamem_copy_pl4(cul, i, i - nblines, cols,
641 bpp = GET_GLOBAL(vga_modes[line].pixbits);
642 if (nblines == 0 && rul == 0 && cul == 0 && rlr == nbrows - 1
643 && clr == nbcols - 1) {
644 memset_far(GET_GLOBAL(vga_modes[line].sstart), 0, attr,
645 nbrows * nbcols * cheight * bpp);
653 if (dir == SCROLL_UP) {
654 for (i = rul; i <= rlr; i++) {
655 if ((i + nblines > rlr) || (nblines == 0))
656 vgamem_fill_cga(cul, i, cols, nbcols, cheight,
659 vgamem_copy_cga(cul, i + nblines, i, cols,
663 for (i = rlr; i >= rul; i--) {
664 if ((i < rul + nblines) || (nblines == 0))
665 vgamem_fill_cga(cul, i, cols, nbcols, cheight,
668 vgamem_copy_cga(cul, i, i - nblines, cols,
678 printf("Scroll in graphics mode ");
685 // -------------------------------------------------------------------
687 biosfn_read_char_attr(u8 page, u16 *car)
689 u8 xcurs, ycurs, mode, line;
694 mode = GET_BDA(video_mode);
695 line = find_vga_entry(mode);
699 // Get the cursor pos for the page
700 biosfn_get_cursor_pos(page, &dummy, &cursor);
701 xcurs = cursor & 0x00ff;
702 ycurs = (cursor & 0xff00) >> 8;
704 // Get the dimensions
705 nbrows = GET_BDA(video_rows) + 1;
706 nbcols = GET_BDA(video_cols);
708 if (GET_GLOBAL(vga_modes[line].class) == TEXT) {
709 // Compute the address
710 u16 *address = (void*)(SCREEN_MEM_START(nbcols, nbrows, page)
711 + (xcurs + ycurs * nbcols) * 2);
713 *car = GET_FARVAR(GET_GLOBAL(vga_modes[line].sstart), *address);
722 // -------------------------------------------------------------------
724 write_gfx_char_pl4(u8 car, u8 attr, u8 xcurs, u8 ycurs, u8 nbcols,
741 addr = xcurs + ycurs * cheight * nbcols;
743 outw(0x0f02, VGAREG_SEQU_ADDRESS);
744 outw(0x0205, VGAREG_GRDC_ADDRESS);
746 outw(0x1803, VGAREG_GRDC_ADDRESS);
748 outw(0x0003, VGAREG_GRDC_ADDRESS);
749 for (i = 0; i < cheight; i++) {
750 u8 *dest = (void*)(addr + i * nbcols);
751 for (j = 0; j < 8; j++) {
753 outw((mask << 8) | 0x08, VGAREG_GRDC_ADDRESS);
754 GET_FARVAR(0xa000, *dest);
755 if (GET_GLOBAL(fdata[src + i]) & mask)
756 SET_FARVAR(0xa000, *dest, attr & 0x0f);
758 SET_FARVAR(0xa000, *dest, 0x00);
761 outw(0xff08, VGAREG_GRDC_ADDRESS);
762 outw(0x0005, VGAREG_GRDC_ADDRESS);
763 outw(0x0003, VGAREG_GRDC_ADDRESS);
766 // -------------------------------------------------------------------
768 write_gfx_char_cga(u8 car, u8 attr, u8 xcurs, u8 ycurs, u8 nbcols, u8 bpp)
770 u8 *fdata = vgafont8;
771 u16 addr = (xcurs * bpp) + ycurs * 320;
774 for (i = 0; i < 8; i++) {
775 u8 *dest = (void*)(addr + (i >> 1) * 80);
782 data = GET_FARVAR(0xb800, *dest);
784 for (j = 0; j < 8; j++) {
785 if (GET_GLOBAL(fdata[src + i]) & mask) {
787 data ^= (attr & 0x01) << (7 - j);
789 data |= (attr & 0x01) << (7 - j);
793 SET_FARVAR(0xb800, *dest, data);
798 data = GET_FARVAR(0xb800, *dest);
800 for (j = 0; j < 4; j++) {
801 if (GET_GLOBAL(fdata[src + i]) & mask) {
803 data ^= (attr & 0x03) << ((3 - j) * 2);
805 data |= (attr & 0x03) << ((3 - j) * 2);
809 SET_FARVAR(0xb800, *dest, data);
816 // -------------------------------------------------------------------
818 write_gfx_char_lin(u8 car, u8 attr, u8 xcurs, u8 ycurs, u8 nbcols)
820 u8 *fdata = vgafont8;
821 u16 addr = xcurs * 8 + ycurs * nbcols * 64;
824 for (i = 0; i < 8; i++) {
825 u8 *dest = (void*)(addr + i * nbcols * 8);
828 for (j = 0; j < 8; j++) {
830 if (GET_GLOBAL(fdata[src + i]) & mask)
832 SET_FARVAR(0xa000, dest[j], data);
838 // -------------------------------------------------------------------
840 biosfn_write_char_attr(u8 car, u8 page, u8 attr, u16 count)
842 u8 cheight, xcurs, ycurs, mode, line, bpp;
847 mode = GET_BDA(video_mode);
848 line = find_vga_entry(mode);
852 // Get the cursor pos for the page
853 biosfn_get_cursor_pos(page, &dummy, &cursor);
854 xcurs = cursor & 0x00ff;
855 ycurs = (cursor & 0xff00) >> 8;
857 // Get the dimensions
858 nbrows = GET_BDA(video_rows) + 1;
859 nbcols = GET_BDA(video_cols);
861 if (GET_GLOBAL(vga_modes[line].class) == TEXT) {
862 // Compute the address
863 void *address = (void*)(SCREEN_MEM_START(nbcols, nbrows, page)
864 + (xcurs + ycurs * nbcols) * 2);
866 dummy = ((u16)attr << 8) + car;
867 memset16_far(GET_GLOBAL(vga_modes[line].sstart), address, dummy, count);
869 // FIXME gfx mode not complete
870 cheight = GET_GLOBAL(video_param_table[GET_GLOBAL(line_to_vpti[line])].cheight);
871 bpp = GET_GLOBAL(vga_modes[line].pixbits);
872 while ((count-- > 0) && (xcurs < nbcols)) {
873 switch (GET_GLOBAL(vga_modes[line].memmodel)) {
876 write_gfx_char_pl4(car, attr, xcurs, ycurs, nbcols,
880 write_gfx_char_cga(car, attr, xcurs, ycurs, nbcols, bpp);
883 write_gfx_char_lin(car, attr, xcurs, ycurs, nbcols);
895 // -------------------------------------------------------------------
897 biosfn_write_char_only(u8 car, u8 page, u8 attr, u16 count)
899 u8 cheight, xcurs, ycurs, mode, line, bpp;
904 mode = GET_BDA(video_mode);
905 line = find_vga_entry(mode);
909 // Get the cursor pos for the page
910 biosfn_get_cursor_pos(page, &dummy, &cursor);
911 xcurs = cursor & 0x00ff;
912 ycurs = (cursor & 0xff00) >> 8;
914 // Get the dimensions
915 nbrows = GET_BDA(video_rows) + 1;
916 nbcols = GET_BDA(video_cols);
918 if (GET_GLOBAL(vga_modes[line].class) == TEXT) {
919 // Compute the address
920 u8 *address = (void*)(SCREEN_MEM_START(nbcols, nbrows, page)
921 + (xcurs + ycurs * nbcols) * 2);
922 while (count-- > 0) {
923 SET_FARVAR(GET_GLOBAL(vga_modes[line].sstart), *address, car);
927 // FIXME gfx mode not complete
928 cheight = GET_GLOBAL(video_param_table[GET_GLOBAL(line_to_vpti[line])].cheight);
929 bpp = GET_GLOBAL(vga_modes[line].pixbits);
930 while ((count-- > 0) && (xcurs < nbcols)) {
931 switch (GET_GLOBAL(vga_modes[line].memmodel)) {
934 write_gfx_char_pl4(car, attr, xcurs, ycurs, nbcols,
938 write_gfx_char_cga(car, attr, xcurs, ycurs, nbcols, bpp);
941 write_gfx_char_lin(car, attr, xcurs, ycurs, nbcols);
955 // -------------------------------------------------------------------
957 biosfn_set_border_color(struct bregs *regs)
959 inb(VGAREG_ACTL_RESET);
960 outb(0x00, VGAREG_ACTL_ADDRESS);
961 u8 al = regs->bl & 0x0f;
964 outb(al, VGAREG_ACTL_WRITE_DATA);
965 u8 bl = regs->bl & 0x10;
968 for (i = 1; i < 4; i++) {
969 outb(i, VGAREG_ACTL_ADDRESS);
971 al = inb(VGAREG_ACTL_READ_DATA);
974 outb(al, VGAREG_ACTL_WRITE_DATA);
976 outb(0x20, VGAREG_ACTL_ADDRESS);
980 biosfn_set_palette(struct bregs *regs)
982 inb(VGAREG_ACTL_RESET);
983 u8 bl = regs->bl & 0x01;
985 for (i = 1; i < 4; i++) {
986 outb(i, VGAREG_ACTL_ADDRESS);
988 u8 al = inb(VGAREG_ACTL_READ_DATA);
991 outb(al, VGAREG_ACTL_WRITE_DATA);
993 outb(0x20, VGAREG_ACTL_ADDRESS);
996 // -------------------------------------------------------------------
998 biosfn_write_pixel(u8 BH, u8 AL, u16 CX, u16 DX)
1000 u8 mask, attr, data;
1003 u8 mode = GET_BDA(video_mode);
1004 u8 line = find_vga_entry(mode);
1007 if (GET_GLOBAL(vga_modes[line].class) == TEXT)
1011 switch (GET_GLOBAL(vga_modes[line].memmodel)) {
1014 addr = (void*)(CX / 8 + DX * GET_BDA(video_cols));
1015 mask = 0x80 >> (CX & 0x07);
1016 outw((mask << 8) | 0x08, VGAREG_GRDC_ADDRESS);
1017 outw(0x0205, VGAREG_GRDC_ADDRESS);
1018 data = GET_FARVAR(0xa000, *addr);
1020 outw(0x1803, VGAREG_GRDC_ADDRESS);
1021 SET_FARVAR(0xa000, *addr, AL);
1022 outw(0xff08, VGAREG_GRDC_ADDRESS);
1023 outw(0x0005, VGAREG_GRDC_ADDRESS);
1024 outw(0x0003, VGAREG_GRDC_ADDRESS);
1027 if (GET_GLOBAL(vga_modes[line].pixbits) == 2)
1028 addr = (void*)((CX >> 2) + (DX >> 1) * 80);
1030 addr = (void*)((CX >> 3) + (DX >> 1) * 80);
1033 data = GET_FARVAR(0xb800, *addr);
1034 if (GET_GLOBAL(vga_modes[line].pixbits) == 2) {
1035 attr = (AL & 0x03) << ((3 - (CX & 0x03)) * 2);
1036 mask = 0x03 << ((3 - (CX & 0x03)) * 2);
1038 attr = (AL & 0x01) << (7 - (CX & 0x07));
1039 mask = 0x01 << (7 - (CX & 0x07));
1047 SET_FARVAR(0xb800, *addr, data);
1050 addr = (void*)(CX + DX * (GET_BDA(video_cols) * 8));
1051 SET_FARVAR(0xa000, *addr, AL);
1060 // -------------------------------------------------------------------
1062 biosfn_read_pixel(u8 BH, u16 CX, u16 DX, u16 *AX)
1064 u8 mode, line, mask, attr, data, i;
1067 mode = GET_BDA(video_mode);
1068 line = find_vga_entry(mode);
1071 if (GET_GLOBAL(vga_modes[line].class) == TEXT)
1075 switch (GET_GLOBAL(vga_modes[line].memmodel)) {
1078 addr = (void*)(CX / 8 + DX * GET_BDA(video_cols));
1079 mask = 0x80 >> (CX & 0x07);
1081 for (i = 0; i < 4; i++) {
1082 outw((i << 8) | 0x04, VGAREG_GRDC_ADDRESS);
1083 data = GET_FARVAR(0xa000, *addr) & mask;
1085 attr |= (0x01 << i);
1089 addr = (void*)((CX >> 2) + (DX >> 1) * 80);
1092 data = GET_FARVAR(0xb800, *addr);
1093 if (GET_GLOBAL(vga_modes[line].pixbits) == 2)
1094 attr = (data >> ((3 - (CX & 0x03)) * 2)) & 0x03;
1096 attr = (data >> (7 - (CX & 0x07))) & 0x01;
1099 addr = (void*)(CX + DX * (GET_BDA(video_cols) * 8));
1100 attr = GET_FARVAR(0xa000, *addr);
1108 *AX = (*AX & 0xff00) | attr;
1111 // -------------------------------------------------------------------
1113 biosfn_write_teletype(u8 car, u8 page, u8 attr, u8 flag)
1114 { // flag = WITH_ATTR / NO_ATTR
1115 u8 cheight, xcurs, ycurs, mode, line, bpp;
1119 // special case if page is 0xff, use current page
1121 page = GET_BDA(video_page);
1124 mode = GET_BDA(video_mode);
1125 line = find_vga_entry(mode);
1129 // Get the cursor pos for the page
1130 biosfn_get_cursor_pos(page, &dummy, &cursor);
1131 xcurs = cursor & 0x00ff;
1132 ycurs = (cursor & 0xff00) >> 8;
1134 // Get the dimensions
1135 nbrows = GET_BDA(video_rows) + 1;
1136 nbcols = GET_BDA(video_cols);
1158 biosfn_write_teletype(' ', page, attr, flag);
1159 biosfn_get_cursor_pos(page, &dummy, &cursor);
1160 xcurs = cursor & 0x00ff;
1161 ycurs = (cursor & 0xff00) >> 8;
1162 } while (xcurs % 8 == 0);
1167 if (GET_GLOBAL(vga_modes[line].class) == TEXT) {
1168 // Compute the address
1169 u8 *address = (void*)(SCREEN_MEM_START(nbcols, nbrows, page)
1170 + (xcurs + ycurs * nbcols) * 2);
1172 SET_FARVAR(GET_GLOBAL(vga_modes[line].sstart), address[0], car);
1173 if (flag == WITH_ATTR)
1174 SET_FARVAR(GET_GLOBAL(vga_modes[line].sstart), address[1], attr);
1176 // FIXME gfx mode not complete
1177 cheight = GET_GLOBAL(video_param_table[GET_GLOBAL(line_to_vpti[line])].cheight);
1178 bpp = GET_GLOBAL(vga_modes[line].pixbits);
1179 switch (GET_GLOBAL(vga_modes[line].memmodel)) {
1182 write_gfx_char_pl4(car, attr, xcurs, ycurs, nbcols,
1186 write_gfx_char_cga(car, attr, xcurs, ycurs, nbcols, bpp);
1189 write_gfx_char_lin(car, attr, xcurs, ycurs, nbcols);
1200 // Do we need to wrap ?
1201 if (xcurs == nbcols) {
1205 // Do we need to scroll ?
1206 if (ycurs == nbrows) {
1207 if (GET_GLOBAL(vga_modes[line].class) == TEXT)
1208 biosfn_scroll(0x01, 0x07, 0, 0, nbrows - 1, nbcols - 1, page,
1211 biosfn_scroll(0x01, 0x00, 0, 0, nbrows - 1, nbcols - 1, page,
1215 // Set the cursor for the page
1219 biosfn_set_cursor_pos(page, cursor);
1222 // -------------------------------------------------------------------
1224 biosfn_get_video_mode(struct bregs *regs)
1226 regs->bh = GET_BDA(video_page);
1227 regs->al = GET_BDA(video_mode) | (GET_BDA(video_ctl) & 0x80);
1228 regs->ah = GET_BDA(video_cols);
1231 // -------------------------------------------------------------------
1233 biosfn_set_overscan_border_color(struct bregs *regs)
1235 inb(VGAREG_ACTL_RESET);
1236 outb(0x11, VGAREG_ACTL_ADDRESS);
1237 outb(regs->bh, VGAREG_ACTL_WRITE_DATA);
1238 outb(0x20, VGAREG_ACTL_ADDRESS);
1241 // -------------------------------------------------------------------
1243 biosfn_set_all_palette_reg(struct bregs *regs)
1245 inb(VGAREG_ACTL_RESET);
1247 u8 *data = (u8*)(regs->dx + 0);
1249 for (i = 0; i < 0x10; i++) {
1250 outb(i, VGAREG_ACTL_ADDRESS);
1251 u8 val = GET_FARVAR(regs->es, *data);
1252 outb(val, VGAREG_ACTL_WRITE_DATA);
1255 outb(0x11, VGAREG_ACTL_ADDRESS);
1256 outb(GET_FARVAR(regs->es, *data), VGAREG_ACTL_WRITE_DATA);
1257 outb(0x20, VGAREG_ACTL_ADDRESS);
1260 // -------------------------------------------------------------------
1262 biosfn_toggle_intensity(struct bregs *regs)
1264 inb(VGAREG_ACTL_RESET);
1265 outb(0x10, VGAREG_ACTL_ADDRESS);
1266 u8 val = (inb(VGAREG_ACTL_READ_DATA) & 0x7f) | ((regs->bl & 0x01) << 3);
1267 outb(val, VGAREG_ACTL_WRITE_DATA);
1268 outb(0x20, VGAREG_ACTL_ADDRESS);
1271 // -------------------------------------------------------------------
1273 biosfn_set_single_palette_reg(u8 reg, u8 val)
1275 inb(VGAREG_ACTL_RESET);
1276 outb(reg, VGAREG_ACTL_ADDRESS);
1277 outb(val, VGAREG_ACTL_WRITE_DATA);
1278 outb(0x20, VGAREG_ACTL_ADDRESS);
1281 // -------------------------------------------------------------------
1283 biosfn_get_single_palette_reg(u8 reg)
1285 inb(VGAREG_ACTL_RESET);
1286 outb(reg, VGAREG_ACTL_ADDRESS);
1287 u8 v = inb(VGAREG_ACTL_READ_DATA);
1288 inb(VGAREG_ACTL_RESET);
1289 outb(0x20, VGAREG_ACTL_ADDRESS);
1293 // -------------------------------------------------------------------
1295 biosfn_read_overscan_border_color(struct bregs *regs)
1297 inb(VGAREG_ACTL_RESET);
1298 outb(0x11, VGAREG_ACTL_ADDRESS);
1299 regs->bh = inb(VGAREG_ACTL_READ_DATA);
1300 inb(VGAREG_ACTL_RESET);
1301 outb(0x20, VGAREG_ACTL_ADDRESS);
1304 // -------------------------------------------------------------------
1306 biosfn_get_all_palette_reg(struct bregs *regs)
1308 u8 *data = (u8*)(regs->dx + 0);
1310 for (i = 0; i < 0x10; i++) {
1311 inb(VGAREG_ACTL_RESET);
1312 outb(i, VGAREG_ACTL_ADDRESS);
1313 SET_FARVAR(regs->es, *data, inb(VGAREG_ACTL_READ_DATA));
1316 inb(VGAREG_ACTL_RESET);
1317 outb(0x11, VGAREG_ACTL_ADDRESS);
1318 SET_FARVAR(regs->es, *data, inb(VGAREG_ACTL_READ_DATA));
1319 inb(VGAREG_ACTL_RESET);
1320 outb(0x20, VGAREG_ACTL_ADDRESS);
1323 // -------------------------------------------------------------------
1325 biosfn_set_single_dac_reg(struct bregs *regs)
1327 outb(regs->bl, VGAREG_DAC_WRITE_ADDRESS);
1328 outb(regs->dh, VGAREG_DAC_DATA);
1329 outb(regs->ch, VGAREG_DAC_DATA);
1330 outb(regs->cl, VGAREG_DAC_DATA);
1333 // -------------------------------------------------------------------
1335 biosfn_set_all_dac_reg(struct bregs *regs)
1337 outb(regs->bl, VGAREG_DAC_WRITE_ADDRESS);
1338 u8 *data = (u8*)(regs->dx + 0);
1339 int count = regs->cx;
1341 outb(GET_FARVAR(regs->es, *data), VGAREG_DAC_DATA);
1343 outb(GET_FARVAR(regs->es, *data), VGAREG_DAC_DATA);
1345 outb(GET_FARVAR(regs->es, *data), VGAREG_DAC_DATA);
1351 // -------------------------------------------------------------------
1353 biosfn_select_video_dac_color_page(struct bregs *regs)
1355 inb(VGAREG_ACTL_RESET);
1356 outb(0x10, VGAREG_ACTL_ADDRESS);
1357 u8 val = inb(VGAREG_ACTL_READ_DATA);
1358 if (!(regs->bl & 0x01)) {
1359 val = (val & 0x7f) | (regs->bh << 7);
1360 outb(val, VGAREG_ACTL_WRITE_DATA);
1361 outb(0x20, VGAREG_ACTL_ADDRESS);
1364 inb(VGAREG_ACTL_RESET);
1365 outb(0x14, VGAREG_ACTL_ADDRESS);
1370 outb(bh, VGAREG_ACTL_WRITE_DATA);
1371 outb(0x20, VGAREG_ACTL_ADDRESS);
1374 // -------------------------------------------------------------------
1376 biosfn_read_single_dac_reg(struct bregs *regs)
1378 outb(regs->bl, VGAREG_DAC_READ_ADDRESS);
1379 regs->dh = inb(VGAREG_DAC_DATA);
1380 regs->ch = inb(VGAREG_DAC_DATA);
1381 regs->cl = inb(VGAREG_DAC_DATA);
1384 // -------------------------------------------------------------------
1386 biosfn_read_all_dac_reg(struct bregs *regs)
1388 outb(regs->bl, VGAREG_DAC_READ_ADDRESS);
1389 u8 *data = (u8*)(regs->dx + 0);
1390 int count = regs->cx;
1392 SET_FARVAR(regs->es, *data, inb(VGAREG_DAC_DATA));
1394 SET_FARVAR(regs->es, *data, inb(VGAREG_DAC_DATA));
1396 SET_FARVAR(regs->es, *data, inb(VGAREG_DAC_DATA));
1402 // -------------------------------------------------------------------
1404 biosfn_set_pel_mask(struct bregs *regs)
1406 outb(regs->bl, VGAREG_PEL_MASK);
1409 // -------------------------------------------------------------------
1411 biosfn_read_pel_mask(struct bregs *regs)
1413 regs->bl = inb(VGAREG_PEL_MASK);
1416 // -------------------------------------------------------------------
1418 biosfn_read_video_dac_state(struct bregs *regs)
1420 inb(VGAREG_ACTL_RESET);
1421 outb(0x10, VGAREG_ACTL_ADDRESS);
1422 u8 val1 = inb(VGAREG_ACTL_READ_DATA) >> 7;
1424 inb(VGAREG_ACTL_RESET);
1425 outb(0x14, VGAREG_ACTL_ADDRESS);
1426 u8 val2 = inb(VGAREG_ACTL_READ_DATA) & 0x0f;
1430 inb(VGAREG_ACTL_RESET);
1431 outb(0x20, VGAREG_ACTL_ADDRESS);
1437 // -------------------------------------------------------------------
1441 outw(0x0100, VGAREG_SEQU_ADDRESS);
1442 outw(0x0402, VGAREG_SEQU_ADDRESS);
1443 outw(0x0704, VGAREG_SEQU_ADDRESS);
1444 outw(0x0300, VGAREG_SEQU_ADDRESS);
1445 outw(0x0204, VGAREG_GRDC_ADDRESS);
1446 outw(0x0005, VGAREG_GRDC_ADDRESS);
1447 outw(0x0406, VGAREG_GRDC_ADDRESS);
1451 release_font_access()
1453 outw(0x0100, VGAREG_SEQU_ADDRESS);
1454 outw(0x0302, VGAREG_SEQU_ADDRESS);
1455 outw(0x0304, VGAREG_SEQU_ADDRESS);
1456 outw(0x0300, VGAREG_SEQU_ADDRESS);
1457 u16 v = inw(VGAREG_READ_MISC_OUTPUT);
1458 v = ((v & 0x01) << 10) | 0x0a06;
1459 outw(v, VGAREG_GRDC_ADDRESS);
1460 outw(0x0004, VGAREG_GRDC_ADDRESS);
1461 outw(0x1005, VGAREG_GRDC_ADDRESS);
1465 set_scan_lines(u8 lines)
1467 u16 crtc_addr, cols, vde;
1468 u8 crtc_r9, ovl, rows;
1470 crtc_addr = GET_BDA(crtc_address);
1471 outb(0x09, crtc_addr);
1472 crtc_r9 = inb(crtc_addr + 1);
1473 crtc_r9 = (crtc_r9 & 0xe0) | (lines - 1);
1474 outb(crtc_r9, crtc_addr + 1);
1476 biosfn_set_cursor_shape(0x06, 0x07);
1478 biosfn_set_cursor_shape(lines - 4, lines - 3);
1479 SET_BDA(char_height, lines);
1480 outb(0x12, crtc_addr);
1481 vde = inb(crtc_addr + 1);
1482 outb(0x07, crtc_addr);
1483 ovl = inb(crtc_addr + 1);
1484 vde += (((ovl & 0x02) << 7) + ((ovl & 0x40) << 3) + 1);
1486 SET_BDA(video_rows, rows - 1);
1487 cols = GET_BDA(video_cols);
1488 SET_BDA(video_pagesize, rows * cols * 2);
1492 biosfn_load_text_user_pat(u8 AL, u16 ES, u16 BP, u16 CX, u16 DX, u8 BL,
1496 u16 blockaddr = ((BL & 0x03) << 14) + ((BL & 0x04) << 11);
1498 for (i = 0; i < CX; i++) {
1499 void *src = (void*)(BP + i * BH);
1500 void *dest = (void*)(blockaddr + (DX + i) * 32);
1501 memcpy_far(0xA000, dest, ES, src, BH);
1503 release_font_access();
1509 biosfn_load_text_8_14_pat(u8 AL, u8 BL)
1512 u16 blockaddr = ((BL & 0x03) << 14) + ((BL & 0x04) << 11);
1514 for (i = 0; i < 0x100; i++) {
1516 void *dest = (void*)(blockaddr + i * 32);
1517 memcpy_far(0xA000, dest, 0xC000, &vgafont14[src], 14);
1519 release_font_access();
1525 biosfn_load_text_8_8_pat(u8 AL, u8 BL)
1528 u16 blockaddr = ((BL & 0x03) << 14) + ((BL & 0x04) << 11);
1530 for (i = 0; i < 0x100; i++) {
1532 void *dest = (void*)(blockaddr + i * 32);
1533 memcpy_far(0xA000, dest, 0xC000, &vgafont8[src], 8);
1535 release_font_access();
1540 // -------------------------------------------------------------------
1542 biosfn_set_text_block_specifier(struct bregs *regs)
1544 outw((regs->bl << 8) | 0x03, VGAREG_SEQU_ADDRESS);
1547 // -------------------------------------------------------------------
1549 biosfn_load_text_8_16_pat(u8 AL, u8 BL)
1552 u16 blockaddr = ((BL & 0x03) << 14) + ((BL & 0x04) << 11);
1554 for (i = 0; i < 0x100; i++) {
1556 void *dest = (void*)(blockaddr + i * 32);
1557 memcpy_far(0xA000, dest, 0xC000, &vgafont16[src], 16);
1559 release_font_access();
1564 // -------------------------------------------------------------------
1566 biosfn_get_font_info(u8 BH, u16 *ES, u16 *BP, u16 *CX, u16 *DX)
1570 u32 segoff = GET_IVT(0x1f).segoff;
1576 u32 segoff = GET_IVT(0x43).segoff;
1583 *BP = (u32)vgafont14;
1587 *BP = (u32)vgafont8;
1591 *BP = (u32)vgafont8 + 128 * 8;
1595 *BP = (u32)vgafont14alt;
1599 *BP = (u32)vgafont16;
1603 *BP = (u32)vgafont16alt;
1607 printf("Get font info BH(%02x) was discarded\n", BH);
1611 // Set byte/char of on screen font
1612 *CX = GET_BDA(char_height) & 0xff;
1614 // Set Highest char row
1615 *DX = GET_BDA(video_rows);
1618 // -------------------------------------------------------------------
1620 biosfn_get_ega_info(struct bregs *regs)
1622 regs->cx = GET_BDA(video_switches) & 0x0f;
1623 regs->ax = GET_BDA(crtc_address);
1624 if (regs->ax == VGAREG_MDA_CRTC_ADDRESS)
1630 // -------------------------------------------------------------------
1632 biosfn_select_vert_res(struct bregs *regs)
1634 u8 mctl = GET_BDA(modeset_ctl);
1635 u8 vswt = GET_BDA(video_switches);
1640 mctl = (mctl & ~0x10) | 0x80;
1641 vswt = (vswt & ~0x0f) | 0x08;
1646 vswt = (vswt & ~0x0f) | 0x09;
1650 mctl = (mctl & ~0x80) | 0x10;
1651 vswt = (vswt & ~0x0f) | 0x09;
1655 printf("Select vert res (%02x) was discarded\n");
1659 SET_BDA(modeset_ctl, mctl);
1660 SET_BDA(video_switches, vswt);
1665 biosfn_enable_default_palette_loading(struct bregs *regs)
1667 u8 v = (regs->al & 0x01) << 3;
1668 u8 mctl = GET_BDA(video_ctl) & ~0x08;
1669 SET_BDA(video_ctl, mctl | v);
1674 biosfn_enable_video_addressing(struct bregs *regs)
1676 u8 v = ((regs->al << 1) & 0x02) ^ 0x02;
1677 u8 v2 = inb(VGAREG_READ_MISC_OUTPUT) & ~0x02;
1678 outb(v | v2, VGAREG_WRITE_MISC_OUTPUT);
1684 biosfn_enable_grayscale_summing(struct bregs *regs)
1686 u8 v = ((regs->al << 1) & 0x02) ^ 0x02;
1687 u8 v2 = GET_BDA(modeset_ctl) & ~0x02;
1688 SET_BDA(modeset_ctl, v | v2);
1693 biosfn_enable_cursor_emulation(struct bregs *regs)
1695 u8 v = (regs->al & 0x01) ^ 0x01;
1696 u8 v2 = GET_BDA(modeset_ctl) & ~0x01;
1697 SET_BDA(modeset_ctl, v | v2);
1701 // -------------------------------------------------------------------
1703 biosfn_write_string(u8 flag, u8 page, u8 attr, u16 count, u8 row, u8 col,
1704 u16 seg, u8 *offset)
1706 u16 newcurs, oldcurs, dummy;
1709 // Read curs info for the page
1710 biosfn_get_cursor_pos(page, &dummy, &oldcurs);
1712 // if row=0xff special case : use current cursor position
1714 col = oldcurs & 0x00ff;
1715 row = (oldcurs & 0xff00) >> 8;
1721 biosfn_set_cursor_pos(page, newcurs);
1723 while (count-- != 0) {
1724 car = GET_FARVAR(seg, *offset);
1726 if ((flag & 0x02) != 0) {
1727 attr = GET_FARVAR(seg, *offset);
1731 biosfn_write_teletype(car, page, attr, WITH_ATTR);
1734 // Set back curs pos
1735 if ((flag & 0x01) == 0)
1736 biosfn_set_cursor_pos(page, oldcurs);
1739 // -------------------------------------------------------------------
1741 biosfn_read_display_code(struct bregs *regs)
1743 regs->bx = GET_BDA(dcc_index);
1748 biosfn_set_display_code(struct bregs *regs)
1750 SET_BDA(dcc_index, regs->bl);
1752 printf("Alternate Display code (%02x) was discarded", regs->bh);
1757 // -------------------------------------------------------------------
1759 biosfn_read_state_info(u16 BX, u16 ES, u16 DI)
1761 // Address of static functionality table
1762 SET_FARVAR(ES, *(u16*)(DI + 0x00), (u32)static_functionality);
1763 SET_FARVAR(ES, *(u16*)(DI + 0x02), 0xC000);
1765 // Hard coded copy from BIOS area. Should it be cleaner ?
1766 memcpy_far(ES, (void*)(DI + 0x04), SEG_BDA, (void*)0x49, 30);
1767 memcpy_far(ES, (void*)(DI + 0x22), SEG_BDA, (void*)0x84, 3);
1769 SET_FARVAR(ES, *(u8*)(DI + 0x25), GET_BDA(dcc_index));
1770 SET_FARVAR(ES, *(u8*)(DI + 0x26), 0);
1771 SET_FARVAR(ES, *(u8*)(DI + 0x27), 16);
1772 SET_FARVAR(ES, *(u8*)(DI + 0x28), 0);
1773 SET_FARVAR(ES, *(u8*)(DI + 0x29), 8);
1774 SET_FARVAR(ES, *(u8*)(DI + 0x2a), 2);
1775 SET_FARVAR(ES, *(u8*)(DI + 0x2b), 0);
1776 SET_FARVAR(ES, *(u8*)(DI + 0x2c), 0);
1777 SET_FARVAR(ES, *(u8*)(DI + 0x31), 3);
1778 SET_FARVAR(ES, *(u8*)(DI + 0x32), 0);
1780 memset_far(ES, (void*)(DI + 0x33), 0, 13);
1783 // -------------------------------------------------------------------
1784 // -------------------------------------------------------------------
1786 biosfn_read_video_state_size(u16 CX)
1792 size += (5 + 8 + 5) * 2 + 6;
1794 size += 3 + 256 * 3 + 1;
1799 biosfn_save_video_state(u16 CX, u16 ES, u16 BX)
1801 u16 i, crtc_addr, ar_index;
1803 crtc_addr = GET_BDA(crtc_address);
1805 SET_FARVAR(ES, *(u8*)(BX+0), inb(VGAREG_SEQU_ADDRESS));
1807 SET_FARVAR(ES, *(u8*)(BX+0), inb(crtc_addr));
1809 SET_FARVAR(ES, *(u8*)(BX+0), inb(VGAREG_GRDC_ADDRESS));
1811 inb(VGAREG_ACTL_RESET);
1812 ar_index = inb(VGAREG_ACTL_ADDRESS);
1813 SET_FARVAR(ES, *(u8*)(BX+0), ar_index);
1815 SET_FARVAR(ES, *(u8*)(BX+0), inb(VGAREG_READ_FEATURE_CTL));
1818 for (i = 1; i <= 4; i++) {
1819 outb(i, VGAREG_SEQU_ADDRESS);
1820 SET_FARVAR(ES, *(u8*)(BX+0), inb(VGAREG_SEQU_DATA));
1823 outb(0, VGAREG_SEQU_ADDRESS);
1824 SET_FARVAR(ES, *(u8*)(BX+0), inb(VGAREG_SEQU_DATA));
1827 for (i = 0; i <= 0x18; i++) {
1829 SET_FARVAR(ES, *(u8*)(BX+0), inb(crtc_addr + 1));
1833 for (i = 0; i <= 0x13; i++) {
1834 inb(VGAREG_ACTL_RESET);
1835 outb(i | (ar_index & 0x20), VGAREG_ACTL_ADDRESS);
1836 SET_FARVAR(ES, *(u8*)(BX+0), inb(VGAREG_ACTL_READ_DATA));
1839 inb(VGAREG_ACTL_RESET);
1841 for (i = 0; i <= 8; i++) {
1842 outb(i, VGAREG_GRDC_ADDRESS);
1843 SET_FARVAR(ES, *(u8*)(BX+0), inb(VGAREG_GRDC_DATA));
1847 SET_FARVAR(ES, *(u16*)(BX+0), crtc_addr);
1850 /* XXX: read plane latches */
1851 SET_FARVAR(ES, *(u8*)(BX+0), 0);
1853 SET_FARVAR(ES, *(u8*)(BX+0), 0);
1855 SET_FARVAR(ES, *(u8*)(BX+0), 0);
1857 SET_FARVAR(ES, *(u8*)(BX+0), 0);
1861 SET_FARVAR(ES, *(u8*)(BX+0), GET_BDA(video_mode));
1863 SET_FARVAR(ES, *(u16*)(BX+0), GET_BDA(video_cols));
1865 SET_FARVAR(ES, *(u16*)(BX+0), GET_BDA(video_pagesize));
1867 SET_FARVAR(ES, *(u16*)(BX+0), GET_BDA(crtc_address));
1869 SET_FARVAR(ES, *(u8*)(BX+0), GET_BDA(video_rows));
1871 SET_FARVAR(ES, *(u16*)(BX+0), GET_BDA(char_height));
1873 SET_FARVAR(ES, *(u8*)(BX+0), GET_BDA(video_ctl));
1875 SET_FARVAR(ES, *(u8*)(BX+0), GET_BDA(video_switches));
1877 SET_FARVAR(ES, *(u8*)(BX+0), GET_BDA(modeset_ctl));
1879 SET_FARVAR(ES, *(u16*)(BX+0), GET_BDA(cursor_type));
1881 for (i = 0; i < 8; i++) {
1882 SET_FARVAR(ES, *(u16*)(BX+0), GET_BDA(cursor_pos[i]));
1885 SET_FARVAR(ES, *(u16*)(BX+0), GET_BDA(video_pagestart));
1887 SET_FARVAR(ES, *(u8*)(BX+0), GET_BDA(video_page));
1890 SET_FARVAR(ES, *(u16*)(BX+0), GET_FARVAR(0, *(u16*)(0x1f * 4)));
1892 SET_FARVAR(ES, *(u16*)(BX+0), GET_FARVAR(0, *(u16*)(0x1f * 4 + 2)));
1894 SET_FARVAR(ES, *(u16*)(BX+0), GET_FARVAR(0, *(u16*)(0x43 * 4)));
1896 SET_FARVAR(ES, *(u16*)(BX+0), GET_FARVAR(0, *(u16*)(0x43 * 4 + 2)));
1900 /* XXX: check this */
1901 SET_FARVAR(ES, *(u8*)(BX+0), inb(VGAREG_DAC_STATE));
1902 BX++; /* read/write mode dac */
1903 SET_FARVAR(ES, *(u8*)(BX+0), inb(VGAREG_DAC_WRITE_ADDRESS));
1904 BX++; /* pix address */
1905 SET_FARVAR(ES, *(u8*)(BX+0), inb(VGAREG_PEL_MASK));
1907 // Set the whole dac always, from 0
1908 outb(0x00, VGAREG_DAC_WRITE_ADDRESS);
1909 for (i = 0; i < 256 * 3; i++) {
1910 SET_FARVAR(ES, *(u8*)(BX+0), inb(VGAREG_DAC_DATA));
1913 SET_FARVAR(ES, *(u8*)(BX+0), 0);
1914 BX++; /* color select register */
1920 biosfn_restore_video_state(u16 CX, u16 ES, u16 BX)
1922 u16 i, crtc_addr, v, addr1, ar_index;
1925 // Reset Attribute Ctl flip-flop
1926 inb(VGAREG_ACTL_RESET);
1928 crtc_addr = GET_FARVAR(ES, *(u16*)(BX + 0x40));
1932 for (i = 1; i <= 4; i++) {
1933 outb(i, VGAREG_SEQU_ADDRESS);
1934 outb(GET_FARVAR(ES, *(u8*)(BX+0)), VGAREG_SEQU_DATA);
1937 outb(0, VGAREG_SEQU_ADDRESS);
1938 outb(GET_FARVAR(ES, *(u8*)(BX+0)), VGAREG_SEQU_DATA);
1941 // Disable CRTC write protection
1942 outw(0x0011, crtc_addr);
1944 for (i = 0; i <= 0x18; i++) {
1947 outb(GET_FARVAR(ES, *(u8*)(BX+0)), crtc_addr + 1);
1951 // select crtc base address
1952 v = inb(VGAREG_READ_MISC_OUTPUT) & ~0x01;
1953 if (crtc_addr == VGAREG_VGA_CRTC_ADDRESS)
1955 outb(v, VGAREG_WRITE_MISC_OUTPUT);
1957 // enable write protection if needed
1958 outb(0x11, crtc_addr);
1959 outb(GET_FARVAR(ES, *(u8*)(BX - 0x18 + 0x11)), crtc_addr + 1);
1961 // Set Attribute Ctl
1962 ar_index = GET_FARVAR(ES, *(u8*)(addr1 + 0x03));
1963 inb(VGAREG_ACTL_RESET);
1964 for (i = 0; i <= 0x13; i++) {
1965 outb(i | (ar_index & 0x20), VGAREG_ACTL_ADDRESS);
1966 outb(GET_FARVAR(ES, *(u8*)(BX+0)), VGAREG_ACTL_WRITE_DATA);
1969 outb(ar_index, VGAREG_ACTL_ADDRESS);
1970 inb(VGAREG_ACTL_RESET);
1972 for (i = 0; i <= 8; i++) {
1973 outb(i, VGAREG_GRDC_ADDRESS);
1974 outb(GET_FARVAR(ES, *(u8*)(BX+0)), VGAREG_GRDC_DATA);
1977 BX += 2; /* crtc_addr */
1978 BX += 4; /* plane latches */
1980 outb(GET_FARVAR(ES, *(u8*)(addr1+0)), VGAREG_SEQU_ADDRESS);
1982 outb(GET_FARVAR(ES, *(u8*)(addr1+0)), crtc_addr);
1984 outb(GET_FARVAR(ES, *(u8*)(addr1+0)), VGAREG_GRDC_ADDRESS);
1987 outb(GET_FARVAR(ES, *(u8*)(addr1+0)), crtc_addr - 0x4 + 0xa);
1991 SET_BDA(video_mode, GET_FARVAR(ES, *(u8*)(BX+0)));
1993 SET_BDA(video_cols, GET_FARVAR(ES, *(u16*)(BX+0)));
1995 SET_BDA(video_pagesize, GET_FARVAR(ES, *(u16*)(BX+0)));
1997 SET_BDA(crtc_address, GET_FARVAR(ES, *(u16*)(BX+0)));
1999 SET_BDA(video_rows, GET_FARVAR(ES, *(u8*)(BX+0)));
2001 SET_BDA(char_height, GET_FARVAR(ES, *(u16*)(BX+0)));
2003 SET_BDA(video_ctl, GET_FARVAR(ES, *(u8*)(BX+0)));
2005 SET_BDA(video_switches, GET_FARVAR(ES, *(u8*)(BX+0)));
2007 SET_BDA(modeset_ctl, GET_FARVAR(ES, *(u8*)(BX+0)));
2009 SET_BDA(cursor_type, GET_FARVAR(ES, *(u16*)(BX+0)));
2011 for (i = 0; i < 8; i++) {
2012 SET_BDA(cursor_pos[i], GET_FARVAR(ES, *(u16*)(BX+0)));
2015 SET_BDA(video_pagestart, GET_FARVAR(ES, *(u16*)(BX+0)));
2017 SET_BDA(video_page, GET_FARVAR(ES, *(u8*)(BX+0)));
2020 SET_IVT(0x1f, GET_FARVAR(ES, *(u16*)(BX+2)), GET_FARVAR(ES, *(u16*)(BX+0)));
2022 SET_IVT(0x43, GET_FARVAR(ES, *(u16*)(BX+2)), GET_FARVAR(ES, *(u16*)(BX+0)));
2027 v = GET_FARVAR(ES, *(u8*)(BX+0));
2029 outb(GET_FARVAR(ES, *(u8*)(BX+0)), VGAREG_PEL_MASK);
2031 // Set the whole dac always, from 0
2032 outb(0x00, VGAREG_DAC_WRITE_ADDRESS);
2033 for (i = 0; i < 256 * 3; i++) {
2034 outb(GET_FARVAR(ES, *(u8*)(BX+0)), VGAREG_DAC_DATA);
2038 outb(v, VGAREG_DAC_WRITE_ADDRESS);
2044 /****************************************************************
2045 * VGA int 10 handler
2046 ****************************************************************/
2049 handle_1000(struct bregs *regs)
2052 biosfn_set_video_mode(regs->al);
2053 switch(regs->al & 0x7F) {
2072 handle_1001(struct bregs *regs)
2074 biosfn_set_cursor_shape(regs->ch, regs->cl);
2078 handle_1002(struct bregs *regs)
2080 biosfn_set_cursor_pos(regs->bh, regs->dx);
2084 handle_1003(struct bregs *regs)
2086 biosfn_get_cursor_pos(regs->bh, ®s->cx, ®s->dx);
2089 // Read light pen pos (unimplemented)
2091 handle_1004(struct bregs *regs)
2094 regs->ax = regs->bx = regs->cx = regs->dx = 0;
2098 handle_1005(struct bregs *regs)
2100 biosfn_set_active_page(regs->al);
2104 handle_1006(struct bregs *regs)
2106 biosfn_scroll(regs->al, regs->bh, regs->ch, regs->cl, regs->dh, regs->dl
2111 handle_1007(struct bregs *regs)
2113 biosfn_scroll(regs->al, regs->bh, regs->ch, regs->cl, regs->dh, regs->dl
2114 , 0xFF, SCROLL_DOWN);
2118 handle_1008(struct bregs *regs)
2121 biosfn_read_char_attr(regs->bh, ®s->ax);
2125 handle_1009(struct bregs *regs)
2128 biosfn_write_char_attr(regs->al, regs->bh, regs->bl, regs->cx);
2132 handle_100a(struct bregs *regs)
2135 biosfn_write_char_only(regs->al, regs->bh, regs->bl, regs->cx);
2140 handle_100b00(struct bregs *regs)
2143 biosfn_set_border_color(regs);
2147 handle_100b01(struct bregs *regs)
2150 biosfn_set_palette(regs);
2154 handle_100bXX(struct bregs *regs)
2160 handle_100b(struct bregs *regs)
2163 case 0x00: handle_100b00(regs); break;
2164 case 0x01: handle_100b01(regs); break;
2165 default: handle_100bXX(regs); break;
2171 handle_100c(struct bregs *regs)
2174 biosfn_write_pixel(regs->bh, regs->al, regs->cx, regs->dx);
2178 handle_100d(struct bregs *regs)
2181 biosfn_read_pixel(regs->bh, regs->cx, regs->dx, ®s->ax);
2185 handle_100e(struct bregs *regs)
2187 // Ralf Brown Interrupt list is WRONG on bh(page)
2188 // We do output only on the current page !
2189 biosfn_write_teletype(regs->al, 0xff, regs->bl, NO_ATTR);
2193 handle_100f(struct bregs *regs)
2196 biosfn_get_video_mode(regs);
2201 handle_101000(struct bregs *regs)
2203 if (regs->bl > 0x14)
2205 biosfn_set_single_palette_reg(regs->bl, regs->bh);
2209 handle_101001(struct bregs *regs)
2212 biosfn_set_overscan_border_color(regs);
2216 handle_101002(struct bregs *regs)
2219 biosfn_set_all_palette_reg(regs);
2223 handle_101003(struct bregs *regs)
2226 biosfn_toggle_intensity(regs);
2230 handle_101007(struct bregs *regs)
2232 if (regs->bl > 0x14)
2234 regs->bh = biosfn_get_single_palette_reg(regs->bl);
2238 handle_101008(struct bregs *regs)
2241 biosfn_read_overscan_border_color(regs);
2245 handle_101009(struct bregs *regs)
2248 biosfn_get_all_palette_reg(regs);
2252 handle_101010(struct bregs *regs)
2255 biosfn_set_single_dac_reg(regs);
2259 handle_101012(struct bregs *regs)
2262 biosfn_set_all_dac_reg(regs);
2266 handle_101013(struct bregs *regs)
2269 biosfn_select_video_dac_color_page(regs);
2273 handle_101015(struct bregs *regs)
2276 biosfn_read_single_dac_reg(regs);
2280 handle_101017(struct bregs *regs)
2283 biosfn_read_all_dac_reg(regs);
2287 handle_101018(struct bregs *regs)
2290 biosfn_set_pel_mask(regs);
2294 handle_101019(struct bregs *regs)
2297 biosfn_read_pel_mask(regs);
2301 handle_10101a(struct bregs *regs)
2304 biosfn_read_video_dac_state(regs);
2308 handle_10101b(struct bregs *regs)
2310 biosfn_perform_gray_scale_summing(regs->bx, regs->cx);
2314 handle_1010XX(struct bregs *regs)
2320 handle_1010(struct bregs *regs)
2323 case 0x00: handle_101000(regs); break;
2324 case 0x01: handle_101001(regs); break;
2325 case 0x02: handle_101002(regs); break;
2326 case 0x03: handle_101003(regs); break;
2327 case 0x07: handle_101007(regs); break;
2328 case 0x08: handle_101008(regs); break;
2329 case 0x09: handle_101009(regs); break;
2330 case 0x10: handle_101010(regs); break;
2331 case 0x12: handle_101012(regs); break;
2332 case 0x13: handle_101013(regs); break;
2333 case 0x15: handle_101015(regs); break;
2334 case 0x17: handle_101017(regs); break;
2335 case 0x18: handle_101018(regs); break;
2336 case 0x19: handle_101019(regs); break;
2337 case 0x1a: handle_10101a(regs); break;
2338 case 0x1b: handle_10101b(regs); break;
2339 default: handle_1010XX(regs); break;
2345 handle_101100(struct bregs *regs)
2348 biosfn_load_text_user_pat(regs->al, regs->es, 0 // XXX - regs->bp
2349 , regs->cx, regs->dx, regs->bl, regs->bh);
2353 handle_101101(struct bregs *regs)
2356 biosfn_load_text_8_14_pat(regs->al, regs->bl);
2360 handle_101102(struct bregs *regs)
2363 biosfn_load_text_8_8_pat(regs->al, regs->bl);
2367 handle_101103(struct bregs *regs)
2370 biosfn_set_text_block_specifier(regs);
2374 handle_101104(struct bregs *regs)
2377 biosfn_load_text_8_16_pat(regs->al, regs->bl);
2381 handle_101110(struct bregs *regs)
2383 handle_101100(regs);
2387 handle_101111(struct bregs *regs)
2389 handle_101101(regs);
2393 handle_101112(struct bregs *regs)
2395 handle_101102(regs);
2399 handle_101114(struct bregs *regs)
2401 handle_101104(regs);
2405 handle_101130(struct bregs *regs)
2408 biosfn_get_font_info(regs->bh, ®s->es, 0 // ®s->bp
2409 , ®s->cx, ®s->dx);
2413 handle_1011XX(struct bregs *regs)
2419 handle_1011(struct bregs *regs)
2422 case 0x00: handle_101100(regs); break;
2423 case 0x01: handle_101101(regs); break;
2424 case 0x02: handle_101102(regs); break;
2425 case 0x03: handle_101103(regs); break;
2426 case 0x04: handle_101104(regs); break;
2427 case 0x10: handle_101110(regs); break;
2428 case 0x11: handle_101111(regs); break;
2429 case 0x12: handle_101112(regs); break;
2430 case 0x14: handle_101114(regs); break;
2431 case 0x30: handle_101130(regs); break;
2432 default: handle_1011XX(regs); break;
2438 handle_101210(struct bregs *regs)
2441 biosfn_get_ega_info(regs);
2445 handle_101230(struct bregs *regs)
2448 biosfn_select_vert_res(regs);
2452 handle_101231(struct bregs *regs)
2455 biosfn_enable_default_palette_loading(regs);
2459 handle_101232(struct bregs *regs)
2462 biosfn_enable_video_addressing(regs);
2466 handle_101233(struct bregs *regs)
2469 biosfn_enable_grayscale_summing(regs);
2473 handle_101234(struct bregs *regs)
2476 biosfn_enable_cursor_emulation(regs);
2480 handle_101235(struct bregs *regs)
2487 handle_101236(struct bregs *regs)
2494 handle_1012XX(struct bregs *regs)
2500 handle_1012(struct bregs *regs)
2503 case 0x10: handle_101210(regs); break;
2504 case 0x30: handle_101230(regs); break;
2505 case 0x31: handle_101231(regs); break;
2506 case 0x32: handle_101232(regs); break;
2507 case 0x33: handle_101233(regs); break;
2508 case 0x34: handle_101234(regs); break;
2509 case 0x35: handle_101235(regs); break;
2510 case 0x36: handle_101236(regs); break;
2511 default: handle_1012XX(regs); break;
2514 // XXX - cirrus has 1280, 1281, 1282, 1285, 129a, 12a0, 12a1, 12a2, 12ae
2519 handle_1013(struct bregs *regs)
2522 biosfn_write_string(regs->al, regs->bh, regs->bl, regs->cx
2523 , regs->dh, regs->dl, regs->es, 0); // regs->bp);
2528 handle_101a00(struct bregs *regs)
2531 biosfn_read_display_code(regs);
2535 handle_101a01(struct bregs *regs)
2538 biosfn_set_display_code(regs);
2542 handle_101aXX(struct bregs *regs)
2548 handle_101a(struct bregs *regs)
2551 case 0x00: handle_101a00(regs); break;
2552 case 0x01: handle_101a01(regs); break;
2553 default: handle_101aXX(regs); break;
2559 handle_101b(struct bregs *regs)
2562 biosfn_read_state_info(regs->bx, regs->es, regs->di);
2568 handle_101c00(struct bregs *regs)
2571 regs->bx = biosfn_read_video_state_size(regs->cx);
2575 handle_101c01(struct bregs *regs)
2578 biosfn_save_video_state(regs->cx, regs->es, regs->bx);
2582 handle_101c02(struct bregs *regs)
2585 biosfn_restore_video_state(regs->cx, regs->es, regs->bx);
2589 handle_101cXX(struct bregs *regs)
2595 handle_101c(struct bregs *regs)
2598 case 0x00: handle_101c00(regs); break;
2599 case 0x01: handle_101c01(regs); break;
2600 case 0x02: handle_101c02(regs); break;
2601 default: handle_101cXX(regs); break;
2607 handle_104f00(struct bregs *regs)
2609 // XXX - vbe_biosfn_return_controller_information(&AX,ES,DI);
2610 // XXX - OR cirrus_vesa_00h
2614 handle_104f01(struct bregs *regs)
2616 // XXX - vbe_biosfn_return_mode_information(&AX,CX,ES,DI);
2617 // XXX - OR cirrus_vesa_01h
2621 handle_104f02(struct bregs *regs)
2623 // XXX - vbe_biosfn_set_mode(&AX,BX,ES,DI);
2624 // XXX - OR cirrus_vesa_02h
2628 handle_104f03(struct bregs *regs)
2630 // XXX - vbe_biosfn_return_current_mode
2631 // XXX - OR cirrus_vesa_03h
2635 handle_104f04(struct bregs *regs)
2637 // XXX - vbe_biosfn_save_restore_state(&AX, CX, DX, ES, &BX);
2641 handle_104f05(struct bregs *regs)
2643 // XXX - vbe_biosfn_display_window_control
2644 // XXX - OR cirrus_vesa_05h
2648 handle_104f06(struct bregs *regs)
2650 // XXX - vbe_biosfn_set_get_logical_scan_line_length
2651 // XXX - OR cirrus_vesa_06h
2655 handle_104f07(struct bregs *regs)
2657 // XXX - vbe_biosfn_set_get_display_start
2658 // XXX - OR cirrus_vesa_07h
2662 handle_104f08(struct bregs *regs)
2664 // XXX - vbe_biosfn_set_get_dac_palette_format
2668 handle_104f0a(struct bregs *regs)
2670 // XXX - vbe_biosfn_return_protected_mode_interface
2674 handle_104fXX(struct bregs *regs)
2681 handle_104f(struct bregs *regs)
2684 handle_104fXX(regs);
2688 // XXX - check vbe_has_vbe_display()?
2691 case 0x00: handle_104f00(regs); break;
2692 case 0x01: handle_104f01(regs); break;
2693 case 0x02: handle_104f02(regs); break;
2694 case 0x03: handle_104f03(regs); break;
2695 case 0x04: handle_104f04(regs); break;
2696 case 0x05: handle_104f05(regs); break;
2697 case 0x06: handle_104f06(regs); break;
2698 case 0x07: handle_104f07(regs); break;
2699 case 0x08: handle_104f08(regs); break;
2700 case 0x0a: handle_104f0a(regs); break;
2701 default: handle_104fXX(regs); break;
2707 handle_10XX(struct bregs *regs)
2712 // INT 10h Video Support Service Entry Point
2714 handle_10(struct bregs *regs)
2716 debug_enter(regs, DEBUG_VGA_10);
2718 case 0x00: handle_1000(regs); break;
2719 case 0x01: handle_1001(regs); break;
2720 case 0x02: handle_1002(regs); break;
2721 case 0x03: handle_1003(regs); break;
2722 case 0x04: handle_1004(regs); break;
2723 case 0x05: handle_1005(regs); break;
2724 case 0x06: handle_1006(regs); break;
2725 case 0x07: handle_1007(regs); break;
2726 case 0x08: handle_1008(regs); break;
2727 case 0x09: handle_1009(regs); break;
2728 case 0x0a: handle_100a(regs); break;
2729 case 0x0b: handle_100b(regs); break;
2730 case 0x0c: handle_100c(regs); break;
2731 case 0x0d: handle_100d(regs); break;
2732 case 0x0e: handle_100e(regs); break;
2733 case 0x0f: handle_100f(regs); break;
2734 case 0x10: handle_1010(regs); break;
2735 case 0x11: handle_1011(regs); break;
2736 case 0x12: handle_1012(regs); break;
2737 case 0x13: handle_1013(regs); break;
2738 case 0x1a: handle_101a(regs); break;
2739 case 0x1b: handle_101b(regs); break;
2740 case 0x1c: handle_101c(regs); break;
2741 case 0x4f: handle_104f(regs); break;
2742 default: handle_10XX(regs); break;
2747 /****************************************************************
2749 ****************************************************************/
2754 // init detected hardware BIOS Area
2755 // set 80x25 color (not clear from RBIL but usual)
2756 u16 eqf = GET_BDA(equipment_list_flags);
2757 SET_BDA(equipment_list_flags, (eqf & 0xffcf) | 0x20);
2759 // Just for the first int10 find its children
2761 // the default char height
2762 SET_BDA(char_height, 0x10);
2765 SET_BDA(video_ctl, 0x60);
2767 // Set the basic screen we have
2768 SET_BDA(video_switches, 0xf9);
2770 // Set the basic modeset options
2771 SET_BDA(modeset_ctl, 0x51);
2773 // Set the default MSR
2774 SET_BDA(video_msr, 0x09);
2780 // switch to color mode and enable CPU access 480 lines
2781 outb(0xc3, VGAREG_WRITE_MISC_OUTPUT);
2782 // more than 64k 3C4/04
2783 outb(0x04, VGAREG_SEQU_ADDRESS);
2784 outb(0x02, VGAREG_SEQU_DATA);
2788 vga_post(struct bregs *regs)
2790 debug_enter(regs, DEBUG_VGA_POST);
2798 extern void entry_10(void);
2799 SET_IVT(0x10, 0xC000, (u32)entry_10);
2804 // XXX - clear screen and display info
2807 SET_VGA(video_save_pointer_table[0], (u32)video_param_table);
2808 SET_VGA(video_save_pointer_table[1], 0xC000);
2811 extern u8 _rom_header_size, _rom_header_checksum;
2812 SET_VGA(_rom_header_checksum, 0);
2813 u8 sum = -checksum_far(0xC000, 0, _rom_header_size * 512);
2814 SET_VGA(_rom_header_checksum, sum);