1 // VGA bios implementation
3 // Copyright (C) 2009 Kevin O'Connor <kevin@koconnor.net>
4 // Copyright (C) 2001-2008 the LGPL VGABios developers Team
6 // This file may be distributed under the terms of the GNU LGPLv3 license.
10 // * introduce "struct vregs", or add ebp to struct bregs.
11 // * define structs for save/restore state
12 // * review correctness of converted asm by comparing with RBIL
13 // * refactor redundant code into sub-functions
14 // * See if there is a method to the in/out stuff that can be encapsulated.
15 // * remove "biosfn" prefixes
16 // * don't hardcode 0xc000
17 // * add defs for 0xa000/0xb800
18 // * verify all funcs static
20 // * convert vbe/clext code
22 // * separate code into separate files
23 // * extract hw code from bios interfaces
25 #include "bregs.h" // struct bregs
26 #include "biosvar.h" // GET_BDA
27 #include "util.h" // memset
28 #include "vgatables.h" // vga_modes
32 #define CONFIG_CIRRUS 0
35 #define DEBUG_VGA_POST 1
36 #define DEBUG_VGA_10 3
38 #define SET_VGA(var, val) SET_FARVAR(0xc000, (var), (val))
41 // ===================================================================
45 // ===================================================================
47 // -------------------------------------------------------------------
49 call16_vgaint(u32 eax, u32 ebx)
62 memcpy16_far(u16 d_seg, void *d_far, u16 s_seg, const void *s_far, size_t len)
64 memcpy_far(d_seg, d_far, s_seg, s_far, len);
68 // ===================================================================
72 // ===================================================================
74 // -------------------------------------------------------------------
76 biosfn_perform_gray_scale_summing(u16 start, u16 count)
78 inb(VGAREG_ACTL_RESET);
79 outb(0x00, VGAREG_ACTL_ADDRESS);
82 for (i = start; i < start+count; i++) {
83 // set read address and switch to read mode
84 outb(i, VGAREG_DAC_READ_ADDRESS);
85 // get 6-bit wide RGB data values
86 u8 r = inb(VGAREG_DAC_DATA);
87 u8 g = inb(VGAREG_DAC_DATA);
88 u8 b = inb(VGAREG_DAC_DATA);
90 // intensity = ( 0.3 * Red ) + ( 0.59 * Green ) + ( 0.11 * Blue )
91 u16 intensity = ((77 * r + 151 * g + 28 * b) + 0x80) >> 8;
96 // set write address and switch to write mode
97 outb(i, VGAREG_DAC_WRITE_ADDRESS);
98 // write new intensity value
99 outb(intensity & 0xff, VGAREG_DAC_DATA);
100 outb(intensity & 0xff, VGAREG_DAC_DATA);
101 outb(intensity & 0xff, VGAREG_DAC_DATA);
103 inb(VGAREG_ACTL_RESET);
104 outb(0x20, VGAREG_ACTL_ADDRESS);
107 // -------------------------------------------------------------------
109 biosfn_set_cursor_shape(u8 CH, u8 CL)
114 u16 curs = (CH << 8) + CL;
115 SET_BDA(cursor_type, curs);
117 u8 modeset_ctl = GET_BDA(modeset_ctl);
118 u16 cheight = GET_BDA(char_height);
119 if ((modeset_ctl & 0x01) && (cheight > 8) && (CL < 8) && (CH < 0x20)) {
121 CH = ((CH + 1) * cheight / 8) - 1;
123 CH = ((CL + 1) * cheight / 8) - 2;
124 CL = ((CL + 1) * cheight / 8) - 1;
126 // CTRC regs 0x0a and 0x0b
127 u16 crtc_addr = GET_BDA(crtc_address);
128 outb(0x0a, crtc_addr);
129 outb(CH, crtc_addr + 1);
130 outb(0x0b, crtc_addr);
131 outb(CL, crtc_addr + 1);
134 // -------------------------------------------------------------------
136 biosfn_set_cursor_pos(u8 page, u16 cursor)
138 // Should not happen...
143 SET_BDA(cursor_pos[page], cursor);
145 // Set the hardware cursor
146 u8 current = GET_BDA(video_page);
150 // Get the dimensions
151 u16 nbcols = GET_BDA(video_cols);
152 u16 nbrows = GET_BDA(video_rows) + 1;
154 u8 xcurs = cursor & 0x00ff;
155 u8 ycurs = (cursor & 0xff00) >> 8;
157 // Calculate the address knowing nbcols nbrows and page num
158 u16 address = SCREEN_IO_START(nbcols, nbrows, page) + xcurs + ycurs * nbcols;
160 // CRTC regs 0x0e and 0x0f
161 u16 crtc_addr = GET_BDA(crtc_address);
162 outb(0x0e, crtc_addr);
163 outb((address & 0xff00) >> 8, crtc_addr + 1);
164 outb(0x0f, crtc_addr);
165 outb(address & 0x00ff, crtc_addr + 1);
168 // -------------------------------------------------------------------
170 biosfn_get_cursor_pos(u8 page, u16 *shape, u16 *pos)
178 // FIXME should handle VGA 14/16 lines
179 *shape = GET_BDA(cursor_type);
180 *pos = GET_BDA(cursor_pos[page]);
183 // -------------------------------------------------------------------
185 biosfn_set_active_page(u8 page)
191 struct vgamode_s *vmode_g = find_vga_entry(GET_BDA(video_mode));
195 // Get pos curs pos for the right page
197 biosfn_get_cursor_pos(page, &dummy, &cursor);
200 if (GET_GLOBAL(vmode_g->class) == TEXT) {
201 // Get the dimensions
202 u16 nbcols = GET_BDA(video_cols);
203 u16 nbrows = GET_BDA(video_rows) + 1;
205 // Calculate the address knowing nbcols nbrows and page num
206 address = SCREEN_MEM_START(nbcols, nbrows, page);
207 SET_BDA(video_pagestart, address);
210 address = SCREEN_IO_START(nbcols, nbrows, page);
212 struct VideoParam_s *vparam_g = GET_GLOBAL(vmode_g->vparam);
213 address = page * GET_GLOBAL(vparam_g->slength);
216 // CRTC regs 0x0c and 0x0d
217 u16 crtc_addr = GET_BDA(crtc_address);
218 outb(0x0c, crtc_addr);
219 outb((address & 0xff00) >> 8, crtc_addr + 1);
220 outb(0x0d, crtc_addr);
221 outb(address & 0x00ff, crtc_addr + 1);
223 // And change the BIOS page
224 SET_BDA(video_page, page);
226 dprintf(1, "Set active page %02x address %04x\n", page, address);
228 // Display the cursor, now the page is active
229 biosfn_set_cursor_pos(page, cursor);
233 biosfn_set_video_mode(u8 mode)
234 { // mode: Bit 7 is 1 if no clear screen
236 cirrus_set_video_mode(mode);
239 if (vbe_has_vbe_display())
240 dispi_set_enable(VBE_DISPI_DISABLED);
244 u8 noclearmem = mode & 0x80;
247 // find the entry in the video modes
248 struct vgamode_s *vmode_g = find_vga_entry(mode);
249 dprintf(1, "mode search %02x found %p\n", mode, vmode_g);
253 struct VideoParam_s *vparam_g = GET_GLOBAL(vmode_g->vparam);
254 u16 twidth = GET_GLOBAL(vparam_g->twidth);
255 u16 theightm1 = GET_GLOBAL(vparam_g->theightm1);
256 u16 cheight = GET_GLOBAL(vparam_g->cheight);
258 // Read the bios mode set control
259 u8 modeset_ctl = GET_BDA(modeset_ctl);
261 // Then we know the number of lines
264 // if palette loading (bit 3 of modeset ctl = 0)
265 if ((modeset_ctl & 0x08) == 0) { // Set the PEL mask
266 outb(GET_GLOBAL(vmode_g->pelmask), VGAREG_PEL_MASK);
268 // Set the whole dac always, from 0
269 outb(0x00, VGAREG_DAC_WRITE_ADDRESS);
271 // From which palette
272 u8 *palette_g = GET_GLOBAL(vmode_g->dac);
273 u16 palsize = GET_GLOBAL(vmode_g->dacsize);
274 // Always 256*3 values
276 for (i = 0; i < 0x0100; i++) {
278 outb(GET_GLOBAL(palette_g[(i * 3) + 0]), VGAREG_DAC_DATA);
279 outb(GET_GLOBAL(palette_g[(i * 3) + 1]), VGAREG_DAC_DATA);
280 outb(GET_GLOBAL(palette_g[(i * 3) + 2]), VGAREG_DAC_DATA);
282 outb(0, VGAREG_DAC_DATA);
283 outb(0, VGAREG_DAC_DATA);
284 outb(0, VGAREG_DAC_DATA);
287 if ((modeset_ctl & 0x02) == 0x02)
288 biosfn_perform_gray_scale_summing(0x00, 0x100);
290 // Reset Attribute Ctl flip-flop
291 inb(VGAREG_ACTL_RESET);
295 for (i = 0; i <= 0x13; i++) {
296 outb(i, VGAREG_ACTL_ADDRESS);
297 outb(GET_GLOBAL(vparam_g->actl_regs[i]), VGAREG_ACTL_WRITE_DATA);
299 outb(0x14, VGAREG_ACTL_ADDRESS);
300 outb(0x00, VGAREG_ACTL_WRITE_DATA);
303 outb(0, VGAREG_SEQU_ADDRESS);
304 outb(0x03, VGAREG_SEQU_DATA);
305 for (i = 1; i <= 4; i++) {
306 outb(i, VGAREG_SEQU_ADDRESS);
307 outb(GET_GLOBAL(vparam_g->sequ_regs[i - 1]), VGAREG_SEQU_DATA);
311 for (i = 0; i <= 8; i++) {
312 outb(i, VGAREG_GRDC_ADDRESS);
313 outb(GET_GLOBAL(vparam_g->grdc_regs[i]), VGAREG_GRDC_DATA);
316 // Set CRTC address VGA or MDA
317 u16 crtc_addr = VGAREG_VGA_CRTC_ADDRESS;
318 if (GET_GLOBAL(vmode_g->memmodel) == MTEXT)
319 crtc_addr = VGAREG_MDA_CRTC_ADDRESS;
321 // Disable CRTC write protection
322 outw(0x0011, crtc_addr);
324 for (i = 0; i <= 0x18; i++) {
326 outb(GET_GLOBAL(vparam_g->crtc_regs[i]), crtc_addr + 1);
329 // Set the misc register
330 outb(GET_GLOBAL(vparam_g->miscreg), VGAREG_WRITE_MISC_OUTPUT);
333 outb(0x20, VGAREG_ACTL_ADDRESS);
334 inb(VGAREG_ACTL_RESET);
336 if (noclearmem == 0x00) {
337 if (GET_GLOBAL(vmode_g->class) == TEXT) {
338 memset16_far(GET_GLOBAL(vmode_g->sstart), 0, 0x0720, 32*1024);
341 memset16_far(GET_GLOBAL(vmode_g->sstart), 0, 0x0000, 32*1024);
343 outb(0x02, VGAREG_SEQU_ADDRESS);
344 u8 mmask = inb(VGAREG_SEQU_DATA);
345 outb(0x0f, VGAREG_SEQU_DATA); // all planes
346 memset16_far(GET_GLOBAL(vmode_g->sstart), 0, 0x0000, 64*1024);
347 outb(mmask, VGAREG_SEQU_DATA);
352 SET_BDA(video_mode, mode);
353 SET_BDA(video_cols, twidth);
354 SET_BDA(video_pagesize, GET_GLOBAL(vparam_g->slength));
355 SET_BDA(crtc_address, crtc_addr);
356 SET_BDA(video_rows, theightm1);
357 SET_BDA(char_height, cheight);
358 SET_BDA(video_ctl, (0x60 | noclearmem));
359 SET_BDA(video_switches, 0xF9);
360 SET_BDA(modeset_ctl, GET_BDA(modeset_ctl) & 0x7f);
362 // FIXME We nearly have the good tables. to be reworked
363 SET_BDA(dcc_index, 0x08); // 8 is VGA should be ok for now
364 SET_BDA(video_savetable_ptr, (u32)video_save_pointer_table);
365 SET_BDA(video_savetable_seg, 0xc000);
368 SET_BDA(video_msr, 0x00); // Unavailable on vanilla vga, but...
369 SET_BDA(video_pal, 0x00); // Unavailable on vanilla vga, but...
372 if (GET_GLOBAL(vmode_g->class) == TEXT)
373 biosfn_set_cursor_shape(0x06, 0x07);
374 // Set cursor pos for page 0..7
375 for (i = 0; i < 8; i++)
376 biosfn_set_cursor_pos(i, 0x0000);
379 biosfn_set_active_page(0x00);
381 // Write the fonts in memory
382 if (GET_GLOBAL(vmode_g->class) == TEXT) {
383 call16_vgaint(0x1104, 0);
384 call16_vgaint(0x1103, 0);
386 // Set the ints 0x1F and 0x43
387 SET_IVT(0x1f, 0xC000, (u32)&vgafont8[128 * 8]);
391 SET_IVT(0x43, 0xC000, (u32)vgafont8);
394 SET_IVT(0x43, 0xC000, (u32)vgafont14);
397 SET_IVT(0x43, 0xC000, (u32)vgafont16);
402 // -------------------------------------------------------------------
404 vgamem_copy_pl4(u8 xstart, u8 ysrc, u8 ydest, u8 cols, u8 nbcols,
407 u16 src = ysrc * cheight * nbcols + xstart;
408 u16 dest = ydest * cheight * nbcols + xstart;
409 outw(0x0105, VGAREG_GRDC_ADDRESS);
411 for (i = 0; i < cheight; i++)
412 memcpy_far(0xa000, (void*)(dest + i * nbcols)
413 , 0xa000, (void*)(src + i * nbcols), cols);
414 outw(0x0005, VGAREG_GRDC_ADDRESS);
417 // -------------------------------------------------------------------
419 vgamem_fill_pl4(u8 xstart, u8 ystart, u8 cols, u8 nbcols, u8 cheight,
422 u16 dest = ystart * cheight * nbcols + xstart;
423 outw(0x0205, VGAREG_GRDC_ADDRESS);
425 for (i = 0; i < cheight; i++)
426 memset_far(0xa000, (void*)(dest + i * nbcols), attr, cols);
427 outw(0x0005, VGAREG_GRDC_ADDRESS);
430 // -------------------------------------------------------------------
432 vgamem_copy_cga(u8 xstart, u8 ysrc, u8 ydest, u8 cols, u8 nbcols,
435 u16 src = ((ysrc * cheight * nbcols) >> 1) + xstart;
436 u16 dest = ((ydest * cheight * nbcols) >> 1) + xstart;
438 for (i = 0; i < cheight; i++)
440 memcpy_far(0xb800, (void*)(0x2000 + dest + (i >> 1) * nbcols)
441 , 0xb800, (void*)(0x2000 + src + (i >> 1) * nbcols)
444 memcpy_far(0xb800, (void*)(dest + (i >> 1) * nbcols)
445 , 0xb800, (void*)(src + (i >> 1) * nbcols), cols);
448 // -------------------------------------------------------------------
450 vgamem_fill_cga(u8 xstart, u8 ystart, u8 cols, u8 nbcols, u8 cheight,
453 u16 dest = ((ystart * cheight * nbcols) >> 1) + xstart;
455 for (i = 0; i < cheight; i++)
457 memset_far(0xb800, (void*)(0x2000 + dest + (i >> 1) * nbcols)
460 memset_far(0xb800, (void*)(dest + (i >> 1) * nbcols), attr, cols);
463 // -------------------------------------------------------------------
465 biosfn_scroll(u8 nblines, u8 attr, u8 rul, u8 cul, u8 rlr, u8 clr, u8 page,
468 // page == 0xFF if current
475 struct vgamode_s *vmode_g = find_vga_entry(GET_BDA(video_mode));
479 // Get the dimensions
480 u16 nbrows = GET_BDA(video_rows) + 1;
481 u16 nbcols = GET_BDA(video_cols);
483 // Get the current page
485 page = GET_BDA(video_page);
491 if (nblines > nbrows)
493 u8 cols = clr - cul + 1;
495 if (GET_GLOBAL(vmode_g->class) == TEXT) {
496 // Compute the address
497 void *address = (void*)(SCREEN_MEM_START(nbcols, nbrows, page));
498 dprintf(3, "Scroll, address %p (%d %d %02x)\n"
499 , address, nbrows, nbcols, page);
501 if (nblines == 0 && rul == 0 && cul == 0 && rlr == nbrows - 1
502 && clr == nbcols - 1) {
503 memset16_far(GET_GLOBAL(vmode_g->sstart), address
504 , (u16)attr * 0x100 + ' ', nbrows * nbcols * 2);
505 } else { // if Scroll up
506 if (dir == SCROLL_UP) {
508 for (i = rul; i <= rlr; i++)
509 if ((i + nblines > rlr) || (nblines == 0))
510 memset16_far(GET_GLOBAL(vmode_g->sstart)
511 , address + (i * nbcols + cul) * 2
512 , (u16)attr * 0x100 + ' ', cols * 2);
514 memcpy16_far(GET_GLOBAL(vmode_g->sstart)
515 , address + (i * nbcols + cul) * 2
516 , GET_GLOBAL(vmode_g->sstart)
517 , (void*)(((i + nblines) * nbcols + cul) * 2)
521 for (i = rlr; i >= rul; i--) {
522 if ((i < rul + nblines) || (nblines == 0))
523 memset16_far(GET_GLOBAL(vmode_g->sstart)
524 , address + (i * nbcols + cul) * 2
525 , (u16)attr * 0x100 + ' ', cols * 2);
527 memcpy16_far(GET_GLOBAL(vmode_g->sstart)
528 , address + (i * nbcols + cul) * 2
529 , GET_GLOBAL(vmode_g->sstart)
530 , (void*)(((i - nblines) * nbcols + cul) * 2)
540 // FIXME gfx mode not complete
541 struct VideoParam_s *vparam_g = GET_GLOBAL(vmode_g->vparam);
542 u8 cheight = GET_GLOBAL(vparam_g->cheight);
543 switch (GET_GLOBAL(vmode_g->memmodel)) {
546 if (nblines == 0 && rul == 0 && cul == 0 && rlr == nbrows - 1
547 && clr == nbcols - 1) {
548 outw(0x0205, VGAREG_GRDC_ADDRESS);
549 memset_far(GET_GLOBAL(vmode_g->sstart), 0, attr,
550 nbrows * nbcols * cheight);
551 outw(0x0005, VGAREG_GRDC_ADDRESS);
552 } else { // if Scroll up
553 if (dir == SCROLL_UP) {
555 for (i = rul; i <= rlr; i++)
556 if ((i + nblines > rlr) || (nblines == 0))
557 vgamem_fill_pl4(cul, i, cols, nbcols, cheight,
560 vgamem_copy_pl4(cul, i + nblines, i, cols,
564 for (i = rlr; i >= rul; i--) {
565 if ((i < rul + nblines) || (nblines == 0))
566 vgamem_fill_pl4(cul, i, cols, nbcols, cheight,
569 vgamem_copy_pl4(cul, i, i - nblines, cols,
578 u8 bpp = GET_GLOBAL(vmode_g->pixbits);
579 if (nblines == 0 && rul == 0 && cul == 0 && rlr == nbrows - 1
580 && clr == nbcols - 1) {
581 memset_far(GET_GLOBAL(vmode_g->sstart), 0, attr,
582 nbrows * nbcols * cheight * bpp);
590 if (dir == SCROLL_UP) {
592 for (i = rul; i <= rlr; i++)
593 if ((i + nblines > rlr) || (nblines == 0))
594 vgamem_fill_cga(cul, i, cols, nbcols, cheight,
597 vgamem_copy_cga(cul, i + nblines, i, cols,
601 for (i = rlr; i >= rul; i--) {
602 if ((i < rul + nblines) || (nblines == 0))
603 vgamem_fill_cga(cul, i, cols, nbcols, cheight,
606 vgamem_copy_cga(cul, i, i - nblines, cols,
616 dprintf(1, "Scroll in graphics mode\n");
620 // -------------------------------------------------------------------
622 biosfn_read_char_attr(u8 page, u16 *car)
625 struct vgamode_s *vmode_g = find_vga_entry(GET_BDA(video_mode));
629 // Get the cursor pos for the page
631 biosfn_get_cursor_pos(page, &dummy, &cursor);
632 u8 xcurs = cursor & 0x00ff;
633 u8 ycurs = (cursor & 0xff00) >> 8;
635 // Get the dimensions
636 u16 nbrows = GET_BDA(video_rows) + 1;
637 u16 nbcols = GET_BDA(video_cols);
639 if (GET_GLOBAL(vmode_g->class) == TEXT) {
640 // Compute the address
641 u16 *address_far = (void*)(SCREEN_MEM_START(nbcols, nbrows, page)
642 + (xcurs + ycurs * nbcols) * 2);
644 *car = GET_FARVAR(GET_GLOBAL(vmode_g->sstart), *address_far);
647 dprintf(1, "Read char in graphics mode\n");
651 // -------------------------------------------------------------------
653 write_gfx_char_pl4(u8 car, u8 attr, u8 xcurs, u8 ycurs, u8 nbcols,
667 u16 addr = xcurs + ycurs * cheight * nbcols;
668 u16 src = car * cheight;
669 outw(0x0f02, VGAREG_SEQU_ADDRESS);
670 outw(0x0205, VGAREG_GRDC_ADDRESS);
672 outw(0x1803, VGAREG_GRDC_ADDRESS);
674 outw(0x0003, VGAREG_GRDC_ADDRESS);
676 for (i = 0; i < cheight; i++) {
677 u8 *dest_far = (void*)(addr + i * nbcols);
679 for (j = 0; j < 8; j++) {
681 outw((mask << 8) | 0x08, VGAREG_GRDC_ADDRESS);
682 GET_FARVAR(0xa000, *dest_far);
683 if (GET_GLOBAL(fdata_g[src + i]) & mask)
684 SET_FARVAR(0xa000, *dest_far, attr & 0x0f);
686 SET_FARVAR(0xa000, *dest_far, 0x00);
689 outw(0xff08, VGAREG_GRDC_ADDRESS);
690 outw(0x0005, VGAREG_GRDC_ADDRESS);
691 outw(0x0003, VGAREG_GRDC_ADDRESS);
694 // -------------------------------------------------------------------
696 write_gfx_char_cga(u8 car, u8 attr, u8 xcurs, u8 ycurs, u8 nbcols, u8 bpp)
698 u8 *fdata_g = vgafont8;
699 u16 addr = (xcurs * bpp) + ycurs * 320;
702 for (i = 0; i < 8; i++) {
703 u8 *dest_far = (void*)(addr + (i >> 1) * 80);
710 data = GET_FARVAR(0xb800, *dest_far);
712 for (j = 0; j < 8; j++) {
713 if (GET_GLOBAL(fdata_g[src + i]) & mask) {
715 data ^= (attr & 0x01) << (7 - j);
717 data |= (attr & 0x01) << (7 - j);
721 SET_FARVAR(0xb800, *dest_far, data);
726 data = GET_FARVAR(0xb800, *dest_far);
728 for (j = 0; j < 4; j++) {
729 if (GET_GLOBAL(fdata_g[src + i]) & mask) {
731 data ^= (attr & 0x03) << ((3 - j) * 2);
733 data |= (attr & 0x03) << ((3 - j) * 2);
737 SET_FARVAR(0xb800, *dest_far, data);
744 // -------------------------------------------------------------------
746 write_gfx_char_lin(u8 car, u8 attr, u8 xcurs, u8 ycurs, u8 nbcols)
748 u8 *fdata_g = vgafont8;
749 u16 addr = xcurs * 8 + ycurs * nbcols * 64;
752 for (i = 0; i < 8; i++) {
753 u8 *dest_far = (void*)(addr + i * nbcols * 8);
756 for (j = 0; j < 8; j++) {
758 if (GET_GLOBAL(fdata_g[src + i]) & mask)
760 SET_FARVAR(0xa000, dest_far[j], data);
766 // -------------------------------------------------------------------
768 biosfn_write_char_attr(u8 car, u8 page, u8 attr, u16 count)
771 struct vgamode_s *vmode_g = find_vga_entry(GET_BDA(video_mode));
775 // Get the cursor pos for the page
777 biosfn_get_cursor_pos(page, &dummy, &cursor);
778 u8 xcurs = cursor & 0x00ff;
779 u8 ycurs = (cursor & 0xff00) >> 8;
781 // Get the dimensions
782 u16 nbrows = GET_BDA(video_rows) + 1;
783 u16 nbcols = GET_BDA(video_cols);
785 if (GET_GLOBAL(vmode_g->class) == TEXT) {
786 // Compute the address
787 void *address = (void*)(SCREEN_MEM_START(nbcols, nbrows, page)
788 + (xcurs + ycurs * nbcols) * 2);
790 dummy = ((u16)attr << 8) + car;
791 memset16_far(GET_GLOBAL(vmode_g->sstart), address, dummy, count * 2);
795 // FIXME gfx mode not complete
796 struct VideoParam_s *vparam_g = GET_GLOBAL(vmode_g->vparam);
797 u8 cheight = GET_GLOBAL(vparam_g->cheight);
798 u8 bpp = GET_GLOBAL(vmode_g->pixbits);
799 while ((count-- > 0) && (xcurs < nbcols)) {
800 switch (GET_GLOBAL(vmode_g->memmodel)) {
803 write_gfx_char_pl4(car, attr, xcurs, ycurs, nbcols,
807 write_gfx_char_cga(car, attr, xcurs, ycurs, nbcols, bpp);
810 write_gfx_char_lin(car, attr, xcurs, ycurs, nbcols);
817 // -------------------------------------------------------------------
819 biosfn_write_char_only(u8 car, u8 page, u8 attr, u16 count)
822 struct vgamode_s *vmode_g = find_vga_entry(GET_BDA(video_mode));
826 // Get the cursor pos for the page
828 biosfn_get_cursor_pos(page, &dummy, &cursor);
829 u8 xcurs = cursor & 0x00ff;
830 u8 ycurs = (cursor & 0xff00) >> 8;
832 // Get the dimensions
833 u16 nbrows = GET_BDA(video_rows) + 1;
834 u16 nbcols = GET_BDA(video_cols);
836 if (GET_GLOBAL(vmode_g->class) == TEXT) {
837 // Compute the address
838 u8 *address_far = (void*)(SCREEN_MEM_START(nbcols, nbrows, page)
839 + (xcurs + ycurs * nbcols) * 2);
840 while (count-- > 0) {
841 SET_FARVAR(GET_GLOBAL(vmode_g->sstart), *address_far, car);
847 // FIXME gfx mode not complete
848 struct VideoParam_s *vparam_g = GET_GLOBAL(vmode_g->vparam);
849 u8 cheight = GET_GLOBAL(vparam_g->cheight);
850 u8 bpp = GET_GLOBAL(vmode_g->pixbits);
851 while ((count-- > 0) && (xcurs < nbcols)) {
852 switch (GET_GLOBAL(vmode_g->memmodel)) {
855 write_gfx_char_pl4(car, attr, xcurs, ycurs, nbcols,
859 write_gfx_char_cga(car, attr, xcurs, ycurs, nbcols, bpp);
862 write_gfx_char_lin(car, attr, xcurs, ycurs, nbcols);
869 // -------------------------------------------------------------------
871 biosfn_set_border_color(struct bregs *regs)
873 inb(VGAREG_ACTL_RESET);
874 outb(0x00, VGAREG_ACTL_ADDRESS);
875 u8 al = regs->bl & 0x0f;
878 outb(al, VGAREG_ACTL_WRITE_DATA);
879 u8 bl = regs->bl & 0x10;
882 for (i = 1; i < 4; i++) {
883 outb(i, VGAREG_ACTL_ADDRESS);
885 al = inb(VGAREG_ACTL_READ_DATA);
888 outb(al, VGAREG_ACTL_WRITE_DATA);
890 outb(0x20, VGAREG_ACTL_ADDRESS);
894 biosfn_set_palette(struct bregs *regs)
896 inb(VGAREG_ACTL_RESET);
897 u8 bl = regs->bl & 0x01;
899 for (i = 1; i < 4; i++) {
900 outb(i, VGAREG_ACTL_ADDRESS);
902 u8 al = inb(VGAREG_ACTL_READ_DATA);
905 outb(al, VGAREG_ACTL_WRITE_DATA);
907 outb(0x20, VGAREG_ACTL_ADDRESS);
910 // -------------------------------------------------------------------
912 biosfn_write_pixel(u8 BH, u8 AL, u16 CX, u16 DX)
915 struct vgamode_s *vmode_g = find_vga_entry(GET_BDA(video_mode));
918 if (GET_GLOBAL(vmode_g->class) == TEXT)
921 u8 *addr_far, mask, attr, data;
922 switch (GET_GLOBAL(vmode_g->memmodel)) {
925 addr_far = (void*)(CX / 8 + DX * GET_BDA(video_cols));
926 mask = 0x80 >> (CX & 0x07);
927 outw((mask << 8) | 0x08, VGAREG_GRDC_ADDRESS);
928 outw(0x0205, VGAREG_GRDC_ADDRESS);
929 data = GET_FARVAR(0xa000, *addr_far);
931 outw(0x1803, VGAREG_GRDC_ADDRESS);
932 SET_FARVAR(0xa000, *addr_far, AL);
933 outw(0xff08, VGAREG_GRDC_ADDRESS);
934 outw(0x0005, VGAREG_GRDC_ADDRESS);
935 outw(0x0003, VGAREG_GRDC_ADDRESS);
938 if (GET_GLOBAL(vmode_g->pixbits) == 2)
939 addr_far = (void*)((CX >> 2) + (DX >> 1) * 80);
941 addr_far = (void*)((CX >> 3) + (DX >> 1) * 80);
944 data = GET_FARVAR(0xb800, *addr_far);
945 if (GET_GLOBAL(vmode_g->pixbits) == 2) {
946 attr = (AL & 0x03) << ((3 - (CX & 0x03)) * 2);
947 mask = 0x03 << ((3 - (CX & 0x03)) * 2);
949 attr = (AL & 0x01) << (7 - (CX & 0x07));
950 mask = 0x01 << (7 - (CX & 0x07));
958 SET_FARVAR(0xb800, *addr_far, data);
961 addr_far = (void*)(CX + DX * (GET_BDA(video_cols) * 8));
962 SET_FARVAR(0xa000, *addr_far, AL);
967 // -------------------------------------------------------------------
969 biosfn_read_pixel(u8 BH, u16 CX, u16 DX, u16 *AX)
972 struct vgamode_s *vmode_g = find_vga_entry(GET_BDA(video_mode));
975 if (GET_GLOBAL(vmode_g->class) == TEXT)
978 u8 *addr_far, mask, attr=0, data, i;
979 switch (GET_GLOBAL(vmode_g->memmodel)) {
982 addr_far = (void*)(CX / 8 + DX * GET_BDA(video_cols));
983 mask = 0x80 >> (CX & 0x07);
985 for (i = 0; i < 4; i++) {
986 outw((i << 8) | 0x04, VGAREG_GRDC_ADDRESS);
987 data = GET_FARVAR(0xa000, *addr_far) & mask;
993 addr_far = (void*)((CX >> 2) + (DX >> 1) * 80);
996 data = GET_FARVAR(0xb800, *addr_far);
997 if (GET_GLOBAL(vmode_g->pixbits) == 2)
998 attr = (data >> ((3 - (CX & 0x03)) * 2)) & 0x03;
1000 attr = (data >> (7 - (CX & 0x07))) & 0x01;
1003 addr_far = (void*)(CX + DX * (GET_BDA(video_cols) * 8));
1004 attr = GET_FARVAR(0xa000, *addr_far);
1007 *AX = (*AX & 0xff00) | attr;
1010 // -------------------------------------------------------------------
1012 biosfn_write_teletype(u8 car, u8 page, u8 attr, u8 flag)
1013 { // flag = WITH_ATTR / NO_ATTR
1014 // special case if page is 0xff, use current page
1016 page = GET_BDA(video_page);
1019 struct vgamode_s *vmode_g = find_vga_entry(GET_BDA(video_mode));
1023 // Get the cursor pos for the page
1025 biosfn_get_cursor_pos(page, &dummy, &cursor);
1026 u8 xcurs = cursor & 0x00ff;
1027 u8 ycurs = (cursor & 0xff00) >> 8;
1029 // Get the dimensions
1030 u16 nbrows = GET_BDA(video_rows) + 1;
1031 u16 nbcols = GET_BDA(video_cols);
1053 biosfn_write_teletype(' ', page, attr, flag);
1054 biosfn_get_cursor_pos(page, &dummy, &cursor);
1055 xcurs = cursor & 0x00ff;
1056 ycurs = (cursor & 0xff00) >> 8;
1057 } while (xcurs % 8 == 0);
1062 if (GET_GLOBAL(vmode_g->class) == TEXT) {
1063 // Compute the address
1064 u8 *address_far = (void*)(SCREEN_MEM_START(nbcols, nbrows, page)
1065 + (xcurs + ycurs * nbcols) * 2);
1067 SET_FARVAR(GET_GLOBAL(vmode_g->sstart), address_far[0], car);
1068 if (flag == WITH_ATTR)
1069 SET_FARVAR(GET_GLOBAL(vmode_g->sstart), address_far[1], attr);
1071 // FIXME gfx mode not complete
1072 struct VideoParam_s *vparam_g = GET_GLOBAL(vmode_g->vparam);
1073 u8 cheight = GET_GLOBAL(vparam_g->cheight);
1074 u8 bpp = GET_GLOBAL(vmode_g->pixbits);
1075 switch (GET_GLOBAL(vmode_g->memmodel)) {
1078 write_gfx_char_pl4(car, attr, xcurs, ycurs, nbcols, cheight);
1081 write_gfx_char_cga(car, attr, xcurs, ycurs, nbcols, bpp);
1084 write_gfx_char_lin(car, attr, xcurs, ycurs, nbcols);
1091 // Do we need to wrap ?
1092 if (xcurs == nbcols) {
1096 // Do we need to scroll ?
1097 if (ycurs == nbrows) {
1098 if (GET_GLOBAL(vmode_g->class) == TEXT)
1099 biosfn_scroll(0x01, 0x07, 0, 0, nbrows - 1, nbcols - 1, page,
1102 biosfn_scroll(0x01, 0x00, 0, 0, nbrows - 1, nbcols - 1, page,
1106 // Set the cursor for the page
1110 biosfn_set_cursor_pos(page, cursor);
1113 // -------------------------------------------------------------------
1115 biosfn_get_video_mode(struct bregs *regs)
1117 regs->bh = GET_BDA(video_page);
1118 regs->al = GET_BDA(video_mode) | (GET_BDA(video_ctl) & 0x80);
1119 regs->ah = GET_BDA(video_cols);
1122 // -------------------------------------------------------------------
1124 biosfn_set_overscan_border_color(struct bregs *regs)
1126 inb(VGAREG_ACTL_RESET);
1127 outb(0x11, VGAREG_ACTL_ADDRESS);
1128 outb(regs->bh, VGAREG_ACTL_WRITE_DATA);
1129 outb(0x20, VGAREG_ACTL_ADDRESS);
1132 // -------------------------------------------------------------------
1134 biosfn_set_all_palette_reg(struct bregs *regs)
1136 inb(VGAREG_ACTL_RESET);
1138 u8 *data_far = (u8*)(regs->dx + 0);
1140 for (i = 0; i < 0x10; i++) {
1141 outb(i, VGAREG_ACTL_ADDRESS);
1142 u8 val = GET_FARVAR(regs->es, *data_far);
1143 outb(val, VGAREG_ACTL_WRITE_DATA);
1146 outb(0x11, VGAREG_ACTL_ADDRESS);
1147 outb(GET_FARVAR(regs->es, *data_far), VGAREG_ACTL_WRITE_DATA);
1148 outb(0x20, VGAREG_ACTL_ADDRESS);
1151 // -------------------------------------------------------------------
1153 biosfn_toggle_intensity(struct bregs *regs)
1155 inb(VGAREG_ACTL_RESET);
1156 outb(0x10, VGAREG_ACTL_ADDRESS);
1157 u8 val = (inb(VGAREG_ACTL_READ_DATA) & 0x7f) | ((regs->bl & 0x01) << 3);
1158 outb(val, VGAREG_ACTL_WRITE_DATA);
1159 outb(0x20, VGAREG_ACTL_ADDRESS);
1162 // -------------------------------------------------------------------
1164 biosfn_set_single_palette_reg(u8 reg, u8 val)
1166 inb(VGAREG_ACTL_RESET);
1167 outb(reg, VGAREG_ACTL_ADDRESS);
1168 outb(val, VGAREG_ACTL_WRITE_DATA);
1169 outb(0x20, VGAREG_ACTL_ADDRESS);
1172 // -------------------------------------------------------------------
1174 biosfn_get_single_palette_reg(u8 reg)
1176 inb(VGAREG_ACTL_RESET);
1177 outb(reg, VGAREG_ACTL_ADDRESS);
1178 u8 v = inb(VGAREG_ACTL_READ_DATA);
1179 inb(VGAREG_ACTL_RESET);
1180 outb(0x20, VGAREG_ACTL_ADDRESS);
1184 // -------------------------------------------------------------------
1186 biosfn_read_overscan_border_color(struct bregs *regs)
1188 inb(VGAREG_ACTL_RESET);
1189 outb(0x11, VGAREG_ACTL_ADDRESS);
1190 regs->bh = inb(VGAREG_ACTL_READ_DATA);
1191 inb(VGAREG_ACTL_RESET);
1192 outb(0x20, VGAREG_ACTL_ADDRESS);
1195 // -------------------------------------------------------------------
1197 biosfn_get_all_palette_reg(struct bregs *regs)
1199 u8 *data_far = (u8*)(regs->dx + 0);
1201 for (i = 0; i < 0x10; i++) {
1202 inb(VGAREG_ACTL_RESET);
1203 outb(i, VGAREG_ACTL_ADDRESS);
1204 SET_FARVAR(regs->es, *data_far, inb(VGAREG_ACTL_READ_DATA));
1207 inb(VGAREG_ACTL_RESET);
1208 outb(0x11, VGAREG_ACTL_ADDRESS);
1209 SET_FARVAR(regs->es, *data_far, inb(VGAREG_ACTL_READ_DATA));
1210 inb(VGAREG_ACTL_RESET);
1211 outb(0x20, VGAREG_ACTL_ADDRESS);
1214 // -------------------------------------------------------------------
1216 biosfn_set_single_dac_reg(struct bregs *regs)
1218 outb(regs->bl, VGAREG_DAC_WRITE_ADDRESS);
1219 outb(regs->dh, VGAREG_DAC_DATA);
1220 outb(regs->ch, VGAREG_DAC_DATA);
1221 outb(regs->cl, VGAREG_DAC_DATA);
1224 // -------------------------------------------------------------------
1226 biosfn_set_all_dac_reg(struct bregs *regs)
1228 outb(regs->bl, VGAREG_DAC_WRITE_ADDRESS);
1229 u8 *data_far = (u8*)(regs->dx + 0);
1230 int count = regs->cx;
1232 outb(GET_FARVAR(regs->es, *data_far), VGAREG_DAC_DATA);
1234 outb(GET_FARVAR(regs->es, *data_far), VGAREG_DAC_DATA);
1236 outb(GET_FARVAR(regs->es, *data_far), VGAREG_DAC_DATA);
1242 // -------------------------------------------------------------------
1244 biosfn_select_video_dac_color_page(struct bregs *regs)
1246 inb(VGAREG_ACTL_RESET);
1247 outb(0x10, VGAREG_ACTL_ADDRESS);
1248 u8 val = inb(VGAREG_ACTL_READ_DATA);
1249 if (!(regs->bl & 0x01)) {
1250 val = (val & 0x7f) | (regs->bh << 7);
1251 outb(val, VGAREG_ACTL_WRITE_DATA);
1252 outb(0x20, VGAREG_ACTL_ADDRESS);
1255 inb(VGAREG_ACTL_RESET);
1256 outb(0x14, VGAREG_ACTL_ADDRESS);
1261 outb(bh, VGAREG_ACTL_WRITE_DATA);
1262 outb(0x20, VGAREG_ACTL_ADDRESS);
1265 // -------------------------------------------------------------------
1267 biosfn_read_single_dac_reg(struct bregs *regs)
1269 outb(regs->bl, VGAREG_DAC_READ_ADDRESS);
1270 regs->dh = inb(VGAREG_DAC_DATA);
1271 regs->ch = inb(VGAREG_DAC_DATA);
1272 regs->cl = inb(VGAREG_DAC_DATA);
1275 // -------------------------------------------------------------------
1277 biosfn_read_all_dac_reg(struct bregs *regs)
1279 outb(regs->bl, VGAREG_DAC_READ_ADDRESS);
1280 u8 *data_far = (u8*)(regs->dx + 0);
1281 int count = regs->cx;
1283 SET_FARVAR(regs->es, *data_far, inb(VGAREG_DAC_DATA));
1285 SET_FARVAR(regs->es, *data_far, inb(VGAREG_DAC_DATA));
1287 SET_FARVAR(regs->es, *data_far, inb(VGAREG_DAC_DATA));
1293 // -------------------------------------------------------------------
1295 biosfn_set_pel_mask(struct bregs *regs)
1297 outb(regs->bl, VGAREG_PEL_MASK);
1300 // -------------------------------------------------------------------
1302 biosfn_read_pel_mask(struct bregs *regs)
1304 regs->bl = inb(VGAREG_PEL_MASK);
1307 // -------------------------------------------------------------------
1309 biosfn_read_video_dac_state(struct bregs *regs)
1311 inb(VGAREG_ACTL_RESET);
1312 outb(0x10, VGAREG_ACTL_ADDRESS);
1313 u8 val1 = inb(VGAREG_ACTL_READ_DATA) >> 7;
1315 inb(VGAREG_ACTL_RESET);
1316 outb(0x14, VGAREG_ACTL_ADDRESS);
1317 u8 val2 = inb(VGAREG_ACTL_READ_DATA) & 0x0f;
1321 inb(VGAREG_ACTL_RESET);
1322 outb(0x20, VGAREG_ACTL_ADDRESS);
1328 // -------------------------------------------------------------------
1332 outw(0x0100, VGAREG_SEQU_ADDRESS);
1333 outw(0x0402, VGAREG_SEQU_ADDRESS);
1334 outw(0x0704, VGAREG_SEQU_ADDRESS);
1335 outw(0x0300, VGAREG_SEQU_ADDRESS);
1336 outw(0x0204, VGAREG_GRDC_ADDRESS);
1337 outw(0x0005, VGAREG_GRDC_ADDRESS);
1338 outw(0x0406, VGAREG_GRDC_ADDRESS);
1342 release_font_access()
1344 outw(0x0100, VGAREG_SEQU_ADDRESS);
1345 outw(0x0302, VGAREG_SEQU_ADDRESS);
1346 outw(0x0304, VGAREG_SEQU_ADDRESS);
1347 outw(0x0300, VGAREG_SEQU_ADDRESS);
1348 u16 v = inw(VGAREG_READ_MISC_OUTPUT);
1349 v = ((v & 0x01) << 10) | 0x0a06;
1350 outw(v, VGAREG_GRDC_ADDRESS);
1351 outw(0x0004, VGAREG_GRDC_ADDRESS);
1352 outw(0x1005, VGAREG_GRDC_ADDRESS);
1356 set_scan_lines(u8 lines)
1358 u16 crtc_addr = GET_BDA(crtc_address);
1359 outb(0x09, crtc_addr);
1360 u8 crtc_r9 = inb(crtc_addr + 1);
1361 crtc_r9 = (crtc_r9 & 0xe0) | (lines - 1);
1362 outb(crtc_r9, crtc_addr + 1);
1364 biosfn_set_cursor_shape(0x06, 0x07);
1366 biosfn_set_cursor_shape(lines - 4, lines - 3);
1367 SET_BDA(char_height, lines);
1368 outb(0x12, crtc_addr);
1369 u16 vde = inb(crtc_addr + 1);
1370 outb(0x07, crtc_addr);
1371 u8 ovl = inb(crtc_addr + 1);
1372 vde += (((ovl & 0x02) << 7) + ((ovl & 0x40) << 3) + 1);
1373 u8 rows = vde / lines;
1374 SET_BDA(video_rows, rows - 1);
1375 u16 cols = GET_BDA(video_cols);
1376 SET_BDA(video_pagesize, rows * cols * 2);
1380 biosfn_load_text_user_pat(u8 AL, u16 ES, u16 BP, u16 CX, u16 DX, u8 BL,
1384 u16 blockaddr = ((BL & 0x03) << 14) + ((BL & 0x04) << 11);
1386 for (i = 0; i < CX; i++) {
1387 void *src = (void*)(BP + i * BH);
1388 void *dest = (void*)(blockaddr + (DX + i) * 32);
1389 memcpy_far(0xA000, dest, ES, src, BH);
1391 release_font_access();
1397 biosfn_load_text_8_14_pat(u8 AL, u8 BL)
1400 u16 blockaddr = ((BL & 0x03) << 14) + ((BL & 0x04) << 11);
1402 for (i = 0; i < 0x100; i++) {
1404 void *dest = (void*)(blockaddr + i * 32);
1405 memcpy_far(0xA000, dest, 0xC000, &vgafont14[src], 14);
1407 release_font_access();
1413 biosfn_load_text_8_8_pat(u8 AL, u8 BL)
1416 u16 blockaddr = ((BL & 0x03) << 14) + ((BL & 0x04) << 11);
1418 for (i = 0; i < 0x100; i++) {
1420 void *dest = (void*)(blockaddr + i * 32);
1421 memcpy_far(0xA000, dest, 0xC000, &vgafont8[src], 8);
1423 release_font_access();
1428 // -------------------------------------------------------------------
1430 biosfn_set_text_block_specifier(struct bregs *regs)
1432 outw((regs->bl << 8) | 0x03, VGAREG_SEQU_ADDRESS);
1435 // -------------------------------------------------------------------
1437 biosfn_load_text_8_16_pat(u8 AL, u8 BL)
1440 u16 blockaddr = ((BL & 0x03) << 14) + ((BL & 0x04) << 11);
1442 for (i = 0; i < 0x100; i++) {
1444 void *dest = (void*)(blockaddr + i * 32);
1445 memcpy_far(0xA000, dest, 0xC000, &vgafont16[src], 16);
1447 release_font_access();
1452 // -------------------------------------------------------------------
1454 biosfn_get_font_info(u8 BH, u16 *ES, u16 *BP, u16 *CX, u16 *DX)
1458 u32 segoff = GET_IVT(0x1f).segoff;
1464 u32 segoff = GET_IVT(0x43).segoff;
1471 *BP = (u32)vgafont14;
1475 *BP = (u32)vgafont8;
1479 *BP = (u32)vgafont8 + 128 * 8;
1483 *BP = (u32)vgafont14alt;
1487 *BP = (u32)vgafont16;
1491 *BP = (u32)vgafont16alt;
1494 dprintf(1, "Get font info BH(%02x) was discarded\n", BH);
1497 // Set byte/char of on screen font
1498 *CX = GET_BDA(char_height) & 0xff;
1500 // Set Highest char row
1501 *DX = GET_BDA(video_rows);
1504 // -------------------------------------------------------------------
1506 biosfn_get_ega_info(struct bregs *regs)
1508 regs->cx = GET_BDA(video_switches) & 0x0f;
1509 regs->ax = GET_BDA(crtc_address);
1510 if (regs->ax == VGAREG_MDA_CRTC_ADDRESS)
1516 // -------------------------------------------------------------------
1518 biosfn_select_vert_res(struct bregs *regs)
1520 u8 mctl = GET_BDA(modeset_ctl);
1521 u8 vswt = GET_BDA(video_switches);
1526 mctl = (mctl & ~0x10) | 0x80;
1527 vswt = (vswt & ~0x0f) | 0x08;
1532 vswt = (vswt & ~0x0f) | 0x09;
1536 mctl = (mctl & ~0x80) | 0x10;
1537 vswt = (vswt & ~0x0f) | 0x09;
1540 dprintf(1, "Select vert res (%02x) was discarded\n", regs->al);
1543 SET_BDA(modeset_ctl, mctl);
1544 SET_BDA(video_switches, vswt);
1549 biosfn_enable_default_palette_loading(struct bregs *regs)
1551 u8 v = (regs->al & 0x01) << 3;
1552 u8 mctl = GET_BDA(video_ctl) & ~0x08;
1553 SET_BDA(video_ctl, mctl | v);
1558 biosfn_enable_video_addressing(struct bregs *regs)
1560 u8 v = ((regs->al << 1) & 0x02) ^ 0x02;
1561 u8 v2 = inb(VGAREG_READ_MISC_OUTPUT) & ~0x02;
1562 outb(v | v2, VGAREG_WRITE_MISC_OUTPUT);
1568 biosfn_enable_grayscale_summing(struct bregs *regs)
1570 u8 v = ((regs->al << 1) & 0x02) ^ 0x02;
1571 u8 v2 = GET_BDA(modeset_ctl) & ~0x02;
1572 SET_BDA(modeset_ctl, v | v2);
1577 biosfn_enable_cursor_emulation(struct bregs *regs)
1579 u8 v = (regs->al & 0x01) ^ 0x01;
1580 u8 v2 = GET_BDA(modeset_ctl) & ~0x01;
1581 SET_BDA(modeset_ctl, v | v2);
1585 // -------------------------------------------------------------------
1587 biosfn_write_string(u8 flag, u8 page, u8 attr, u16 count, u8 row, u8 col,
1588 u16 seg, u8 *offset_far)
1590 // Read curs info for the page
1592 biosfn_get_cursor_pos(page, &dummy, &oldcurs);
1594 // if row=0xff special case : use current cursor position
1596 col = oldcurs & 0x00ff;
1597 row = (oldcurs & 0xff00) >> 8;
1603 biosfn_set_cursor_pos(page, newcurs);
1605 while (count-- != 0) {
1606 u8 car = GET_FARVAR(seg, *offset_far);
1608 if ((flag & 0x02) != 0) {
1609 attr = GET_FARVAR(seg, *offset_far);
1613 biosfn_write_teletype(car, page, attr, WITH_ATTR);
1616 // Set back curs pos
1617 if ((flag & 0x01) == 0)
1618 biosfn_set_cursor_pos(page, oldcurs);
1621 // -------------------------------------------------------------------
1623 biosfn_read_display_code(struct bregs *regs)
1625 regs->bx = GET_BDA(dcc_index);
1630 biosfn_set_display_code(struct bregs *regs)
1632 SET_BDA(dcc_index, regs->bl);
1633 dprintf(1, "Alternate Display code (%02x) was discarded\n", regs->bh);
1637 // -------------------------------------------------------------------
1639 biosfn_read_state_info(u16 BX, u16 ES, u16 DI)
1641 // Address of static functionality table
1642 SET_FARVAR(ES, *(u16*)(DI + 0x00), (u32)static_functionality);
1643 SET_FARVAR(ES, *(u16*)(DI + 0x02), 0xC000);
1645 // Hard coded copy from BIOS area. Should it be cleaner ?
1646 memcpy_far(ES, (void*)(DI + 0x04), SEG_BDA, (void*)0x49, 30);
1647 memcpy_far(ES, (void*)(DI + 0x22), SEG_BDA, (void*)0x84, 3);
1649 SET_FARVAR(ES, *(u8*)(DI + 0x25), GET_BDA(dcc_index));
1650 SET_FARVAR(ES, *(u8*)(DI + 0x26), 0);
1651 SET_FARVAR(ES, *(u8*)(DI + 0x27), 16);
1652 SET_FARVAR(ES, *(u8*)(DI + 0x28), 0);
1653 SET_FARVAR(ES, *(u8*)(DI + 0x29), 8);
1654 SET_FARVAR(ES, *(u8*)(DI + 0x2a), 2);
1655 SET_FARVAR(ES, *(u8*)(DI + 0x2b), 0);
1656 SET_FARVAR(ES, *(u8*)(DI + 0x2c), 0);
1657 SET_FARVAR(ES, *(u8*)(DI + 0x31), 3);
1658 SET_FARVAR(ES, *(u8*)(DI + 0x32), 0);
1660 memset_far(ES, (void*)(DI + 0x33), 0, 13);
1663 // -------------------------------------------------------------------
1664 // -------------------------------------------------------------------
1666 biosfn_read_video_state_size(u16 CX)
1672 size += (5 + 8 + 5) * 2 + 6;
1674 size += 3 + 256 * 3 + 1;
1679 biosfn_save_video_state(u16 CX, u16 ES, u16 BX)
1681 u16 crtc_addr = GET_BDA(crtc_address);
1683 SET_FARVAR(ES, *(u8*)(BX+0), inb(VGAREG_SEQU_ADDRESS));
1685 SET_FARVAR(ES, *(u8*)(BX+0), inb(crtc_addr));
1687 SET_FARVAR(ES, *(u8*)(BX+0), inb(VGAREG_GRDC_ADDRESS));
1689 inb(VGAREG_ACTL_RESET);
1690 u16 ar_index = inb(VGAREG_ACTL_ADDRESS);
1691 SET_FARVAR(ES, *(u8*)(BX+0), ar_index);
1693 SET_FARVAR(ES, *(u8*)(BX+0), inb(VGAREG_READ_FEATURE_CTL));
1697 for (i = 1; i <= 4; i++) {
1698 outb(i, VGAREG_SEQU_ADDRESS);
1699 SET_FARVAR(ES, *(u8*)(BX+0), inb(VGAREG_SEQU_DATA));
1702 outb(0, VGAREG_SEQU_ADDRESS);
1703 SET_FARVAR(ES, *(u8*)(BX+0), inb(VGAREG_SEQU_DATA));
1706 for (i = 0; i <= 0x18; i++) {
1708 SET_FARVAR(ES, *(u8*)(BX+0), inb(crtc_addr + 1));
1712 for (i = 0; i <= 0x13; i++) {
1713 inb(VGAREG_ACTL_RESET);
1714 outb(i | (ar_index & 0x20), VGAREG_ACTL_ADDRESS);
1715 SET_FARVAR(ES, *(u8*)(BX+0), inb(VGAREG_ACTL_READ_DATA));
1718 inb(VGAREG_ACTL_RESET);
1720 for (i = 0; i <= 8; i++) {
1721 outb(i, VGAREG_GRDC_ADDRESS);
1722 SET_FARVAR(ES, *(u8*)(BX+0), inb(VGAREG_GRDC_DATA));
1726 SET_FARVAR(ES, *(u16*)(BX+0), crtc_addr);
1729 /* XXX: read plane latches */
1730 SET_FARVAR(ES, *(u8*)(BX+0), 0);
1732 SET_FARVAR(ES, *(u8*)(BX+0), 0);
1734 SET_FARVAR(ES, *(u8*)(BX+0), 0);
1736 SET_FARVAR(ES, *(u8*)(BX+0), 0);
1740 SET_FARVAR(ES, *(u8*)(BX+0), GET_BDA(video_mode));
1742 SET_FARVAR(ES, *(u16*)(BX+0), GET_BDA(video_cols));
1744 SET_FARVAR(ES, *(u16*)(BX+0), GET_BDA(video_pagesize));
1746 SET_FARVAR(ES, *(u16*)(BX+0), GET_BDA(crtc_address));
1748 SET_FARVAR(ES, *(u8*)(BX+0), GET_BDA(video_rows));
1750 SET_FARVAR(ES, *(u16*)(BX+0), GET_BDA(char_height));
1752 SET_FARVAR(ES, *(u8*)(BX+0), GET_BDA(video_ctl));
1754 SET_FARVAR(ES, *(u8*)(BX+0), GET_BDA(video_switches));
1756 SET_FARVAR(ES, *(u8*)(BX+0), GET_BDA(modeset_ctl));
1758 SET_FARVAR(ES, *(u16*)(BX+0), GET_BDA(cursor_type));
1761 for (i = 0; i < 8; i++) {
1762 SET_FARVAR(ES, *(u16*)(BX+0), GET_BDA(cursor_pos[i]));
1765 SET_FARVAR(ES, *(u16*)(BX+0), GET_BDA(video_pagestart));
1767 SET_FARVAR(ES, *(u8*)(BX+0), GET_BDA(video_page));
1770 SET_FARVAR(ES, *(u16*)(BX+0), GET_FARVAR(0, *(u16*)(0x1f * 4)));
1772 SET_FARVAR(ES, *(u16*)(BX+0), GET_FARVAR(0, *(u16*)(0x1f * 4 + 2)));
1774 SET_FARVAR(ES, *(u16*)(BX+0), GET_FARVAR(0, *(u16*)(0x43 * 4)));
1776 SET_FARVAR(ES, *(u16*)(BX+0), GET_FARVAR(0, *(u16*)(0x43 * 4 + 2)));
1780 /* XXX: check this */
1781 SET_FARVAR(ES, *(u8*)(BX+0), inb(VGAREG_DAC_STATE));
1782 BX++; /* read/write mode dac */
1783 SET_FARVAR(ES, *(u8*)(BX+0), inb(VGAREG_DAC_WRITE_ADDRESS));
1784 BX++; /* pix address */
1785 SET_FARVAR(ES, *(u8*)(BX+0), inb(VGAREG_PEL_MASK));
1787 // Set the whole dac always, from 0
1788 outb(0x00, VGAREG_DAC_WRITE_ADDRESS);
1790 for (i = 0; i < 256 * 3; i++) {
1791 SET_FARVAR(ES, *(u8*)(BX+0), inb(VGAREG_DAC_DATA));
1794 SET_FARVAR(ES, *(u8*)(BX+0), 0);
1795 BX++; /* color select register */
1801 biosfn_restore_video_state(u16 CX, u16 ES, u16 BX)
1804 // Reset Attribute Ctl flip-flop
1805 inb(VGAREG_ACTL_RESET);
1807 u16 crtc_addr = GET_FARVAR(ES, *(u16*)(BX + 0x40));
1812 for (i = 1; i <= 4; i++) {
1813 outb(i, VGAREG_SEQU_ADDRESS);
1814 outb(GET_FARVAR(ES, *(u8*)(BX+0)), VGAREG_SEQU_DATA);
1817 outb(0, VGAREG_SEQU_ADDRESS);
1818 outb(GET_FARVAR(ES, *(u8*)(BX+0)), VGAREG_SEQU_DATA);
1821 // Disable CRTC write protection
1822 outw(0x0011, crtc_addr);
1824 for (i = 0; i <= 0x18; i++) {
1827 outb(GET_FARVAR(ES, *(u8*)(BX+0)), crtc_addr + 1);
1831 // select crtc base address
1832 u16 v = inb(VGAREG_READ_MISC_OUTPUT) & ~0x01;
1833 if (crtc_addr == VGAREG_VGA_CRTC_ADDRESS)
1835 outb(v, VGAREG_WRITE_MISC_OUTPUT);
1837 // enable write protection if needed
1838 outb(0x11, crtc_addr);
1839 outb(GET_FARVAR(ES, *(u8*)(BX - 0x18 + 0x11)), crtc_addr + 1);
1841 // Set Attribute Ctl
1842 u16 ar_index = GET_FARVAR(ES, *(u8*)(addr1 + 0x03));
1843 inb(VGAREG_ACTL_RESET);
1844 for (i = 0; i <= 0x13; i++) {
1845 outb(i | (ar_index & 0x20), VGAREG_ACTL_ADDRESS);
1846 outb(GET_FARVAR(ES, *(u8*)(BX+0)), VGAREG_ACTL_WRITE_DATA);
1849 outb(ar_index, VGAREG_ACTL_ADDRESS);
1850 inb(VGAREG_ACTL_RESET);
1852 for (i = 0; i <= 8; i++) {
1853 outb(i, VGAREG_GRDC_ADDRESS);
1854 outb(GET_FARVAR(ES, *(u8*)(BX+0)), VGAREG_GRDC_DATA);
1857 BX += 2; /* crtc_addr */
1858 BX += 4; /* plane latches */
1860 outb(GET_FARVAR(ES, *(u8*)(addr1+0)), VGAREG_SEQU_ADDRESS);
1862 outb(GET_FARVAR(ES, *(u8*)(addr1+0)), crtc_addr);
1864 outb(GET_FARVAR(ES, *(u8*)(addr1+0)), VGAREG_GRDC_ADDRESS);
1867 outb(GET_FARVAR(ES, *(u8*)(addr1+0)), crtc_addr - 0x4 + 0xa);
1871 SET_BDA(video_mode, GET_FARVAR(ES, *(u8*)(BX+0)));
1873 SET_BDA(video_cols, GET_FARVAR(ES, *(u16*)(BX+0)));
1875 SET_BDA(video_pagesize, GET_FARVAR(ES, *(u16*)(BX+0)));
1877 SET_BDA(crtc_address, GET_FARVAR(ES, *(u16*)(BX+0)));
1879 SET_BDA(video_rows, GET_FARVAR(ES, *(u8*)(BX+0)));
1881 SET_BDA(char_height, GET_FARVAR(ES, *(u16*)(BX+0)));
1883 SET_BDA(video_ctl, GET_FARVAR(ES, *(u8*)(BX+0)));
1885 SET_BDA(video_switches, GET_FARVAR(ES, *(u8*)(BX+0)));
1887 SET_BDA(modeset_ctl, GET_FARVAR(ES, *(u8*)(BX+0)));
1889 SET_BDA(cursor_type, GET_FARVAR(ES, *(u16*)(BX+0)));
1892 for (i = 0; i < 8; i++) {
1893 SET_BDA(cursor_pos[i], GET_FARVAR(ES, *(u16*)(BX+0)));
1896 SET_BDA(video_pagestart, GET_FARVAR(ES, *(u16*)(BX+0)));
1898 SET_BDA(video_page, GET_FARVAR(ES, *(u8*)(BX+0)));
1901 SET_IVT(0x1f, GET_FARVAR(ES, *(u16*)(BX+2)), GET_FARVAR(ES, *(u16*)(BX+0)));
1903 SET_IVT(0x43, GET_FARVAR(ES, *(u16*)(BX+2)), GET_FARVAR(ES, *(u16*)(BX+0)));
1908 u16 v = GET_FARVAR(ES, *(u8*)(BX+0));
1910 outb(GET_FARVAR(ES, *(u8*)(BX+0)), VGAREG_PEL_MASK);
1912 // Set the whole dac always, from 0
1913 outb(0x00, VGAREG_DAC_WRITE_ADDRESS);
1915 for (i = 0; i < 256 * 3; i++) {
1916 outb(GET_FARVAR(ES, *(u8*)(BX+0)), VGAREG_DAC_DATA);
1920 outb(v, VGAREG_DAC_WRITE_ADDRESS);
1926 /****************************************************************
1927 * VGA int 10 handler
1928 ****************************************************************/
1931 handle_1000(struct bregs *regs)
1934 biosfn_set_video_mode(regs->al);
1935 switch(regs->al & 0x7F) {
1954 handle_1001(struct bregs *regs)
1956 biosfn_set_cursor_shape(regs->ch, regs->cl);
1960 handle_1002(struct bregs *regs)
1962 biosfn_set_cursor_pos(regs->bh, regs->dx);
1966 handle_1003(struct bregs *regs)
1968 biosfn_get_cursor_pos(regs->bh, ®s->cx, ®s->dx);
1971 // Read light pen pos (unimplemented)
1973 handle_1004(struct bregs *regs)
1976 regs->ax = regs->bx = regs->cx = regs->dx = 0;
1980 handle_1005(struct bregs *regs)
1982 biosfn_set_active_page(regs->al);
1986 handle_1006(struct bregs *regs)
1988 biosfn_scroll(regs->al, regs->bh, regs->ch, regs->cl, regs->dh, regs->dl
1993 handle_1007(struct bregs *regs)
1995 biosfn_scroll(regs->al, regs->bh, regs->ch, regs->cl, regs->dh, regs->dl
1996 , 0xFF, SCROLL_DOWN);
2000 handle_1008(struct bregs *regs)
2003 biosfn_read_char_attr(regs->bh, ®s->ax);
2007 handle_1009(struct bregs *regs)
2010 biosfn_write_char_attr(regs->al, regs->bh, regs->bl, regs->cx);
2014 handle_100a(struct bregs *regs)
2017 biosfn_write_char_only(regs->al, regs->bh, regs->bl, regs->cx);
2022 handle_100b00(struct bregs *regs)
2025 biosfn_set_border_color(regs);
2029 handle_100b01(struct bregs *regs)
2032 biosfn_set_palette(regs);
2036 handle_100bXX(struct bregs *regs)
2042 handle_100b(struct bregs *regs)
2045 case 0x00: handle_100b00(regs); break;
2046 case 0x01: handle_100b01(regs); break;
2047 default: handle_100bXX(regs); break;
2053 handle_100c(struct bregs *regs)
2056 biosfn_write_pixel(regs->bh, regs->al, regs->cx, regs->dx);
2060 handle_100d(struct bregs *regs)
2063 biosfn_read_pixel(regs->bh, regs->cx, regs->dx, ®s->ax);
2067 handle_100e(struct bregs *regs)
2069 // Ralf Brown Interrupt list is WRONG on bh(page)
2070 // We do output only on the current page !
2071 biosfn_write_teletype(regs->al, 0xff, regs->bl, NO_ATTR);
2075 handle_100f(struct bregs *regs)
2078 biosfn_get_video_mode(regs);
2083 handle_101000(struct bregs *regs)
2085 if (regs->bl > 0x14)
2087 biosfn_set_single_palette_reg(regs->bl, regs->bh);
2091 handle_101001(struct bregs *regs)
2094 biosfn_set_overscan_border_color(regs);
2098 handle_101002(struct bregs *regs)
2101 biosfn_set_all_palette_reg(regs);
2105 handle_101003(struct bregs *regs)
2108 biosfn_toggle_intensity(regs);
2112 handle_101007(struct bregs *regs)
2114 if (regs->bl > 0x14)
2116 regs->bh = biosfn_get_single_palette_reg(regs->bl);
2120 handle_101008(struct bregs *regs)
2123 biosfn_read_overscan_border_color(regs);
2127 handle_101009(struct bregs *regs)
2130 biosfn_get_all_palette_reg(regs);
2134 handle_101010(struct bregs *regs)
2137 biosfn_set_single_dac_reg(regs);
2141 handle_101012(struct bregs *regs)
2144 biosfn_set_all_dac_reg(regs);
2148 handle_101013(struct bregs *regs)
2151 biosfn_select_video_dac_color_page(regs);
2155 handle_101015(struct bregs *regs)
2158 biosfn_read_single_dac_reg(regs);
2162 handle_101017(struct bregs *regs)
2165 biosfn_read_all_dac_reg(regs);
2169 handle_101018(struct bregs *regs)
2172 biosfn_set_pel_mask(regs);
2176 handle_101019(struct bregs *regs)
2179 biosfn_read_pel_mask(regs);
2183 handle_10101a(struct bregs *regs)
2186 biosfn_read_video_dac_state(regs);
2190 handle_10101b(struct bregs *regs)
2192 biosfn_perform_gray_scale_summing(regs->bx, regs->cx);
2196 handle_1010XX(struct bregs *regs)
2202 handle_1010(struct bregs *regs)
2205 case 0x00: handle_101000(regs); break;
2206 case 0x01: handle_101001(regs); break;
2207 case 0x02: handle_101002(regs); break;
2208 case 0x03: handle_101003(regs); break;
2209 case 0x07: handle_101007(regs); break;
2210 case 0x08: handle_101008(regs); break;
2211 case 0x09: handle_101009(regs); break;
2212 case 0x10: handle_101010(regs); break;
2213 case 0x12: handle_101012(regs); break;
2214 case 0x13: handle_101013(regs); break;
2215 case 0x15: handle_101015(regs); break;
2216 case 0x17: handle_101017(regs); break;
2217 case 0x18: handle_101018(regs); break;
2218 case 0x19: handle_101019(regs); break;
2219 case 0x1a: handle_10101a(regs); break;
2220 case 0x1b: handle_10101b(regs); break;
2221 default: handle_1010XX(regs); break;
2227 handle_101100(struct bregs *regs)
2230 biosfn_load_text_user_pat(regs->al, regs->es, 0 // XXX - regs->bp
2231 , regs->cx, regs->dx, regs->bl, regs->bh);
2235 handle_101101(struct bregs *regs)
2238 biosfn_load_text_8_14_pat(regs->al, regs->bl);
2242 handle_101102(struct bregs *regs)
2245 biosfn_load_text_8_8_pat(regs->al, regs->bl);
2249 handle_101103(struct bregs *regs)
2252 biosfn_set_text_block_specifier(regs);
2256 handle_101104(struct bregs *regs)
2259 biosfn_load_text_8_16_pat(regs->al, regs->bl);
2263 handle_101110(struct bregs *regs)
2265 handle_101100(regs);
2269 handle_101111(struct bregs *regs)
2271 handle_101101(regs);
2275 handle_101112(struct bregs *regs)
2277 handle_101102(regs);
2281 handle_101114(struct bregs *regs)
2283 handle_101104(regs);
2287 handle_101130(struct bregs *regs)
2290 biosfn_get_font_info(regs->bh, ®s->es, 0 // ®s->bp
2291 , ®s->cx, ®s->dx);
2295 handle_1011XX(struct bregs *regs)
2301 handle_1011(struct bregs *regs)
2304 case 0x00: handle_101100(regs); break;
2305 case 0x01: handle_101101(regs); break;
2306 case 0x02: handle_101102(regs); break;
2307 case 0x03: handle_101103(regs); break;
2308 case 0x04: handle_101104(regs); break;
2309 case 0x10: handle_101110(regs); break;
2310 case 0x11: handle_101111(regs); break;
2311 case 0x12: handle_101112(regs); break;
2312 case 0x14: handle_101114(regs); break;
2313 case 0x30: handle_101130(regs); break;
2314 default: handle_1011XX(regs); break;
2320 handle_101210(struct bregs *regs)
2323 biosfn_get_ega_info(regs);
2327 handle_101230(struct bregs *regs)
2330 biosfn_select_vert_res(regs);
2334 handle_101231(struct bregs *regs)
2337 biosfn_enable_default_palette_loading(regs);
2341 handle_101232(struct bregs *regs)
2344 biosfn_enable_video_addressing(regs);
2348 handle_101233(struct bregs *regs)
2351 biosfn_enable_grayscale_summing(regs);
2355 handle_101234(struct bregs *regs)
2358 biosfn_enable_cursor_emulation(regs);
2362 handle_101235(struct bregs *regs)
2369 handle_101236(struct bregs *regs)
2376 handle_1012XX(struct bregs *regs)
2382 handle_1012(struct bregs *regs)
2385 case 0x10: handle_101210(regs); break;
2386 case 0x30: handle_101230(regs); break;
2387 case 0x31: handle_101231(regs); break;
2388 case 0x32: handle_101232(regs); break;
2389 case 0x33: handle_101233(regs); break;
2390 case 0x34: handle_101234(regs); break;
2391 case 0x35: handle_101235(regs); break;
2392 case 0x36: handle_101236(regs); break;
2393 default: handle_1012XX(regs); break;
2396 // XXX - cirrus has 1280, 1281, 1282, 1285, 129a, 12a0, 12a1, 12a2, 12ae
2401 handle_1013(struct bregs *regs)
2404 biosfn_write_string(regs->al, regs->bh, regs->bl, regs->cx
2405 , regs->dh, regs->dl, regs->es, 0); // regs->bp);
2410 handle_101a00(struct bregs *regs)
2413 biosfn_read_display_code(regs);
2417 handle_101a01(struct bregs *regs)
2420 biosfn_set_display_code(regs);
2424 handle_101aXX(struct bregs *regs)
2430 handle_101a(struct bregs *regs)
2433 case 0x00: handle_101a00(regs); break;
2434 case 0x01: handle_101a01(regs); break;
2435 default: handle_101aXX(regs); break;
2441 handle_101b(struct bregs *regs)
2444 biosfn_read_state_info(regs->bx, regs->es, regs->di);
2450 handle_101c00(struct bregs *regs)
2453 regs->bx = biosfn_read_video_state_size(regs->cx);
2457 handle_101c01(struct bregs *regs)
2460 biosfn_save_video_state(regs->cx, regs->es, regs->bx);
2464 handle_101c02(struct bregs *regs)
2467 biosfn_restore_video_state(regs->cx, regs->es, regs->bx);
2471 handle_101cXX(struct bregs *regs)
2477 handle_101c(struct bregs *regs)
2480 case 0x00: handle_101c00(regs); break;
2481 case 0x01: handle_101c01(regs); break;
2482 case 0x02: handle_101c02(regs); break;
2483 default: handle_101cXX(regs); break;
2489 handle_104f00(struct bregs *regs)
2491 // XXX - vbe_biosfn_return_controller_information(&AX,ES,DI);
2492 // XXX - OR cirrus_vesa_00h
2496 handle_104f01(struct bregs *regs)
2498 // XXX - vbe_biosfn_return_mode_information(&AX,CX,ES,DI);
2499 // XXX - OR cirrus_vesa_01h
2503 handle_104f02(struct bregs *regs)
2505 // XXX - vbe_biosfn_set_mode(&AX,BX,ES,DI);
2506 // XXX - OR cirrus_vesa_02h
2510 handle_104f03(struct bregs *regs)
2512 // XXX - vbe_biosfn_return_current_mode
2513 // XXX - OR cirrus_vesa_03h
2517 handle_104f04(struct bregs *regs)
2519 // XXX - vbe_biosfn_save_restore_state(&AX, CX, DX, ES, &BX);
2523 handle_104f05(struct bregs *regs)
2525 // XXX - vbe_biosfn_display_window_control
2526 // XXX - OR cirrus_vesa_05h
2530 handle_104f06(struct bregs *regs)
2532 // XXX - vbe_biosfn_set_get_logical_scan_line_length
2533 // XXX - OR cirrus_vesa_06h
2537 handle_104f07(struct bregs *regs)
2539 // XXX - vbe_biosfn_set_get_display_start
2540 // XXX - OR cirrus_vesa_07h
2544 handle_104f08(struct bregs *regs)
2546 // XXX - vbe_biosfn_set_get_dac_palette_format
2550 handle_104f0a(struct bregs *regs)
2552 // XXX - vbe_biosfn_return_protected_mode_interface
2556 handle_104fXX(struct bregs *regs)
2563 handle_104f(struct bregs *regs)
2566 handle_104fXX(regs);
2570 // XXX - check vbe_has_vbe_display()?
2573 case 0x00: handle_104f00(regs); break;
2574 case 0x01: handle_104f01(regs); break;
2575 case 0x02: handle_104f02(regs); break;
2576 case 0x03: handle_104f03(regs); break;
2577 case 0x04: handle_104f04(regs); break;
2578 case 0x05: handle_104f05(regs); break;
2579 case 0x06: handle_104f06(regs); break;
2580 case 0x07: handle_104f07(regs); break;
2581 case 0x08: handle_104f08(regs); break;
2582 case 0x0a: handle_104f0a(regs); break;
2583 default: handle_104fXX(regs); break;
2589 handle_10XX(struct bregs *regs)
2594 // INT 10h Video Support Service Entry Point
2596 handle_10(struct bregs *regs)
2598 debug_enter(regs, DEBUG_VGA_10);
2600 case 0x00: handle_1000(regs); break;
2601 case 0x01: handle_1001(regs); break;
2602 case 0x02: handle_1002(regs); break;
2603 case 0x03: handle_1003(regs); break;
2604 case 0x04: handle_1004(regs); break;
2605 case 0x05: handle_1005(regs); break;
2606 case 0x06: handle_1006(regs); break;
2607 case 0x07: handle_1007(regs); break;
2608 case 0x08: handle_1008(regs); break;
2609 case 0x09: handle_1009(regs); break;
2610 case 0x0a: handle_100a(regs); break;
2611 case 0x0b: handle_100b(regs); break;
2612 case 0x0c: handle_100c(regs); break;
2613 case 0x0d: handle_100d(regs); break;
2614 case 0x0e: handle_100e(regs); break;
2615 case 0x0f: handle_100f(regs); break;
2616 case 0x10: handle_1010(regs); break;
2617 case 0x11: handle_1011(regs); break;
2618 case 0x12: handle_1012(regs); break;
2619 case 0x13: handle_1013(regs); break;
2620 case 0x1a: handle_101a(regs); break;
2621 case 0x1b: handle_101b(regs); break;
2622 case 0x1c: handle_101c(regs); break;
2623 case 0x4f: handle_104f(regs); break;
2624 default: handle_10XX(regs); break;
2629 /****************************************************************
2631 ****************************************************************/
2636 // init detected hardware BIOS Area
2637 // set 80x25 color (not clear from RBIL but usual)
2638 u16 eqf = GET_BDA(equipment_list_flags);
2639 SET_BDA(equipment_list_flags, (eqf & 0xffcf) | 0x20);
2641 // Just for the first int10 find its children
2643 // the default char height
2644 SET_BDA(char_height, 0x10);
2647 SET_BDA(video_ctl, 0x60);
2649 // Set the basic screen we have
2650 SET_BDA(video_switches, 0xf9);
2652 // Set the basic modeset options
2653 SET_BDA(modeset_ctl, 0x51);
2655 // Set the default MSR
2656 SET_BDA(video_msr, 0x09);
2662 // switch to color mode and enable CPU access 480 lines
2663 outb(0xc3, VGAREG_WRITE_MISC_OUTPUT);
2664 // more than 64k 3C4/04
2665 outb(0x04, VGAREG_SEQU_ADDRESS);
2666 outb(0x02, VGAREG_SEQU_DATA);
2670 vga_post(struct bregs *regs)
2672 debug_enter(regs, DEBUG_VGA_POST);
2680 extern void entry_10(void);
2681 SET_IVT(0x10, 0xC000, (u32)entry_10);
2686 // XXX - clear screen and display info
2689 SET_VGA(video_save_pointer_table[0], (u32)video_param_table);
2690 SET_VGA(video_save_pointer_table[1], 0xC000);
2693 extern u8 _rom_header_size, _rom_header_checksum;
2694 SET_VGA(_rom_header_checksum, 0);
2695 u8 sum = -checksum_far(0xC000, 0, _rom_header_size * 512);
2696 SET_VGA(_rom_header_checksum, sum);