1 // Standard VGA driver code
3 // Copyright (C) 2009 Kevin O'Connor <kevin@koconnor.net>
4 // Copyright (C) 2001-2008 the LGPL VGABios developers Team
6 // This file may be distributed under the terms of the GNU LGPLv3 license.
8 #include "stdvga.h" // stdvga_init
9 #include "ioport.h" // outb
10 #include "farptr.h" // SET_FARVAR
11 #include "biosvar.h" // GET_GLOBAL
12 #include "util.h" // memcpy_far
15 /****************************************************************
17 ****************************************************************/
20 stdvga_set_border_color(u8 color)
25 stdvga_attr_write(0x00, v1);
28 for (i = 1; i < 4; i++)
29 stdvga_attr_mask(i, 0x10, color & 0x10);
33 stdvga_set_overscan_border_color(u8 color)
35 stdvga_attr_write(0x11, color);
39 stdvga_get_overscan_border_color(void)
41 return stdvga_attr_read(0x11);
45 stdvga_set_palette(u8 palid)
48 for (i = 1; i < 4; i++)
49 stdvga_attr_mask(i, 0x01, palid & 0x01);
53 stdvga_set_all_palette_reg(u16 seg, u8 *data_far)
56 for (i = 0; i < 0x10; i++) {
57 stdvga_attr_write(i, GET_FARVAR(seg, *data_far));
60 stdvga_attr_write(0x11, GET_FARVAR(seg, *data_far));
64 stdvga_get_all_palette_reg(u16 seg, u8 *data_far)
67 for (i = 0; i < 0x10; i++) {
68 SET_FARVAR(seg, *data_far, stdvga_attr_read(i));
71 SET_FARVAR(seg, *data_far, stdvga_attr_read(0x11));
75 stdvga_toggle_intensity(u8 flag)
77 stdvga_attr_mask(0x10, 0x08, (flag & 0x01) << 3);
81 stdvga_select_video_dac_color_page(u8 flag, u8 data)
85 stdvga_attr_mask(0x10, 0x80, data << 7);
89 u8 val = stdvga_attr_read(0x10);
93 stdvga_attr_write(0x14, data);
97 stdvga_read_video_dac_state(u8 *pmode, u8 *curpage)
99 u8 val1 = stdvga_attr_read(0x10) >> 7;
100 u8 val2 = stdvga_attr_read(0x14) & 0x0f;
108 /****************************************************************
110 ****************************************************************/
113 stdvga_save_dac_state(u16 seg, struct saveDACcolors *info)
115 /* XXX: check this */
116 SET_FARVAR(seg, info->rwmode, inb(VGAREG_DAC_STATE));
117 SET_FARVAR(seg, info->peladdr, inb(VGAREG_DAC_WRITE_ADDRESS));
118 SET_FARVAR(seg, info->pelmask, stdvga_pelmask_read());
119 stdvga_dac_read(seg, info->dac, 0, 256);
120 SET_FARVAR(seg, info->color_select, 0);
124 stdvga_restore_dac_state(u16 seg, struct saveDACcolors *info)
126 stdvga_pelmask_write(GET_FARVAR(seg, info->pelmask));
127 stdvga_dac_write(seg, info->dac, 0, 256);
128 outb(GET_FARVAR(seg, info->peladdr), VGAREG_DAC_WRITE_ADDRESS);
132 stdvga_perform_gray_scale_summing(u16 start, u16 count)
134 stdvga_attrindex_write(0x00);
136 for (i = start; i < start+count; i++) {
138 stdvga_dac_read(GET_SEG(SS), rgb, i, 1);
140 // intensity = ( 0.3 * Red ) + ( 0.59 * Green ) + ( 0.11 * Blue )
141 u16 intensity = ((77 * rgb[0] + 151 * rgb[1] + 28 * rgb[2]) + 0x80) >> 8;
142 if (intensity > 0x3f)
145 stdvga_dac_write(GET_SEG(SS), rgb, i, 1);
147 stdvga_attrindex_write(0x20);
151 /****************************************************************
153 ****************************************************************/
156 stdvga_set_text_block_specifier(u8 spec)
158 stdvga_sequ_write(0x03, spec);
161 // Enable reads and writes to the given "plane" when in planar4 mode.
163 stdvga_planar4_plane(int plane)
166 // Return to default mode (read plane0, write all planes)
167 stdvga_sequ_write(0x02, 0x0f);
168 stdvga_grdc_write(0x04, 0);
170 stdvga_sequ_write(0x02, 1<<plane);
171 stdvga_grdc_write(0x04, plane);
176 /****************************************************************
178 ****************************************************************/
181 get_font_access(void)
183 stdvga_sequ_write(0x00, 0x01);
184 stdvga_sequ_write(0x02, 0x04);
185 stdvga_sequ_write(0x04, 0x07);
186 stdvga_sequ_write(0x00, 0x03);
187 stdvga_grdc_write(0x04, 0x02);
188 stdvga_grdc_write(0x05, 0x00);
189 stdvga_grdc_write(0x06, 0x04);
193 release_font_access(void)
195 stdvga_sequ_write(0x00, 0x01);
196 stdvga_sequ_write(0x02, 0x03);
197 stdvga_sequ_write(0x04, 0x03);
198 stdvga_sequ_write(0x00, 0x03);
199 u16 v = (stdvga_misc_read() & 0x01) ? 0x0e : 0x0a;
200 stdvga_grdc_write(0x06, v);
201 stdvga_grdc_write(0x04, 0x00);
202 stdvga_grdc_write(0x05, 0x10);
206 stdvga_load_font(u16 seg, void *src_far, u16 count
207 , u16 start, u8 destflags, u8 fontsize)
210 u16 blockaddr = ((destflags & 0x03) << 14) + ((destflags & 0x04) << 11);
211 void *dest_far = (void*)(blockaddr + start*32);
213 for (i = 0; i < count; i++)
214 memcpy_far(SEG_GRAPH, dest_far + i*32
215 , seg, src_far + i*fontsize, fontsize);
216 release_font_access();
220 /****************************************************************
222 ****************************************************************/
225 stdvga_get_crtc(void)
227 if (stdvga_misc_read() & 1)
228 return VGAREG_VGA_CRTC_ADDRESS;
229 return VGAREG_MDA_CRTC_ADDRESS;
232 // Return the multiplication factor needed for the vga offset register.
234 stdvga_bpp_factor(struct vgamode_s *vmode_g)
236 switch (GET_GLOBAL(vmode_g->memmodel)) {
240 return GET_GLOBAL(vmode_g->depth);
249 stdvga_set_cursor_shape(u8 start, u8 end)
251 u16 crtc_addr = stdvga_get_crtc();
252 stdvga_crtc_write(crtc_addr, 0x0a, start);
253 stdvga_crtc_write(crtc_addr, 0x0b, end);
257 stdvga_set_cursor_pos(u16 address)
259 u16 crtc_addr = stdvga_get_crtc();
260 stdvga_crtc_write(crtc_addr, 0x0e, address >> 8);
261 stdvga_crtc_write(crtc_addr, 0x0f, address);
265 stdvga_set_scan_lines(u8 lines)
267 stdvga_crtc_mask(stdvga_get_crtc(), 0x09, 0x1f, lines - 1);
270 // Get vertical display end
274 u16 crtc_addr = stdvga_get_crtc();
275 u16 vde = stdvga_crtc_read(crtc_addr, 0x12);
276 u8 ovl = stdvga_crtc_read(crtc_addr, 0x07);
277 vde += (((ovl & 0x02) << 7) + ((ovl & 0x40) << 3) + 1);
282 stdvga_get_window(struct vgamode_s *vmode_g, int window)
288 stdvga_set_window(struct vgamode_s *vmode_g, int window, int val)
294 stdvga_get_linelength(struct vgamode_s *vmode_g)
296 u8 val = stdvga_crtc_read(stdvga_get_crtc(), 0x13);
297 return val * stdvga_bpp_factor(vmode_g) * 2;
301 stdvga_set_linelength(struct vgamode_s *vmode_g, int val)
303 int factor = stdvga_bpp_factor(vmode_g) * 2;
304 stdvga_crtc_write(stdvga_get_crtc(), 0x13, DIV_ROUND_UP(val, factor));
309 stdvga_get_displaystart(struct vgamode_s *vmode_g)
311 u16 crtc_addr = stdvga_get_crtc();
312 int addr = (stdvga_crtc_read(crtc_addr, 0x0c) << 8
313 | stdvga_crtc_read(crtc_addr, 0x0d));
314 return addr * stdvga_bpp_factor(vmode_g);
318 stdvga_set_displaystart(struct vgamode_s *vmode_g, int val)
320 u16 crtc_addr = stdvga_get_crtc();
321 val /= stdvga_bpp_factor(vmode_g);
322 stdvga_crtc_write(crtc_addr, 0x0c, val >> 8);
323 stdvga_crtc_write(crtc_addr, 0x0d, val);
328 /****************************************************************
329 * Save/Restore/Set state
330 ****************************************************************/
333 stdvga_save_state(u16 seg, struct saveVideoHardware *info)
335 u16 crtc_addr = stdvga_get_crtc();
336 SET_FARVAR(seg, info->sequ_index, inb(VGAREG_SEQU_ADDRESS));
337 SET_FARVAR(seg, info->crtc_index, inb(crtc_addr));
338 SET_FARVAR(seg, info->grdc_index, inb(VGAREG_GRDC_ADDRESS));
339 SET_FARVAR(seg, info->actl_index, stdvga_attrindex_read());
340 SET_FARVAR(seg, info->feature, inb(VGAREG_READ_FEATURE_CTL));
344 SET_FARVAR(seg, info->sequ_regs[i], stdvga_sequ_read(i+1));
345 SET_FARVAR(seg, info->sequ0, stdvga_sequ_read(0));
348 SET_FARVAR(seg, info->crtc_regs[i], stdvga_crtc_read(crtc_addr, i));
351 SET_FARVAR(seg, info->actl_regs[i], stdvga_attr_read(i));
354 SET_FARVAR(seg, info->grdc_regs[i], stdvga_grdc_read(i));
356 SET_FARVAR(seg, info->crtc_addr, crtc_addr);
358 /* XXX: read plane latches */
360 SET_FARVAR(seg, info->plane_latch[i], 0);
364 stdvga_restore_state(u16 seg, struct saveVideoHardware *info)
368 stdvga_sequ_write(i+1, GET_FARVAR(seg, info->sequ_regs[i]));
369 stdvga_sequ_write(0x00, GET_FARVAR(seg, info->sequ0));
371 // Disable CRTC write protection
372 u16 crtc_addr = GET_FARVAR(seg, info->crtc_addr);
373 stdvga_crtc_write(crtc_addr, 0x11, 0x00);
377 stdvga_crtc_write(crtc_addr, i, GET_FARVAR(seg, info->crtc_regs[i]));
378 // select crtc base address
379 stdvga_misc_mask(0x01, crtc_addr == VGAREG_VGA_CRTC_ADDRESS ? 0x01 : 0x00);
381 // enable write protection if needed
382 stdvga_crtc_write(crtc_addr, 0x11, GET_FARVAR(seg, info->crtc_regs[0x11]));
386 stdvga_attr_write(i, GET_FARVAR(seg, info->actl_regs[i]));
387 stdvga_attrindex_write(GET_FARVAR(seg, info->actl_index));
390 stdvga_grdc_write(i, GET_FARVAR(seg, info->grdc_regs[i]));
392 outb(GET_FARVAR(seg, info->sequ_index), VGAREG_SEQU_ADDRESS);
393 outb(GET_FARVAR(seg, info->crtc_index), crtc_addr);
394 outb(GET_FARVAR(seg, info->grdc_index), VGAREG_GRDC_ADDRESS);
395 outb(GET_FARVAR(seg, info->feature), crtc_addr - 0x4 + 0xa);
399 clear_screen(struct vgamode_s *vmode_g)
401 switch (GET_GLOBAL(vmode_g->memmodel)) {
403 memset16_far(GET_GLOBAL(vmode_g->sstart), 0, 0x0720, 32*1024);
406 memset16_far(GET_GLOBAL(vmode_g->sstart), 0, 0x0000, 32*1024);
409 // XXX - old code gets/sets/restores sequ register 2 to 0xf -
410 // but it should always be 0xf anyway.
411 memset16_far(GET_GLOBAL(vmode_g->sstart), 0, 0x0000, 64*1024);
416 stdvga_set_mode(struct vgamode_s *vmode_g, int flags)
418 if (! stdvga_is_mode(vmode_g)) {
419 warn_internalerror();
422 struct stdvga_mode_s *stdmode_g = container_of(
423 vmode_g, struct stdvga_mode_s, info);
425 // if palette loading (bit 3 of modeset ctl = 0)
426 if (!(flags & MF_NOPALETTE)) { // Set the PEL mask
427 stdvga_pelmask_write(GET_GLOBAL(stdmode_g->pelmask));
429 // From which palette
430 u8 *palette_g = GET_GLOBAL(stdmode_g->dac);
431 u16 palsize = GET_GLOBAL(stdmode_g->dacsize) / 3;
433 // Always 256*3 values
434 stdvga_dac_write(get_global_seg(), palette_g, 0, palsize);
436 for (i = palsize; i < 0x0100; i++) {
437 static u8 rgb[3] VAR16;
438 stdvga_dac_write(get_global_seg(), rgb, i, 1);
441 if (flags & MF_GRAYSUM)
442 stdvga_perform_gray_scale_summing(0x00, 0x100);
446 u8 *regs = GET_GLOBAL(stdmode_g->actl_regs);
448 for (i = 0; i <= 0x13; i++)
449 stdvga_attr_write(i, GET_GLOBAL(regs[i]));
450 stdvga_attr_write(0x14, 0x00);
453 stdvga_sequ_write(0x00, 0x03);
454 regs = GET_GLOBAL(stdmode_g->sequ_regs);
455 for (i = 1; i <= 4; i++)
456 stdvga_sequ_write(i, GET_GLOBAL(regs[i - 1]));
459 regs = GET_GLOBAL(stdmode_g->grdc_regs);
460 for (i = 0; i <= 8; i++)
461 stdvga_grdc_write(i, GET_GLOBAL(regs[i]));
463 // Set CRTC address VGA or MDA
464 u8 miscreg = GET_GLOBAL(stdmode_g->miscreg);
465 u16 crtc_addr = VGAREG_VGA_CRTC_ADDRESS;
467 crtc_addr = VGAREG_MDA_CRTC_ADDRESS;
469 // Disable CRTC write protection
470 stdvga_crtc_write(crtc_addr, 0x11, 0x00);
472 regs = GET_GLOBAL(stdmode_g->crtc_regs);
473 for (i = 0; i <= 0x18; i++)
474 stdvga_crtc_write(crtc_addr, i, GET_GLOBAL(regs[i]));
476 // Set the misc register
477 stdvga_misc_write(miscreg);
480 stdvga_attrindex_write(0x20);
483 if (!(flags & MF_NOCLEARMEM))
484 clear_screen(vmode_g);
486 // Write the fonts in memory
487 u8 memmodel = GET_GLOBAL(vmode_g->memmodel);
488 if (memmodel == MM_TEXT)
489 stdvga_load_font(get_global_seg(), vgafont16, 0x100, 0, 0, 16);
495 /****************************************************************
497 ****************************************************************/
500 stdvga_list_modes(u16 seg, u16 *dest, u16 *last)
502 SET_FARVAR(seg, *dest, 0xffff);
506 stdvga_enable_video_addressing(u8 disable)
508 u8 v = (disable & 1) ? 0x00 : 0x02;
509 stdvga_misc_mask(0x02, v);
515 // switch to color mode and enable CPU access 480 lines
516 stdvga_misc_write(0xc3);
517 // more than 64k 3C4/04
518 stdvga_sequ_write(0x04, 0x02);