3 // Copyright (C) 2009 Kevin O'Connor <kevin@koconnor.net>
4 // Copyright (C) 2001-2008 the LGPL VGABios developers Team
6 // This file may be distributed under the terms of the GNU LGPLv3 license.
8 #include "stdvga.h" // stdvga_init
9 #include "ioport.h" // outb
10 #include "farptr.h" // SET_FARVAR
11 #include "biosvar.h" // GET_GLOBAL
12 #include "util.h" // memcpy_far
13 #include "vgabios.h" // find_vga_entry
16 // * replace direct in/out calls with wrapper functions
19 /****************************************************************
21 ****************************************************************/
24 stdvga_screen_disable(void)
26 inb(VGAREG_ACTL_RESET);
27 outb(0x00, VGAREG_ACTL_ADDRESS);
31 stdvga_screen_enable(void)
33 inb(VGAREG_ACTL_RESET);
34 outb(0x20, VGAREG_ACTL_ADDRESS);
38 stdvga_set_border_color(u8 color)
40 inb(VGAREG_ACTL_RESET);
41 outb(0x00, VGAREG_ACTL_ADDRESS);
45 outb(v1, VGAREG_ACTL_WRITE_DATA);
49 for (i = 1; i < 4; i++) {
50 outb(i, VGAREG_ACTL_ADDRESS);
52 u8 cur = inb(VGAREG_ACTL_READ_DATA);
55 outb(cur, VGAREG_ACTL_WRITE_DATA);
57 outb(0x20, VGAREG_ACTL_ADDRESS);
61 stdvga_set_overscan_border_color(u8 color)
63 inb(VGAREG_ACTL_RESET);
64 outb(0x11, VGAREG_ACTL_ADDRESS);
65 outb(color, VGAREG_ACTL_WRITE_DATA);
66 outb(0x20, VGAREG_ACTL_ADDRESS);
70 stdvga_get_overscan_border_color(void)
72 inb(VGAREG_ACTL_RESET);
73 outb(0x11, VGAREG_ACTL_ADDRESS);
74 u8 v = inb(VGAREG_ACTL_READ_DATA);
75 inb(VGAREG_ACTL_RESET);
76 outb(0x20, VGAREG_ACTL_ADDRESS);
81 stdvga_set_palette(u8 palid)
83 inb(VGAREG_ACTL_RESET);
86 for (i = 1; i < 4; i++) {
87 outb(i, VGAREG_ACTL_ADDRESS);
89 u8 v = inb(VGAREG_ACTL_READ_DATA);
92 outb(v, VGAREG_ACTL_WRITE_DATA);
94 outb(0x20, VGAREG_ACTL_ADDRESS);
98 stdvga_set_single_palette_reg(u8 reg, u8 val)
100 inb(VGAREG_ACTL_RESET);
101 outb(reg, VGAREG_ACTL_ADDRESS);
102 outb(val, VGAREG_ACTL_WRITE_DATA);
103 outb(0x20, VGAREG_ACTL_ADDRESS);
107 stdvga_get_single_palette_reg(u8 reg)
109 inb(VGAREG_ACTL_RESET);
110 outb(reg, VGAREG_ACTL_ADDRESS);
111 u8 v = inb(VGAREG_ACTL_READ_DATA);
112 inb(VGAREG_ACTL_RESET);
113 outb(0x20, VGAREG_ACTL_ADDRESS);
118 stdvga_set_all_palette_reg(u16 seg, u8 *data_far)
120 inb(VGAREG_ACTL_RESET);
122 for (i = 0; i < 0x10; i++) {
123 outb(i, VGAREG_ACTL_ADDRESS);
124 u8 val = GET_FARVAR(seg, *data_far);
125 outb(val, VGAREG_ACTL_WRITE_DATA);
128 outb(0x11, VGAREG_ACTL_ADDRESS);
129 outb(GET_FARVAR(seg, *data_far), VGAREG_ACTL_WRITE_DATA);
130 outb(0x20, VGAREG_ACTL_ADDRESS);
134 stdvga_get_all_palette_reg(u16 seg, u8 *data_far)
137 for (i = 0; i < 0x10; i++) {
138 inb(VGAREG_ACTL_RESET);
139 outb(i, VGAREG_ACTL_ADDRESS);
140 SET_FARVAR(seg, *data_far, inb(VGAREG_ACTL_READ_DATA));
143 inb(VGAREG_ACTL_RESET);
144 outb(0x11, VGAREG_ACTL_ADDRESS);
145 SET_FARVAR(seg, *data_far, inb(VGAREG_ACTL_READ_DATA));
146 inb(VGAREG_ACTL_RESET);
147 outb(0x20, VGAREG_ACTL_ADDRESS);
151 stdvga_toggle_intensity(u8 flag)
153 inb(VGAREG_ACTL_RESET);
154 outb(0x10, VGAREG_ACTL_ADDRESS);
155 u8 val = (inb(VGAREG_ACTL_READ_DATA) & 0xf7) | ((flag & 0x01) << 3);
156 outb(val, VGAREG_ACTL_WRITE_DATA);
157 outb(0x20, VGAREG_ACTL_ADDRESS);
161 stdvga_select_video_dac_color_page(u8 flag, u8 data)
163 inb(VGAREG_ACTL_RESET);
164 outb(0x10, VGAREG_ACTL_ADDRESS);
165 u8 val = inb(VGAREG_ACTL_READ_DATA);
166 if (!(flag & 0x01)) {
167 // select paging mode
168 val = (val & 0x7f) | (data << 7);
169 outb(val, VGAREG_ACTL_WRITE_DATA);
170 outb(0x20, VGAREG_ACTL_ADDRESS);
174 inb(VGAREG_ACTL_RESET);
175 outb(0x14, VGAREG_ACTL_ADDRESS);
179 outb(data, VGAREG_ACTL_WRITE_DATA);
180 outb(0x20, VGAREG_ACTL_ADDRESS);
184 stdvga_read_video_dac_state(u8 *pmode, u8 *curpage)
186 inb(VGAREG_ACTL_RESET);
187 outb(0x10, VGAREG_ACTL_ADDRESS);
188 u8 val1 = inb(VGAREG_ACTL_READ_DATA) >> 7;
190 inb(VGAREG_ACTL_RESET);
191 outb(0x14, VGAREG_ACTL_ADDRESS);
192 u8 val2 = inb(VGAREG_ACTL_READ_DATA) & 0x0f;
196 inb(VGAREG_ACTL_RESET);
197 outb(0x20, VGAREG_ACTL_ADDRESS);
204 /****************************************************************
206 ****************************************************************/
209 stdvga_set_dac_regs(u16 seg, u8 *data_far, u8 start, int count)
211 outb(start, VGAREG_DAC_WRITE_ADDRESS);
213 outb(GET_FARVAR(seg, *data_far), VGAREG_DAC_DATA);
215 outb(GET_FARVAR(seg, *data_far), VGAREG_DAC_DATA);
217 outb(GET_FARVAR(seg, *data_far), VGAREG_DAC_DATA);
224 stdvga_get_dac_regs(u16 seg, u8 *data_far, u8 start, int count)
226 outb(start, VGAREG_DAC_READ_ADDRESS);
228 SET_FARVAR(seg, *data_far, inb(VGAREG_DAC_DATA));
230 SET_FARVAR(seg, *data_far, inb(VGAREG_DAC_DATA));
232 SET_FARVAR(seg, *data_far, inb(VGAREG_DAC_DATA));
239 stdvga_set_pel_mask(u8 val)
241 outb(val, VGAREG_PEL_MASK);
245 stdvga_get_pel_mask(void)
247 return inb(VGAREG_PEL_MASK);
251 stdvga_save_dac_state(u16 seg, struct saveDACcolors *info)
253 /* XXX: check this */
254 SET_FARVAR(seg, info->rwmode, inb(VGAREG_DAC_STATE));
255 SET_FARVAR(seg, info->peladdr, inb(VGAREG_DAC_WRITE_ADDRESS));
256 SET_FARVAR(seg, info->pelmask, inb(VGAREG_PEL_MASK));
257 stdvga_get_dac_regs(seg, info->dac, 0, 256);
258 SET_FARVAR(seg, info->color_select, 0);
262 stdvga_restore_dac_state(u16 seg, struct saveDACcolors *info)
264 outb(GET_FARVAR(seg, info->pelmask), VGAREG_PEL_MASK);
265 stdvga_set_dac_regs(seg, info->dac, 0, 256);
266 outb(GET_FARVAR(seg, info->peladdr), VGAREG_DAC_WRITE_ADDRESS);
270 stdvga_perform_gray_scale_summing(u16 start, u16 count)
272 stdvga_screen_disable();
274 for (i = start; i < start+count; i++) {
276 stdvga_get_dac_regs(GET_SEG(SS), rgb, i, 1);
278 // intensity = ( 0.3 * Red ) + ( 0.59 * Green ) + ( 0.11 * Blue )
279 u16 intensity = ((77 * rgb[0] + 151 * rgb[1] + 28 * rgb[2]) + 0x80) >> 8;
280 if (intensity > 0x3f)
283 stdvga_set_dac_regs(GET_SEG(SS), rgb, i, 1);
285 stdvga_screen_enable();
289 /****************************************************************
291 ****************************************************************/
294 stdvga_sequ_write(u8 index, u8 value)
296 outw((value<<8) | index, VGAREG_SEQU_ADDRESS);
300 stdvga_grdc_write(u8 index, u8 value)
302 outw((value<<8) | index, VGAREG_GRDC_ADDRESS);
306 stdvga_set_text_block_specifier(u8 spec)
308 outw((spec << 8) | 0x03, VGAREG_SEQU_ADDRESS);
312 /****************************************************************
314 ****************************************************************/
317 get_font_access(void)
319 outw(0x0100, VGAREG_SEQU_ADDRESS);
320 outw(0x0402, VGAREG_SEQU_ADDRESS);
321 outw(0x0704, VGAREG_SEQU_ADDRESS);
322 outw(0x0300, VGAREG_SEQU_ADDRESS);
323 outw(0x0204, VGAREG_GRDC_ADDRESS);
324 outw(0x0005, VGAREG_GRDC_ADDRESS);
325 outw(0x0406, VGAREG_GRDC_ADDRESS);
329 release_font_access(void)
331 outw(0x0100, VGAREG_SEQU_ADDRESS);
332 outw(0x0302, VGAREG_SEQU_ADDRESS);
333 outw(0x0304, VGAREG_SEQU_ADDRESS);
334 outw(0x0300, VGAREG_SEQU_ADDRESS);
335 u16 v = (inb(VGAREG_READ_MISC_OUTPUT) & 0x01) ? 0x0e : 0x0a;
336 outw((v << 8) | 0x06, VGAREG_GRDC_ADDRESS);
337 outw(0x0004, VGAREG_GRDC_ADDRESS);
338 outw(0x1005, VGAREG_GRDC_ADDRESS);
342 stdvga_load_font(u16 seg, void *src_far, u16 count
343 , u16 start, u8 destflags, u8 fontsize)
346 u16 blockaddr = ((destflags & 0x03) << 14) + ((destflags & 0x04) << 11);
347 void *dest_far = (void*)(blockaddr + start*32);
349 for (i = 0; i < count; i++)
350 memcpy_far(SEG_GRAPH, dest_far + i*32
351 , seg, src_far + i*fontsize, fontsize);
352 release_font_access();
356 /****************************************************************
358 ****************************************************************/
361 stdvga_get_crtc(void)
363 if (inb(VGAREG_READ_MISC_OUTPUT) & 1)
364 return VGAREG_VGA_CRTC_ADDRESS;
365 return VGAREG_MDA_CRTC_ADDRESS;
369 stdvga_set_cursor_shape(u8 start, u8 end)
371 u16 crtc_addr = stdvga_get_crtc();
372 outb(0x0a, crtc_addr);
373 outb(start, crtc_addr + 1);
374 outb(0x0b, crtc_addr);
375 outb(end, crtc_addr + 1);
379 stdvga_set_active_page(u16 address)
381 u16 crtc_addr = stdvga_get_crtc();
382 outb(0x0c, crtc_addr);
383 outb((address & 0xff00) >> 8, crtc_addr + 1);
384 outb(0x0d, crtc_addr);
385 outb(address & 0x00ff, crtc_addr + 1);
389 stdvga_set_cursor_pos(u16 address)
391 u16 crtc_addr = stdvga_get_crtc();
392 outb(0x0e, crtc_addr);
393 outb((address & 0xff00) >> 8, crtc_addr + 1);
394 outb(0x0f, crtc_addr);
395 outb(address & 0x00ff, crtc_addr + 1);
399 stdvga_set_scan_lines(u8 lines)
401 u16 crtc_addr = stdvga_get_crtc();
402 outb(0x09, crtc_addr);
403 u8 crtc_r9 = inb(crtc_addr + 1);
404 crtc_r9 = (crtc_r9 & 0xe0) | (lines - 1);
405 outb(crtc_r9, crtc_addr + 1);
408 // Get vertical display end
412 u16 crtc_addr = stdvga_get_crtc();
413 outb(0x12, crtc_addr);
414 u16 vde = inb(crtc_addr + 1);
415 outb(0x07, crtc_addr);
416 u8 ovl = inb(crtc_addr + 1);
417 vde += (((ovl & 0x02) << 7) + ((ovl & 0x40) << 3) + 1);
422 /****************************************************************
423 * Save/Restore/Set state
424 ****************************************************************/
427 stdvga_save_state(u16 seg, struct saveVideoHardware *info)
429 u16 crtc_addr = stdvga_get_crtc();
430 SET_FARVAR(seg, info->sequ_index, inb(VGAREG_SEQU_ADDRESS));
431 SET_FARVAR(seg, info->crtc_index, inb(crtc_addr));
432 SET_FARVAR(seg, info->grdc_index, inb(VGAREG_GRDC_ADDRESS));
433 inb(VGAREG_ACTL_RESET);
434 u16 ar_index = inb(VGAREG_ACTL_ADDRESS);
435 SET_FARVAR(seg, info->actl_index, ar_index);
436 SET_FARVAR(seg, info->feature, inb(VGAREG_READ_FEATURE_CTL));
439 for (i=0; i<4; i++) {
440 outb(i+1, VGAREG_SEQU_ADDRESS);
441 SET_FARVAR(seg, info->sequ_regs[i], inb(VGAREG_SEQU_DATA));
443 outb(0, VGAREG_SEQU_ADDRESS);
444 SET_FARVAR(seg, info->sequ0, inb(VGAREG_SEQU_DATA));
446 for (i=0; i<25; i++) {
448 SET_FARVAR(seg, info->crtc_regs[i], inb(crtc_addr + 1));
451 for (i=0; i<20; i++) {
452 inb(VGAREG_ACTL_RESET);
453 outb(i | (ar_index & 0x20), VGAREG_ACTL_ADDRESS);
454 SET_FARVAR(seg, info->actl_regs[i], inb(VGAREG_ACTL_READ_DATA));
456 inb(VGAREG_ACTL_RESET);
458 for (i=0; i<9; i++) {
459 outb(i, VGAREG_GRDC_ADDRESS);
460 SET_FARVAR(seg, info->grdc_regs[i], inb(VGAREG_GRDC_DATA));
463 SET_FARVAR(seg, info->crtc_addr, crtc_addr);
465 /* XXX: read plane latches */
467 SET_FARVAR(seg, info->plane_latch[i], 0);
471 stdvga_restore_state(u16 seg, struct saveVideoHardware *info)
473 // Reset Attribute Ctl flip-flop
474 inb(VGAREG_ACTL_RESET);
476 u16 crtc_addr = GET_FARVAR(seg, info->crtc_addr);
479 for (i=0; i<4; i++) {
480 outb(i+1, VGAREG_SEQU_ADDRESS);
481 outb(GET_FARVAR(seg, info->sequ_regs[i]), VGAREG_SEQU_DATA);
483 outb(0, VGAREG_SEQU_ADDRESS);
484 outb(GET_FARVAR(seg, info->sequ0), VGAREG_SEQU_DATA);
486 // Disable CRTC write protection
487 outw(0x0011, crtc_addr);
492 outb(GET_FARVAR(seg, info->crtc_regs[i]), crtc_addr + 1);
494 // select crtc base address
495 u16 v = inb(VGAREG_READ_MISC_OUTPUT) & ~0x01;
496 if (crtc_addr == VGAREG_VGA_CRTC_ADDRESS)
498 outb(v, VGAREG_WRITE_MISC_OUTPUT);
500 // enable write protection if needed
501 outb(0x11, crtc_addr);
502 outb(GET_FARVAR(seg, info->crtc_regs[0x11]), crtc_addr + 1);
505 u16 ar_index = GET_FARVAR(seg, info->actl_index);
506 inb(VGAREG_ACTL_RESET);
507 for (i=0; i<20; i++) {
508 outb(i | (ar_index & 0x20), VGAREG_ACTL_ADDRESS);
509 outb(GET_FARVAR(seg, info->actl_regs[i]), VGAREG_ACTL_WRITE_DATA);
511 outb(ar_index, VGAREG_ACTL_ADDRESS);
512 inb(VGAREG_ACTL_RESET);
514 for (i=0; i<9; i++) {
515 outb(i, VGAREG_GRDC_ADDRESS);
516 outb(GET_FARVAR(seg, info->grdc_regs[i]), VGAREG_GRDC_DATA);
519 outb(GET_FARVAR(seg, info->sequ_index), VGAREG_SEQU_ADDRESS);
520 outb(GET_FARVAR(seg, info->crtc_index), crtc_addr);
521 outb(GET_FARVAR(seg, info->grdc_index), VGAREG_GRDC_ADDRESS);
522 outb(GET_FARVAR(seg, info->feature), crtc_addr - 0x4 + 0xa);
526 clear_screen(struct vgamode_s *vmode_g)
528 switch (GET_GLOBAL(vmode_g->memmodel)) {
531 memset16_far(GET_GLOBAL(vmode_g->sstart), 0, 0x0720, 32*1024);
534 memset16_far(GET_GLOBAL(vmode_g->sstart), 0, 0x0000, 32*1024);
537 // XXX - old code gets/sets/restores sequ register 2 to 0xf -
538 // but it should always be 0xf anyway.
539 memset16_far(GET_GLOBAL(vmode_g->sstart), 0, 0x0000, 64*1024);
544 stdvga_set_mode(int mode, int flags)
546 // find the entry in the video modes
547 struct vgamode_s *vmode_g = find_vga_entry(mode);
548 dprintf(1, "mode search %02x found %p\n", mode, vmode_g);
552 // if palette loading (bit 3 of modeset ctl = 0)
553 if (!(flags & MF_NOPALETTE)) { // Set the PEL mask
554 stdvga_set_pel_mask(GET_GLOBAL(vmode_g->pelmask));
556 // From which palette
557 u8 *palette_g = GET_GLOBAL(vmode_g->dac);
558 u16 palsize = GET_GLOBAL(vmode_g->dacsize) / 3;
560 // Always 256*3 values
561 stdvga_set_dac_regs(get_global_seg(), palette_g, 0, palsize);
563 for (i = palsize; i < 0x0100; i++) {
564 static u8 rgb[3] VAR16;
565 stdvga_set_dac_regs(get_global_seg(), rgb, i, 1);
568 if (flags & MF_GRAYSUM)
569 stdvga_perform_gray_scale_summing(0x00, 0x100);
572 // Reset Attribute Ctl flip-flop
573 inb(VGAREG_ACTL_RESET);
576 u8 *regs = GET_GLOBAL(vmode_g->actl_regs);
578 for (i = 0; i <= 0x13; i++) {
579 outb(i, VGAREG_ACTL_ADDRESS);
580 outb(GET_GLOBAL(regs[i]), VGAREG_ACTL_WRITE_DATA);
582 outb(0x14, VGAREG_ACTL_ADDRESS);
583 outb(0x00, VGAREG_ACTL_WRITE_DATA);
586 outb(0, VGAREG_SEQU_ADDRESS);
587 outb(0x03, VGAREG_SEQU_DATA);
588 regs = GET_GLOBAL(vmode_g->sequ_regs);
589 for (i = 1; i <= 4; i++) {
590 outb(i, VGAREG_SEQU_ADDRESS);
591 outb(GET_GLOBAL(regs[i - 1]), VGAREG_SEQU_DATA);
595 regs = GET_GLOBAL(vmode_g->grdc_regs);
596 for (i = 0; i <= 8; i++) {
597 outb(i, VGAREG_GRDC_ADDRESS);
598 outb(GET_GLOBAL(regs[i]), VGAREG_GRDC_DATA);
601 // Set CRTC address VGA or MDA
602 u8 miscreg = GET_GLOBAL(vmode_g->miscreg);
603 u16 crtc_addr = VGAREG_VGA_CRTC_ADDRESS;
605 crtc_addr = VGAREG_MDA_CRTC_ADDRESS;
607 // Disable CRTC write protection
608 outw(0x0011, crtc_addr);
610 regs = GET_GLOBAL(vmode_g->crtc_regs);
611 for (i = 0; i <= 0x18; i++) {
613 outb(GET_GLOBAL(regs[i]), crtc_addr + 1);
616 // Set the misc register
617 outb(miscreg, VGAREG_WRITE_MISC_OUTPUT);
620 outb(0x20, VGAREG_ACTL_ADDRESS);
621 inb(VGAREG_ACTL_RESET);
624 if (!(flags & MF_NOCLEARMEM))
625 clear_screen(vmode_g);
627 // Write the fonts in memory
628 u8 memmodel = GET_GLOBAL(vmode_g->memmodel);
630 stdvga_load_font(get_global_seg(), vgafont16, 0x100, 0, 0, 16);
632 // Setup BDA variables
633 modeswitch_set_bda(mode, flags, vmode_g);
637 /****************************************************************
639 ****************************************************************/
642 stdvga_enable_video_addressing(u8 disable)
644 u8 v = (disable & 1) ? 0x00 : 0x02;
645 u8 v2 = inb(VGAREG_READ_MISC_OUTPUT) & ~0x02;
646 outb(v | v2, VGAREG_WRITE_MISC_OUTPUT);
652 // switch to color mode and enable CPU access 480 lines
653 outb(0xc3, VGAREG_WRITE_MISC_OUTPUT);
654 // more than 64k 3C4/04
655 outb(0x04, VGAREG_SEQU_ADDRESS);
656 outb(0x02, VGAREG_SEQU_DATA);