3 // Copyright (C) 2009 Kevin O'Connor <kevin@koconnor.net>
4 // Copyright (C) 2001-2008 the LGPL VGABios developers Team
6 // This file may be distributed under the terms of the GNU LGPLv3 license.
8 #include "stdvga.h" // stdvga_init
9 #include "ioport.h" // outb
10 #include "farptr.h" // SET_FARVAR
11 #include "biosvar.h" // GET_GLOBAL
12 #include "util.h" // memcpy_far
13 #include "vbe.h" // VBE_RETURN_STATUS_FAILED
14 #include "vgabios.h" // find_vga_entry
17 // * replace direct in/out calls with wrapper functions
20 /****************************************************************
22 ****************************************************************/
25 stdvga_screen_disable(void)
27 inb(VGAREG_ACTL_RESET);
28 outb(0x00, VGAREG_ACTL_ADDRESS);
32 stdvga_screen_enable(void)
34 inb(VGAREG_ACTL_RESET);
35 outb(0x20, VGAREG_ACTL_ADDRESS);
39 stdvga_set_border_color(u8 color)
41 inb(VGAREG_ACTL_RESET);
42 outb(0x00, VGAREG_ACTL_ADDRESS);
46 outb(v1, VGAREG_ACTL_WRITE_DATA);
50 for (i = 1; i < 4; i++) {
51 outb(i, VGAREG_ACTL_ADDRESS);
53 u8 cur = inb(VGAREG_ACTL_READ_DATA);
56 outb(cur, VGAREG_ACTL_WRITE_DATA);
58 outb(0x20, VGAREG_ACTL_ADDRESS);
62 stdvga_set_overscan_border_color(u8 color)
64 inb(VGAREG_ACTL_RESET);
65 outb(0x11, VGAREG_ACTL_ADDRESS);
66 outb(color, VGAREG_ACTL_WRITE_DATA);
67 outb(0x20, VGAREG_ACTL_ADDRESS);
71 stdvga_get_overscan_border_color(void)
73 inb(VGAREG_ACTL_RESET);
74 outb(0x11, VGAREG_ACTL_ADDRESS);
75 u8 v = inb(VGAREG_ACTL_READ_DATA);
76 inb(VGAREG_ACTL_RESET);
77 outb(0x20, VGAREG_ACTL_ADDRESS);
82 stdvga_set_palette(u8 palid)
84 inb(VGAREG_ACTL_RESET);
87 for (i = 1; i < 4; i++) {
88 outb(i, VGAREG_ACTL_ADDRESS);
90 u8 v = inb(VGAREG_ACTL_READ_DATA);
93 outb(v, VGAREG_ACTL_WRITE_DATA);
95 outb(0x20, VGAREG_ACTL_ADDRESS);
99 stdvga_set_single_palette_reg(u8 reg, u8 val)
101 inb(VGAREG_ACTL_RESET);
102 outb(reg, VGAREG_ACTL_ADDRESS);
103 outb(val, VGAREG_ACTL_WRITE_DATA);
104 outb(0x20, VGAREG_ACTL_ADDRESS);
108 stdvga_get_single_palette_reg(u8 reg)
110 inb(VGAREG_ACTL_RESET);
111 outb(reg, VGAREG_ACTL_ADDRESS);
112 u8 v = inb(VGAREG_ACTL_READ_DATA);
113 inb(VGAREG_ACTL_RESET);
114 outb(0x20, VGAREG_ACTL_ADDRESS);
119 stdvga_set_all_palette_reg(u16 seg, u8 *data_far)
121 inb(VGAREG_ACTL_RESET);
123 for (i = 0; i < 0x10; i++) {
124 outb(i, VGAREG_ACTL_ADDRESS);
125 u8 val = GET_FARVAR(seg, *data_far);
126 outb(val, VGAREG_ACTL_WRITE_DATA);
129 outb(0x11, VGAREG_ACTL_ADDRESS);
130 outb(GET_FARVAR(seg, *data_far), VGAREG_ACTL_WRITE_DATA);
131 outb(0x20, VGAREG_ACTL_ADDRESS);
135 stdvga_get_all_palette_reg(u16 seg, u8 *data_far)
138 for (i = 0; i < 0x10; i++) {
139 inb(VGAREG_ACTL_RESET);
140 outb(i, VGAREG_ACTL_ADDRESS);
141 SET_FARVAR(seg, *data_far, inb(VGAREG_ACTL_READ_DATA));
144 inb(VGAREG_ACTL_RESET);
145 outb(0x11, VGAREG_ACTL_ADDRESS);
146 SET_FARVAR(seg, *data_far, inb(VGAREG_ACTL_READ_DATA));
147 inb(VGAREG_ACTL_RESET);
148 outb(0x20, VGAREG_ACTL_ADDRESS);
152 stdvga_toggle_intensity(u8 flag)
154 inb(VGAREG_ACTL_RESET);
155 outb(0x10, VGAREG_ACTL_ADDRESS);
156 u8 val = (inb(VGAREG_ACTL_READ_DATA) & 0xf7) | ((flag & 0x01) << 3);
157 outb(val, VGAREG_ACTL_WRITE_DATA);
158 outb(0x20, VGAREG_ACTL_ADDRESS);
162 stdvga_select_video_dac_color_page(u8 flag, u8 data)
164 inb(VGAREG_ACTL_RESET);
165 outb(0x10, VGAREG_ACTL_ADDRESS);
166 u8 val = inb(VGAREG_ACTL_READ_DATA);
167 if (!(flag & 0x01)) {
168 // select paging mode
169 val = (val & 0x7f) | (data << 7);
170 outb(val, VGAREG_ACTL_WRITE_DATA);
171 outb(0x20, VGAREG_ACTL_ADDRESS);
175 inb(VGAREG_ACTL_RESET);
176 outb(0x14, VGAREG_ACTL_ADDRESS);
180 outb(data, VGAREG_ACTL_WRITE_DATA);
181 outb(0x20, VGAREG_ACTL_ADDRESS);
185 stdvga_read_video_dac_state(u8 *pmode, u8 *curpage)
187 inb(VGAREG_ACTL_RESET);
188 outb(0x10, VGAREG_ACTL_ADDRESS);
189 u8 val1 = inb(VGAREG_ACTL_READ_DATA) >> 7;
191 inb(VGAREG_ACTL_RESET);
192 outb(0x14, VGAREG_ACTL_ADDRESS);
193 u8 val2 = inb(VGAREG_ACTL_READ_DATA) & 0x0f;
197 inb(VGAREG_ACTL_RESET);
198 outb(0x20, VGAREG_ACTL_ADDRESS);
205 /****************************************************************
207 ****************************************************************/
210 stdvga_set_dac_regs(u16 seg, u8 *data_far, u8 start, int count)
212 outb(start, VGAREG_DAC_WRITE_ADDRESS);
214 outb(GET_FARVAR(seg, *data_far), VGAREG_DAC_DATA);
216 outb(GET_FARVAR(seg, *data_far), VGAREG_DAC_DATA);
218 outb(GET_FARVAR(seg, *data_far), VGAREG_DAC_DATA);
225 stdvga_get_dac_regs(u16 seg, u8 *data_far, u8 start, int count)
227 outb(start, VGAREG_DAC_READ_ADDRESS);
229 SET_FARVAR(seg, *data_far, inb(VGAREG_DAC_DATA));
231 SET_FARVAR(seg, *data_far, inb(VGAREG_DAC_DATA));
233 SET_FARVAR(seg, *data_far, inb(VGAREG_DAC_DATA));
240 stdvga_set_pel_mask(u8 val)
242 outb(val, VGAREG_PEL_MASK);
246 stdvga_get_pel_mask(void)
248 return inb(VGAREG_PEL_MASK);
252 stdvga_save_dac_state(u16 seg, struct saveDACcolors *info)
254 /* XXX: check this */
255 SET_FARVAR(seg, info->rwmode, inb(VGAREG_DAC_STATE));
256 SET_FARVAR(seg, info->peladdr, inb(VGAREG_DAC_WRITE_ADDRESS));
257 SET_FARVAR(seg, info->pelmask, inb(VGAREG_PEL_MASK));
258 stdvga_get_dac_regs(seg, info->dac, 0, 256);
259 SET_FARVAR(seg, info->color_select, 0);
263 stdvga_restore_dac_state(u16 seg, struct saveDACcolors *info)
265 outb(GET_FARVAR(seg, info->pelmask), VGAREG_PEL_MASK);
266 stdvga_set_dac_regs(seg, info->dac, 0, 256);
267 outb(GET_FARVAR(seg, info->peladdr), VGAREG_DAC_WRITE_ADDRESS);
271 stdvga_perform_gray_scale_summing(u16 start, u16 count)
273 stdvga_screen_disable();
275 for (i = start; i < start+count; i++) {
277 stdvga_get_dac_regs(GET_SEG(SS), rgb, i, 1);
279 // intensity = ( 0.3 * Red ) + ( 0.59 * Green ) + ( 0.11 * Blue )
280 u16 intensity = ((77 * rgb[0] + 151 * rgb[1] + 28 * rgb[2]) + 0x80) >> 8;
281 if (intensity > 0x3f)
284 stdvga_set_dac_regs(GET_SEG(SS), rgb, i, 1);
286 stdvga_screen_enable();
290 /****************************************************************
292 ****************************************************************/
295 stdvga_sequ_write(u8 index, u8 value)
297 outw((value<<8) | index, VGAREG_SEQU_ADDRESS);
301 stdvga_grdc_write(u8 index, u8 value)
303 outw((value<<8) | index, VGAREG_GRDC_ADDRESS);
307 stdvga_set_text_block_specifier(u8 spec)
309 outw((spec << 8) | 0x03, VGAREG_SEQU_ADDRESS);
313 /****************************************************************
315 ****************************************************************/
318 get_font_access(void)
320 outw(0x0100, VGAREG_SEQU_ADDRESS);
321 outw(0x0402, VGAREG_SEQU_ADDRESS);
322 outw(0x0704, VGAREG_SEQU_ADDRESS);
323 outw(0x0300, VGAREG_SEQU_ADDRESS);
324 outw(0x0204, VGAREG_GRDC_ADDRESS);
325 outw(0x0005, VGAREG_GRDC_ADDRESS);
326 outw(0x0406, VGAREG_GRDC_ADDRESS);
330 release_font_access(void)
332 outw(0x0100, VGAREG_SEQU_ADDRESS);
333 outw(0x0302, VGAREG_SEQU_ADDRESS);
334 outw(0x0304, VGAREG_SEQU_ADDRESS);
335 outw(0x0300, VGAREG_SEQU_ADDRESS);
336 u16 v = (inb(VGAREG_READ_MISC_OUTPUT) & 0x01) ? 0x0e : 0x0a;
337 outw((v << 8) | 0x06, VGAREG_GRDC_ADDRESS);
338 outw(0x0004, VGAREG_GRDC_ADDRESS);
339 outw(0x1005, VGAREG_GRDC_ADDRESS);
343 stdvga_load_font(u16 seg, void *src_far, u16 count
344 , u16 start, u8 destflags, u8 fontsize)
347 u16 blockaddr = ((destflags & 0x03) << 14) + ((destflags & 0x04) << 11);
348 void *dest_far = (void*)(blockaddr + start*32);
350 for (i = 0; i < count; i++)
351 memcpy_far(SEG_GRAPH, dest_far + i*32
352 , seg, src_far + i*fontsize, fontsize);
353 release_font_access();
357 /****************************************************************
359 ****************************************************************/
362 stdvga_get_crtc(void)
364 if (inb(VGAREG_READ_MISC_OUTPUT) & 1)
365 return VGAREG_VGA_CRTC_ADDRESS;
366 return VGAREG_MDA_CRTC_ADDRESS;
370 stdvga_set_cursor_shape(u8 start, u8 end)
372 u16 crtc_addr = stdvga_get_crtc();
373 outb(0x0a, crtc_addr);
374 outb(start, crtc_addr + 1);
375 outb(0x0b, crtc_addr);
376 outb(end, crtc_addr + 1);
380 stdvga_set_active_page(u16 address)
382 u16 crtc_addr = stdvga_get_crtc();
383 outb(0x0c, crtc_addr);
384 outb((address & 0xff00) >> 8, crtc_addr + 1);
385 outb(0x0d, crtc_addr);
386 outb(address & 0x00ff, crtc_addr + 1);
390 stdvga_set_cursor_pos(u16 address)
392 u16 crtc_addr = stdvga_get_crtc();
393 outb(0x0e, crtc_addr);
394 outb((address & 0xff00) >> 8, crtc_addr + 1);
395 outb(0x0f, crtc_addr);
396 outb(address & 0x00ff, crtc_addr + 1);
400 stdvga_set_scan_lines(u8 lines)
402 u16 crtc_addr = stdvga_get_crtc();
403 outb(0x09, crtc_addr);
404 u8 crtc_r9 = inb(crtc_addr + 1);
405 crtc_r9 = (crtc_r9 & 0xe0) | (lines - 1);
406 outb(crtc_r9, crtc_addr + 1);
409 // Get vertical display end
413 u16 crtc_addr = stdvga_get_crtc();
414 outb(0x12, crtc_addr);
415 u16 vde = inb(crtc_addr + 1);
416 outb(0x07, crtc_addr);
417 u8 ovl = inb(crtc_addr + 1);
418 vde += (((ovl & 0x02) << 7) + ((ovl & 0x40) << 3) + 1);
423 /****************************************************************
424 * Save/Restore/Set state
425 ****************************************************************/
428 stdvga_save_state(u16 seg, struct saveVideoHardware *info)
430 u16 crtc_addr = stdvga_get_crtc();
431 SET_FARVAR(seg, info->sequ_index, inb(VGAREG_SEQU_ADDRESS));
432 SET_FARVAR(seg, info->crtc_index, inb(crtc_addr));
433 SET_FARVAR(seg, info->grdc_index, inb(VGAREG_GRDC_ADDRESS));
434 inb(VGAREG_ACTL_RESET);
435 u16 ar_index = inb(VGAREG_ACTL_ADDRESS);
436 SET_FARVAR(seg, info->actl_index, ar_index);
437 SET_FARVAR(seg, info->feature, inb(VGAREG_READ_FEATURE_CTL));
440 for (i=0; i<4; i++) {
441 outb(i+1, VGAREG_SEQU_ADDRESS);
442 SET_FARVAR(seg, info->sequ_regs[i], inb(VGAREG_SEQU_DATA));
444 outb(0, VGAREG_SEQU_ADDRESS);
445 SET_FARVAR(seg, info->sequ0, inb(VGAREG_SEQU_DATA));
447 for (i=0; i<25; i++) {
449 SET_FARVAR(seg, info->crtc_regs[i], inb(crtc_addr + 1));
452 for (i=0; i<20; i++) {
453 inb(VGAREG_ACTL_RESET);
454 outb(i | (ar_index & 0x20), VGAREG_ACTL_ADDRESS);
455 SET_FARVAR(seg, info->actl_regs[i], inb(VGAREG_ACTL_READ_DATA));
457 inb(VGAREG_ACTL_RESET);
459 for (i=0; i<9; i++) {
460 outb(i, VGAREG_GRDC_ADDRESS);
461 SET_FARVAR(seg, info->grdc_regs[i], inb(VGAREG_GRDC_DATA));
464 SET_FARVAR(seg, info->crtc_addr, crtc_addr);
466 /* XXX: read plane latches */
468 SET_FARVAR(seg, info->plane_latch[i], 0);
472 stdvga_restore_state(u16 seg, struct saveVideoHardware *info)
474 // Reset Attribute Ctl flip-flop
475 inb(VGAREG_ACTL_RESET);
477 u16 crtc_addr = GET_FARVAR(seg, info->crtc_addr);
480 for (i=0; i<4; i++) {
481 outb(i+1, VGAREG_SEQU_ADDRESS);
482 outb(GET_FARVAR(seg, info->sequ_regs[i]), VGAREG_SEQU_DATA);
484 outb(0, VGAREG_SEQU_ADDRESS);
485 outb(GET_FARVAR(seg, info->sequ0), VGAREG_SEQU_DATA);
487 // Disable CRTC write protection
488 outw(0x0011, crtc_addr);
493 outb(GET_FARVAR(seg, info->crtc_regs[i]), crtc_addr + 1);
495 // select crtc base address
496 u16 v = inb(VGAREG_READ_MISC_OUTPUT) & ~0x01;
497 if (crtc_addr == VGAREG_VGA_CRTC_ADDRESS)
499 outb(v, VGAREG_WRITE_MISC_OUTPUT);
501 // enable write protection if needed
502 outb(0x11, crtc_addr);
503 outb(GET_FARVAR(seg, info->crtc_regs[0x11]), crtc_addr + 1);
506 u16 ar_index = GET_FARVAR(seg, info->actl_index);
507 inb(VGAREG_ACTL_RESET);
508 for (i=0; i<20; i++) {
509 outb(i | (ar_index & 0x20), VGAREG_ACTL_ADDRESS);
510 outb(GET_FARVAR(seg, info->actl_regs[i]), VGAREG_ACTL_WRITE_DATA);
512 outb(ar_index, VGAREG_ACTL_ADDRESS);
513 inb(VGAREG_ACTL_RESET);
515 for (i=0; i<9; i++) {
516 outb(i, VGAREG_GRDC_ADDRESS);
517 outb(GET_FARVAR(seg, info->grdc_regs[i]), VGAREG_GRDC_DATA);
520 outb(GET_FARVAR(seg, info->sequ_index), VGAREG_SEQU_ADDRESS);
521 outb(GET_FARVAR(seg, info->crtc_index), crtc_addr);
522 outb(GET_FARVAR(seg, info->grdc_index), VGAREG_GRDC_ADDRESS);
523 outb(GET_FARVAR(seg, info->feature), crtc_addr - 0x4 + 0xa);
527 clear_screen(struct vgamode_s *vmode_g)
529 switch (GET_GLOBAL(vmode_g->memmodel)) {
531 memset16_far(GET_GLOBAL(vmode_g->sstart), 0, 0x0720, 32*1024);
534 memset16_far(GET_GLOBAL(vmode_g->sstart), 0, 0x0000, 32*1024);
537 // XXX - old code gets/sets/restores sequ register 2 to 0xf -
538 // but it should always be 0xf anyway.
539 memset16_far(GET_GLOBAL(vmode_g->sstart), 0, 0x0000, 64*1024);
544 stdvga_set_mode(int mode, int flags)
546 // find the entry in the video modes
547 struct vgamode_s *vmode_g = find_vga_entry(mode);
548 dprintf(1, "mode search %02x found %p\n", mode, vmode_g);
550 return VBE_RETURN_STATUS_FAILED;
552 // if palette loading (bit 3 of modeset ctl = 0)
553 if (!(flags & MF_NOPALETTE)) { // Set the PEL mask
554 stdvga_set_pel_mask(GET_GLOBAL(vmode_g->pelmask));
556 // From which palette
557 u8 *palette_g = GET_GLOBAL(vmode_g->dac);
558 u16 palsize = GET_GLOBAL(vmode_g->dacsize) / 3;
560 // Always 256*3 values
561 stdvga_set_dac_regs(get_global_seg(), palette_g, 0, palsize);
563 for (i = palsize; i < 0x0100; i++) {
564 static u8 rgb[3] VAR16;
565 stdvga_set_dac_regs(get_global_seg(), rgb, i, 1);
568 if (flags & MF_GRAYSUM)
569 stdvga_perform_gray_scale_summing(0x00, 0x100);
572 // Reset Attribute Ctl flip-flop
573 inb(VGAREG_ACTL_RESET);
576 u8 *regs = GET_GLOBAL(vmode_g->actl_regs);
578 for (i = 0; i <= 0x13; i++) {
579 outb(i, VGAREG_ACTL_ADDRESS);
580 outb(GET_GLOBAL(regs[i]), VGAREG_ACTL_WRITE_DATA);
582 outb(0x14, VGAREG_ACTL_ADDRESS);
583 outb(0x00, VGAREG_ACTL_WRITE_DATA);
586 outb(0, VGAREG_SEQU_ADDRESS);
587 outb(0x03, VGAREG_SEQU_DATA);
588 regs = GET_GLOBAL(vmode_g->sequ_regs);
589 for (i = 1; i <= 4; i++) {
590 outb(i, VGAREG_SEQU_ADDRESS);
591 outb(GET_GLOBAL(regs[i - 1]), VGAREG_SEQU_DATA);
595 regs = GET_GLOBAL(vmode_g->grdc_regs);
596 for (i = 0; i <= 8; i++) {
597 outb(i, VGAREG_GRDC_ADDRESS);
598 outb(GET_GLOBAL(regs[i]), VGAREG_GRDC_DATA);
601 // Set CRTC address VGA or MDA
602 u8 miscreg = GET_GLOBAL(vmode_g->miscreg);
603 u16 crtc_addr = VGAREG_VGA_CRTC_ADDRESS;
605 crtc_addr = VGAREG_MDA_CRTC_ADDRESS;
607 // Disable CRTC write protection
608 outw(0x0011, crtc_addr);
610 regs = GET_GLOBAL(vmode_g->crtc_regs);
611 for (i = 0; i <= 0x18; i++) {
613 outb(GET_GLOBAL(regs[i]), crtc_addr + 1);
616 // Set the misc register
617 outb(miscreg, VGAREG_WRITE_MISC_OUTPUT);
620 outb(0x20, VGAREG_ACTL_ADDRESS);
621 inb(VGAREG_ACTL_RESET);
624 if (!(flags & MF_NOCLEARMEM))
625 clear_screen(vmode_g);
627 // Write the fonts in memory
628 u8 memmodel = GET_GLOBAL(vmode_g->memmodel);
629 if (memmodel == MM_TEXT)
630 stdvga_load_font(get_global_seg(), vgafont16, 0x100, 0, 0, 16);
632 // Setup BDA variables
633 modeswitch_set_bda(mode, flags, vmode_g);
639 /****************************************************************
641 ****************************************************************/
644 stdvga_enable_video_addressing(u8 disable)
646 u8 v = (disable & 1) ? 0x00 : 0x02;
647 u8 v2 = inb(VGAREG_READ_MISC_OUTPUT) & ~0x02;
648 outb(v | v2, VGAREG_WRITE_MISC_OUTPUT);
654 // switch to color mode and enable CPU access 480 lines
655 outb(0xc3, VGAREG_WRITE_MISC_OUTPUT);
656 // more than 64k 3C4/04
657 outb(0x04, VGAREG_SEQU_ADDRESS);
658 outb(0x02, VGAREG_SEQU_DATA);