1 // Standard VGA driver code
3 // Copyright (C) 2009 Kevin O'Connor <kevin@koconnor.net>
4 // Copyright (C) 2001-2008 the LGPL VGABios developers Team
6 // This file may be distributed under the terms of the GNU LGPLv3 license.
8 #include "vgabios.h" // struct vgamode_s
9 #include "stdvga.h" // stdvga_init
10 #include "ioport.h" // outb
11 #include "farptr.h" // SET_FARVAR
12 #include "biosvar.h" // GET_GLOBAL
13 #include "util.h" // memcpy_far
16 /****************************************************************
18 ****************************************************************/
21 stdvga_set_border_color(u8 color)
26 stdvga_attr_write(0x00, v1);
29 for (i = 1; i < 4; i++)
30 stdvga_attr_mask(i, 0x10, color & 0x10);
34 stdvga_set_overscan_border_color(u8 color)
36 stdvga_attr_write(0x11, color);
40 stdvga_get_overscan_border_color(void)
42 return stdvga_attr_read(0x11);
46 stdvga_set_palette(u8 palid)
49 for (i = 1; i < 4; i++)
50 stdvga_attr_mask(i, 0x01, palid & 0x01);
54 stdvga_set_all_palette_reg(u16 seg, u8 *data_far)
57 for (i = 0; i < 0x10; i++) {
58 stdvga_attr_write(i, GET_FARVAR(seg, *data_far));
61 stdvga_attr_write(0x11, GET_FARVAR(seg, *data_far));
65 stdvga_get_all_palette_reg(u16 seg, u8 *data_far)
68 for (i = 0; i < 0x10; i++) {
69 SET_FARVAR(seg, *data_far, stdvga_attr_read(i));
72 SET_FARVAR(seg, *data_far, stdvga_attr_read(0x11));
76 stdvga_toggle_intensity(u8 flag)
78 stdvga_attr_mask(0x10, 0x08, (flag & 0x01) << 3);
82 stdvga_select_video_dac_color_page(u8 flag, u8 data)
86 stdvga_attr_mask(0x10, 0x80, data << 7);
90 u8 val = stdvga_attr_read(0x10);
94 stdvga_attr_write(0x14, data);
98 stdvga_read_video_dac_state(u8 *pmode, u8 *curpage)
100 u8 val1 = stdvga_attr_read(0x10) >> 7;
101 u8 val2 = stdvga_attr_read(0x14) & 0x0f;
109 /****************************************************************
111 ****************************************************************/
114 stdvga_save_dac_state(u16 seg, struct saveDACcolors *info)
116 /* XXX: check this */
117 SET_FARVAR(seg, info->rwmode, inb(VGAREG_DAC_STATE));
118 SET_FARVAR(seg, info->peladdr, inb(VGAREG_DAC_WRITE_ADDRESS));
119 SET_FARVAR(seg, info->pelmask, stdvga_pelmask_read());
120 stdvga_dac_read(seg, info->dac, 0, 256);
121 SET_FARVAR(seg, info->color_select, 0);
125 stdvga_restore_dac_state(u16 seg, struct saveDACcolors *info)
127 stdvga_pelmask_write(GET_FARVAR(seg, info->pelmask));
128 stdvga_dac_write(seg, info->dac, 0, 256);
129 outb(GET_FARVAR(seg, info->peladdr), VGAREG_DAC_WRITE_ADDRESS);
133 stdvga_perform_gray_scale_summing(u16 start, u16 count)
135 stdvga_attrindex_write(0x00);
137 for (i = start; i < start+count; i++) {
139 stdvga_dac_read(GET_SEG(SS), rgb, i, 1);
141 // intensity = ( 0.3 * Red ) + ( 0.59 * Green ) + ( 0.11 * Blue )
142 u16 intensity = ((77 * rgb[0] + 151 * rgb[1] + 28 * rgb[2]) + 0x80) >> 8;
143 if (intensity > 0x3f)
146 stdvga_dac_write(GET_SEG(SS), rgb, i, 1);
148 stdvga_attrindex_write(0x20);
152 /****************************************************************
154 ****************************************************************/
157 stdvga_set_text_block_specifier(u8 spec)
159 stdvga_sequ_write(0x03, spec);
162 // Enable reads and writes to the given "plane" when in planar4 mode.
164 stdvga_planar4_plane(int plane)
167 // Return to default mode (read plane0, write all planes)
168 stdvga_sequ_write(0x02, 0x0f);
169 stdvga_grdc_write(0x04, 0);
171 stdvga_sequ_write(0x02, 1<<plane);
172 stdvga_grdc_write(0x04, plane);
177 /****************************************************************
179 ****************************************************************/
182 get_font_access(void)
184 stdvga_sequ_write(0x00, 0x01);
185 stdvga_sequ_write(0x02, 0x04);
186 stdvga_sequ_write(0x04, 0x07);
187 stdvga_sequ_write(0x00, 0x03);
188 stdvga_grdc_write(0x04, 0x02);
189 stdvga_grdc_write(0x05, 0x00);
190 stdvga_grdc_write(0x06, 0x04);
194 release_font_access(void)
196 stdvga_sequ_write(0x00, 0x01);
197 stdvga_sequ_write(0x02, 0x03);
198 stdvga_sequ_write(0x04, 0x03);
199 stdvga_sequ_write(0x00, 0x03);
200 u16 v = (stdvga_misc_read() & 0x01) ? 0x0e : 0x0a;
201 stdvga_grdc_write(0x06, v);
202 stdvga_grdc_write(0x04, 0x00);
203 stdvga_grdc_write(0x05, 0x10);
207 stdvga_load_font(u16 seg, void *src_far, u16 count
208 , u16 start, u8 destflags, u8 fontsize)
211 u16 blockaddr = ((destflags & 0x03) << 14) + ((destflags & 0x04) << 11);
212 void *dest_far = (void*)(blockaddr + start*32);
214 for (i = 0; i < count; i++)
215 memcpy_far(SEG_GRAPH, dest_far + i*32
216 , seg, src_far + i*fontsize, fontsize);
217 release_font_access();
221 /****************************************************************
223 ****************************************************************/
226 stdvga_get_crtc(void)
228 if (stdvga_misc_read() & 1)
229 return VGAREG_VGA_CRTC_ADDRESS;
230 return VGAREG_MDA_CRTC_ADDRESS;
233 // Return the multiplication factor needed for the vga offset register.
235 stdvga_bpp_factor(struct vgamode_s *vmode_g)
237 switch (GET_GLOBAL(vmode_g->memmodel)) {
241 return GET_GLOBAL(vmode_g->depth);
250 stdvga_set_cursor_shape(u8 start, u8 end)
252 u16 crtc_addr = stdvga_get_crtc();
253 stdvga_crtc_write(crtc_addr, 0x0a, start);
254 stdvga_crtc_write(crtc_addr, 0x0b, end);
258 stdvga_set_cursor_pos(int address)
260 u16 crtc_addr = stdvga_get_crtc();
261 address /= 2; // Assume we're in text mode.
262 stdvga_crtc_write(crtc_addr, 0x0e, address >> 8);
263 stdvga_crtc_write(crtc_addr, 0x0f, address);
267 stdvga_set_scan_lines(u8 lines)
269 stdvga_crtc_mask(stdvga_get_crtc(), 0x09, 0x1f, lines - 1);
272 // Get vertical display end
276 u16 crtc_addr = stdvga_get_crtc();
277 u16 vde = stdvga_crtc_read(crtc_addr, 0x12);
278 u8 ovl = stdvga_crtc_read(crtc_addr, 0x07);
279 vde += (((ovl & 0x02) << 7) + ((ovl & 0x40) << 3) + 1);
284 stdvga_get_window(struct vgamode_s *vmode_g, int window)
290 stdvga_set_window(struct vgamode_s *vmode_g, int window, int val)
296 stdvga_get_linelength(struct vgamode_s *vmode_g)
298 u8 val = stdvga_crtc_read(stdvga_get_crtc(), 0x13);
299 return val * stdvga_bpp_factor(vmode_g) * 2;
303 stdvga_set_linelength(struct vgamode_s *vmode_g, int val)
305 int factor = stdvga_bpp_factor(vmode_g) * 2;
306 stdvga_crtc_write(stdvga_get_crtc(), 0x13, DIV_ROUND_UP(val, factor));
311 stdvga_get_displaystart(struct vgamode_s *vmode_g)
313 u16 crtc_addr = stdvga_get_crtc();
314 int addr = (stdvga_crtc_read(crtc_addr, 0x0c) << 8
315 | stdvga_crtc_read(crtc_addr, 0x0d));
316 return addr * stdvga_bpp_factor(vmode_g);
320 stdvga_set_displaystart(struct vgamode_s *vmode_g, int val)
322 u16 crtc_addr = stdvga_get_crtc();
323 val /= stdvga_bpp_factor(vmode_g);
324 stdvga_crtc_write(crtc_addr, 0x0c, val >> 8);
325 stdvga_crtc_write(crtc_addr, 0x0d, val);
330 stdvga_get_dacformat(struct vgamode_s *vmode_g)
336 stdvga_set_dacformat(struct vgamode_s *vmode_g, int val)
342 /****************************************************************
344 ****************************************************************/
347 stdvga_save_state(u16 seg, struct saveVideoHardware *info)
349 u16 crtc_addr = stdvga_get_crtc();
350 SET_FARVAR(seg, info->sequ_index, inb(VGAREG_SEQU_ADDRESS));
351 SET_FARVAR(seg, info->crtc_index, inb(crtc_addr));
352 SET_FARVAR(seg, info->grdc_index, inb(VGAREG_GRDC_ADDRESS));
353 SET_FARVAR(seg, info->actl_index, stdvga_attrindex_read());
354 SET_FARVAR(seg, info->feature, inb(VGAREG_READ_FEATURE_CTL));
358 SET_FARVAR(seg, info->sequ_regs[i], stdvga_sequ_read(i+1));
359 SET_FARVAR(seg, info->sequ0, stdvga_sequ_read(0));
362 SET_FARVAR(seg, info->crtc_regs[i], stdvga_crtc_read(crtc_addr, i));
365 SET_FARVAR(seg, info->actl_regs[i], stdvga_attr_read(i));
368 SET_FARVAR(seg, info->grdc_regs[i], stdvga_grdc_read(i));
370 SET_FARVAR(seg, info->crtc_addr, crtc_addr);
372 /* XXX: read plane latches */
374 SET_FARVAR(seg, info->plane_latch[i], 0);
378 stdvga_restore_state(u16 seg, struct saveVideoHardware *info)
382 stdvga_sequ_write(i+1, GET_FARVAR(seg, info->sequ_regs[i]));
383 stdvga_sequ_write(0x00, GET_FARVAR(seg, info->sequ0));
385 // Disable CRTC write protection
386 u16 crtc_addr = GET_FARVAR(seg, info->crtc_addr);
387 stdvga_crtc_write(crtc_addr, 0x11, 0x00);
391 stdvga_crtc_write(crtc_addr, i, GET_FARVAR(seg, info->crtc_regs[i]));
392 // select crtc base address
393 stdvga_misc_mask(0x01, crtc_addr == VGAREG_VGA_CRTC_ADDRESS ? 0x01 : 0x00);
395 // enable write protection if needed
396 stdvga_crtc_write(crtc_addr, 0x11, GET_FARVAR(seg, info->crtc_regs[0x11]));
400 stdvga_attr_write(i, GET_FARVAR(seg, info->actl_regs[i]));
401 stdvga_attrindex_write(GET_FARVAR(seg, info->actl_index));
404 stdvga_grdc_write(i, GET_FARVAR(seg, info->grdc_regs[i]));
406 outb(GET_FARVAR(seg, info->sequ_index), VGAREG_SEQU_ADDRESS);
407 outb(GET_FARVAR(seg, info->crtc_index), crtc_addr);
408 outb(GET_FARVAR(seg, info->grdc_index), VGAREG_GRDC_ADDRESS);
409 outb(GET_FARVAR(seg, info->feature), crtc_addr - 0x4 + 0xa);
413 /****************************************************************
415 ****************************************************************/
418 stdvga_enable_video_addressing(u8 disable)
420 u8 v = (disable & 1) ? 0x00 : 0x02;
421 stdvga_misc_mask(0x02, v);
427 // switch to color mode and enable CPU access 480 lines
428 stdvga_misc_write(0xc3);
429 // more than 64k 3C4/04
430 stdvga_sequ_write(0x04, 0x02);