1 // Standard VGA driver code
3 // Copyright (C) 2009 Kevin O'Connor <kevin@koconnor.net>
4 // Copyright (C) 2001-2008 the LGPL VGABios developers Team
6 // This file may be distributed under the terms of the GNU LGPLv3 license.
8 #include "stdvga.h" // stdvga_init
9 #include "ioport.h" // outb
10 #include "farptr.h" // SET_FARVAR
11 #include "biosvar.h" // GET_GLOBAL
12 #include "util.h" // memcpy_far
13 #include "vbe.h" // VBE_RETURN_STATUS_FAILED
16 /****************************************************************
18 ****************************************************************/
21 stdvga_set_border_color(u8 color)
26 stdvga_attr_write(0x00, v1);
29 for (i = 1; i < 4; i++)
30 stdvga_attr_mask(i, 0x10, color & 0x10);
34 stdvga_set_overscan_border_color(u8 color)
36 stdvga_attr_write(0x11, color);
40 stdvga_get_overscan_border_color(void)
42 return stdvga_attr_read(0x11);
46 stdvga_set_palette(u8 palid)
49 for (i = 1; i < 4; i++)
50 stdvga_attr_mask(i, 0x01, palid & 0x01);
54 stdvga_set_all_palette_reg(u16 seg, u8 *data_far)
57 for (i = 0; i < 0x10; i++) {
58 stdvga_attr_write(i, GET_FARVAR(seg, *data_far));
61 stdvga_attr_write(0x11, GET_FARVAR(seg, *data_far));
65 stdvga_get_all_palette_reg(u16 seg, u8 *data_far)
68 for (i = 0; i < 0x10; i++) {
69 SET_FARVAR(seg, *data_far, stdvga_attr_read(i));
72 SET_FARVAR(seg, *data_far, stdvga_attr_read(0x11));
76 stdvga_toggle_intensity(u8 flag)
78 stdvga_attr_mask(0x10, 0x08, (flag & 0x01) << 3);
82 stdvga_select_video_dac_color_page(u8 flag, u8 data)
86 stdvga_attr_mask(0x10, 0x80, data << 7);
90 u8 val = stdvga_attr_read(0x10);
94 stdvga_attr_write(0x14, data);
98 stdvga_read_video_dac_state(u8 *pmode, u8 *curpage)
100 u8 val1 = stdvga_attr_read(0x10) >> 7;
101 u8 val2 = stdvga_attr_read(0x14) & 0x0f;
109 /****************************************************************
111 ****************************************************************/
114 stdvga_save_dac_state(u16 seg, struct saveDACcolors *info)
116 /* XXX: check this */
117 SET_FARVAR(seg, info->rwmode, inb(VGAREG_DAC_STATE));
118 SET_FARVAR(seg, info->peladdr, inb(VGAREG_DAC_WRITE_ADDRESS));
119 SET_FARVAR(seg, info->pelmask, stdvga_pelmask_read());
120 stdvga_dac_read(seg, info->dac, 0, 256);
121 SET_FARVAR(seg, info->color_select, 0);
125 stdvga_restore_dac_state(u16 seg, struct saveDACcolors *info)
127 stdvga_pelmask_write(GET_FARVAR(seg, info->pelmask));
128 stdvga_dac_write(seg, info->dac, 0, 256);
129 outb(GET_FARVAR(seg, info->peladdr), VGAREG_DAC_WRITE_ADDRESS);
133 stdvga_perform_gray_scale_summing(u16 start, u16 count)
135 stdvga_attrindex_write(0x00);
137 for (i = start; i < start+count; i++) {
139 stdvga_dac_read(GET_SEG(SS), rgb, i, 1);
141 // intensity = ( 0.3 * Red ) + ( 0.59 * Green ) + ( 0.11 * Blue )
142 u16 intensity = ((77 * rgb[0] + 151 * rgb[1] + 28 * rgb[2]) + 0x80) >> 8;
143 if (intensity > 0x3f)
146 stdvga_dac_write(GET_SEG(SS), rgb, i, 1);
148 stdvga_attrindex_write(0x20);
152 /****************************************************************
154 ****************************************************************/
157 stdvga_set_text_block_specifier(u8 spec)
159 stdvga_sequ_write(0x03, spec);
162 // Enable reads and writes to the given "plane" when in planar4 mode.
164 stdvga_planar4_plane(int plane)
167 // Return to default mode (read plane0, write all planes)
168 stdvga_sequ_write(0x02, 0x0f);
169 stdvga_grdc_write(0x04, 0);
171 stdvga_sequ_write(0x02, 1<<plane);
172 stdvga_grdc_write(0x04, plane);
177 /****************************************************************
179 ****************************************************************/
182 get_font_access(void)
184 stdvga_sequ_write(0x00, 0x01);
185 stdvga_sequ_write(0x02, 0x04);
186 stdvga_sequ_write(0x04, 0x07);
187 stdvga_sequ_write(0x00, 0x03);
188 stdvga_grdc_write(0x04, 0x02);
189 stdvga_grdc_write(0x05, 0x00);
190 stdvga_grdc_write(0x06, 0x04);
194 release_font_access(void)
196 stdvga_sequ_write(0x00, 0x01);
197 stdvga_sequ_write(0x02, 0x03);
198 stdvga_sequ_write(0x04, 0x03);
199 stdvga_sequ_write(0x00, 0x03);
200 u16 v = (stdvga_misc_read() & 0x01) ? 0x0e : 0x0a;
201 stdvga_grdc_write(0x06, v);
202 stdvga_grdc_write(0x04, 0x00);
203 stdvga_grdc_write(0x05, 0x10);
207 stdvga_load_font(u16 seg, void *src_far, u16 count
208 , u16 start, u8 destflags, u8 fontsize)
211 u16 blockaddr = ((destflags & 0x03) << 14) + ((destflags & 0x04) << 11);
212 void *dest_far = (void*)(blockaddr + start*32);
214 for (i = 0; i < count; i++)
215 memcpy_far(SEG_GRAPH, dest_far + i*32
216 , seg, src_far + i*fontsize, fontsize);
217 release_font_access();
221 /****************************************************************
223 ****************************************************************/
226 stdvga_get_crtc(void)
228 if (stdvga_misc_read() & 1)
229 return VGAREG_VGA_CRTC_ADDRESS;
230 return VGAREG_MDA_CRTC_ADDRESS;
234 stdvga_set_cursor_shape(u8 start, u8 end)
236 u16 crtc_addr = stdvga_get_crtc();
237 stdvga_crtc_write(crtc_addr, 0x0a, start);
238 stdvga_crtc_write(crtc_addr, 0x0b, end);
242 stdvga_set_active_page(u16 address)
244 u16 crtc_addr = stdvga_get_crtc();
245 stdvga_crtc_write(crtc_addr, 0x0c, address >> 8);
246 stdvga_crtc_write(crtc_addr, 0x0d, address);
250 stdvga_set_cursor_pos(u16 address)
252 u16 crtc_addr = stdvga_get_crtc();
253 stdvga_crtc_write(crtc_addr, 0x0e, address >> 8);
254 stdvga_crtc_write(crtc_addr, 0x0f, address);
258 stdvga_set_scan_lines(u8 lines)
260 stdvga_crtc_mask(stdvga_get_crtc(), 0x09, 0x1f, lines - 1);
263 // Get vertical display end
267 u16 crtc_addr = stdvga_get_crtc();
268 u16 vde = stdvga_crtc_read(crtc_addr, 0x12);
269 u8 ovl = stdvga_crtc_read(crtc_addr, 0x07);
270 vde += (((ovl & 0x02) << 7) + ((ovl & 0x40) << 3) + 1);
275 /****************************************************************
276 * Save/Restore/Set state
277 ****************************************************************/
280 stdvga_save_state(u16 seg, struct saveVideoHardware *info)
282 u16 crtc_addr = stdvga_get_crtc();
283 SET_FARVAR(seg, info->sequ_index, inb(VGAREG_SEQU_ADDRESS));
284 SET_FARVAR(seg, info->crtc_index, inb(crtc_addr));
285 SET_FARVAR(seg, info->grdc_index, inb(VGAREG_GRDC_ADDRESS));
286 SET_FARVAR(seg, info->actl_index, stdvga_attrindex_read());
287 SET_FARVAR(seg, info->feature, inb(VGAREG_READ_FEATURE_CTL));
291 SET_FARVAR(seg, info->sequ_regs[i], stdvga_sequ_read(i+1));
292 SET_FARVAR(seg, info->sequ0, stdvga_sequ_read(0));
295 SET_FARVAR(seg, info->crtc_regs[i], stdvga_crtc_read(crtc_addr, i));
298 SET_FARVAR(seg, info->actl_regs[i], stdvga_attr_read(i));
301 SET_FARVAR(seg, info->grdc_regs[i], stdvga_grdc_read(i));
303 SET_FARVAR(seg, info->crtc_addr, crtc_addr);
305 /* XXX: read plane latches */
307 SET_FARVAR(seg, info->plane_latch[i], 0);
311 stdvga_restore_state(u16 seg, struct saveVideoHardware *info)
315 stdvga_sequ_write(i+1, GET_FARVAR(seg, info->sequ_regs[i]));
316 stdvga_sequ_write(0x00, GET_FARVAR(seg, info->sequ0));
318 // Disable CRTC write protection
319 u16 crtc_addr = GET_FARVAR(seg, info->crtc_addr);
320 stdvga_crtc_write(crtc_addr, 0x11, 0x00);
324 stdvga_crtc_write(crtc_addr, i, GET_FARVAR(seg, info->crtc_regs[i]));
325 // select crtc base address
326 stdvga_misc_mask(0x01, crtc_addr == VGAREG_VGA_CRTC_ADDRESS ? 0x01 : 0x00);
328 // enable write protection if needed
329 stdvga_crtc_write(crtc_addr, 0x11, GET_FARVAR(seg, info->crtc_regs[0x11]));
333 stdvga_attr_write(i, GET_FARVAR(seg, info->actl_regs[i]));
334 stdvga_attrindex_write(GET_FARVAR(seg, info->actl_index));
337 stdvga_grdc_write(i, GET_FARVAR(seg, info->grdc_regs[i]));
339 outb(GET_FARVAR(seg, info->sequ_index), VGAREG_SEQU_ADDRESS);
340 outb(GET_FARVAR(seg, info->crtc_index), crtc_addr);
341 outb(GET_FARVAR(seg, info->grdc_index), VGAREG_GRDC_ADDRESS);
342 outb(GET_FARVAR(seg, info->feature), crtc_addr - 0x4 + 0xa);
346 clear_screen(struct vgamode_s *vmode_g)
348 switch (GET_GLOBAL(vmode_g->memmodel)) {
350 memset16_far(GET_GLOBAL(vmode_g->sstart), 0, 0x0720, 32*1024);
353 memset16_far(GET_GLOBAL(vmode_g->sstart), 0, 0x0000, 32*1024);
356 // XXX - old code gets/sets/restores sequ register 2 to 0xf -
357 // but it should always be 0xf anyway.
358 memset16_far(GET_GLOBAL(vmode_g->sstart), 0, 0x0000, 64*1024);
363 stdvga_set_mode(int mode, int flags)
365 // find the entry in the video modes
366 struct vgamode_s *vmode_g = stdvga_find_mode(mode);
367 dprintf(1, "mode search %02x found %p\n", mode, vmode_g);
369 return VBE_RETURN_STATUS_FAILED;
370 struct stdvga_mode_s *stdmode_g = container_of(
371 vmode_g, struct stdvga_mode_s, info);
373 // if palette loading (bit 3 of modeset ctl = 0)
374 if (!(flags & MF_NOPALETTE)) { // Set the PEL mask
375 stdvga_pelmask_write(GET_GLOBAL(stdmode_g->pelmask));
377 // From which palette
378 u8 *palette_g = GET_GLOBAL(stdmode_g->dac);
379 u16 palsize = GET_GLOBAL(stdmode_g->dacsize) / 3;
381 // Always 256*3 values
382 stdvga_dac_write(get_global_seg(), palette_g, 0, palsize);
384 for (i = palsize; i < 0x0100; i++) {
385 static u8 rgb[3] VAR16;
386 stdvga_dac_write(get_global_seg(), rgb, i, 1);
389 if (flags & MF_GRAYSUM)
390 stdvga_perform_gray_scale_summing(0x00, 0x100);
394 u8 *regs = GET_GLOBAL(stdmode_g->actl_regs);
396 for (i = 0; i <= 0x13; i++)
397 stdvga_attr_write(i, GET_GLOBAL(regs[i]));
398 stdvga_attr_write(0x14, 0x00);
401 stdvga_sequ_write(0x00, 0x03);
402 regs = GET_GLOBAL(stdmode_g->sequ_regs);
403 for (i = 1; i <= 4; i++)
404 stdvga_sequ_write(i, GET_GLOBAL(regs[i - 1]));
407 regs = GET_GLOBAL(stdmode_g->grdc_regs);
408 for (i = 0; i <= 8; i++)
409 stdvga_grdc_write(i, GET_GLOBAL(regs[i]));
411 // Set CRTC address VGA or MDA
412 u8 miscreg = GET_GLOBAL(stdmode_g->miscreg);
413 u16 crtc_addr = VGAREG_VGA_CRTC_ADDRESS;
415 crtc_addr = VGAREG_MDA_CRTC_ADDRESS;
417 // Disable CRTC write protection
418 stdvga_crtc_write(crtc_addr, 0x11, 0x00);
420 regs = GET_GLOBAL(stdmode_g->crtc_regs);
421 for (i = 0; i <= 0x18; i++)
422 stdvga_crtc_write(crtc_addr, i, GET_GLOBAL(regs[i]));
424 // Set the misc register
425 stdvga_misc_write(miscreg);
428 stdvga_attrindex_write(0x20);
431 if (!(flags & MF_NOCLEARMEM))
432 clear_screen(vmode_g);
434 // Write the fonts in memory
435 u8 memmodel = GET_GLOBAL(vmode_g->memmodel);
436 if (memmodel == MM_TEXT)
437 stdvga_load_font(get_global_seg(), vgafont16, 0x100, 0, 0, 16);
439 // Setup BDA variables
440 modeswitch_set_bda(mode, flags, vmode_g);
446 /****************************************************************
448 ****************************************************************/
451 stdvga_list_modes(u16 seg, u16 *dest, u16 *last)
453 SET_FARVAR(seg, *dest, 0xffff);
457 stdvga_enable_video_addressing(u8 disable)
459 u8 v = (disable & 1) ? 0x00 : 0x02;
460 stdvga_misc_mask(0x02, v);
466 // switch to color mode and enable CPU access 480 lines
467 stdvga_misc_write(0xc3);
468 // more than 64k 3C4/04
469 stdvga_sequ_write(0x04, 0x02);