vgabios: Merge support for GeodeLX vga bios.
[seabios.git] / vgasrc / geodelx.h
1 // Geode LX VGA functions
2 //
3 // Copyright (C) 2009 Chris Kindt
4 //
5 // Writen for Google Summer of Code 2009 for the coreboot project
6 //
7 // This file may be distributed under the terms of the GNU LGPLv3 license.
8
9 #ifndef  GEODELX_H
10 #define  GEODELX_H
11
12 #define VRC_INDEX                       0xAC1C  // Index register
13 #define VRC_DATA                        0xAC1E  // Data register
14 #define VR_UNLOCK                       0xFC53  // Virtual register unlock code
15
16 #define EXTENDED_REGISTER_LOCK          0x30
17 #define EXTENDED_MODE_CONTROL           0x43
18 #define EXTENDED_START_ADDR             0x44
19
20 #define CRTCE_UNLOCK                    0x4c
21 #define CRTCE_LOCK                      0xff
22
23 // Graphics-specific registers:
24 #define OEM_BAR0                        0x50
25 #define OEM_BAR1                        0x54
26 #define OEM_BAR2                        0x58
27 #define OEM_BAR3                        0x5C
28
29 #define LX_PCI_ADDR                     0x80000900
30 #define LX_PCI_CMD                      (LX_PCI_ADDR + 0x04)
31 #define LX_PCI_FB                       (LX_PCI_ADDR + 0x10)
32 #define LX_PCI_DC                       (LX_PCI_ADDR + 0x18)
33 #define LX_PCI_VP                       (LX_PCI_ADDR + 0x1c)
34
35 #define DC_LOCK_LOCK                    0x00000000
36 #define DC_LOCK_UNLOCK                  0x00004758
37
38 /* LX MSRs */
39 #define MSR_GLIU0                       (1 << 28)
40 #define MSR_GLIU0_BASE4                 (MSR_GLIU0 + 0x23)
41 #define GLIU0_IOD_BM_0                  (MSR_GLIU0 + 0xE0)
42 #define GLIU0_IOD_BM_1                  (MSR_GLIU0 + 0xE1)
43 #define DC_SPARE                        0x80000011
44 #define VP_MSR_CONFIG                   0x48002001
45
46 /* DC REG OFFSET */
47 #define DC_UNLOCK                       0x0
48 #define DC_GENERAL_CFG                  0x4
49 #define DC_DISPLAY_CFG                  0x8
50 #define DC_ARB_CFG                      0xc
51 #define DC_FB_ST_OFFSET                 0x10
52 #define DC_CB_ST_OFFSET                 0x14
53 #define DC_CURS_ST_OFFSET               0x18
54 #define DC_GLIU0_MEM_OFFSET             0x84
55
56 /* VP REG OFFSET */
57 #define VP_VCFG                         0x0
58 #define VP_DCFG                         0x8
59 #define VP_MISC                         0x50
60
61
62 /* DC bits */
63 #define DC_VGAE                         (1 << 7)
64 #define DC_GDEN                         (1 << 3)
65 #define DC_TRUP                         (1 << 6)
66
67 /* VP bits */
68 #define VP_CRT_EN                       (1 << 0)
69 #define VP_HSYNC_EN                     (1 << 1)
70 #define VP_VSYNC_EN                     (1 << 2)
71 #define VP_DAC_BL_EN                    (1 << 3)
72 #define VP_CRT_SKEW                     (1 << 16)
73 #define VP_BYP_BOTH                     (1 << 0)
74
75 /* Masks */
76 #define VP_MSR_CFG_MSK                  0x0
77 #define DC_CFG_MSK                      0xf000a6
78
79 int geodelx_init();
80
81 #endif