1 // QEMU Cirrus CLGD 54xx VGABIOS Extension.
3 // Copyright (C) 2009 Kevin O'Connor <kevin@koconnor.net>
4 // Copyright (c) 2004 Makoto Suzuki (suzu)
6 // This file may be distributed under the terms of the GNU LGPLv3 license.
8 #include "clext.h" // clext_init
9 #include "vgabios.h" // VBE_VENDOR_STRING
10 #include "biosvar.h" // GET_GLOBAL
11 #include "util.h" // dprintf
12 #include "bregs.h" // struct bregs
13 #include "vbe.h" // struct vbe_info
14 #include "stdvga.h" // VGAREG_SEQU_ADDRESS
15 #include "pci.h" // pci_config_readl
16 #include "pci_regs.h" // PCI_BASE_ADDRESS_0
19 /****************************************************************
21 ****************************************************************/
24 static u16 cseq_vga[] VAR16 = {0x0007,0xffff};
25 static u16 cgraph_vga[] VAR16 = {0x0009,0x000a,0x000b,0xffff};
26 static u16 ccrtc_vga[] VAR16 = {0x001a,0x001b,0x001d,0xffff};
29 static u16 cgraph_svgacolor[] VAR16 = {
30 0x0000,0x0001,0x0002,0x0003,0x0004,0x4005,0x0506,0x0f07,0xff08,
35 static u16 cseq_640x480x8[] VAR16 = {
36 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
37 0x580b,0x580c,0x580d,0x580e,
39 0x331b,0x331c,0x331d,0x331e,
42 static u16 ccrtc_640x480x8[] VAR16 = {
44 0x5f00,0x4f01,0x4f02,0x8003,0x5204,0x1e05,0x0b06,0x3e07,
46 0xea10,0xdf12,0x5013,0x4014,0xdf15,0x0b16,0xc317,0xff18,
51 static u16 cseq_640x480x16[] VAR16 = {
52 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1707,
53 0x580b,0x580c,0x580d,0x580e,
55 0x331b,0x331c,0x331d,0x331e,
58 static u16 ccrtc_640x480x16[] VAR16 = {
60 0x5f00,0x4f01,0x4f02,0x8003,0x5204,0x1e05,0x0b06,0x3e07,
62 0xea10,0xdf12,0xa013,0x4014,0xdf15,0x0b16,0xc317,0xff18,
67 static u16 cseq_640x480x24[] VAR16 = {
68 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1507,
69 0x580b,0x580c,0x580d,0x580e,
71 0x331b,0x331c,0x331d,0x331e,
74 static u16 ccrtc_640x480x24[] VAR16 = {
76 0x5f00,0x4f01,0x4f02,0x8003,0x5204,0x1e05,0x0b06,0x3e07,
78 0xea10,0xdf12,0xf013,0x4014,0xdf15,0x0b16,0xc317,0xff18,
83 static u16 cseq_800x600x8[] VAR16 = {
84 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
85 0x230b,0x230c,0x230d,0x230e,
87 0x141b,0x141c,0x141d,0x141e,
90 static u16 ccrtc_800x600x8[] VAR16 = {
91 0x2311,0x7d00,0x6301,0x6302,0x8003,0x6b04,0x1a05,0x9806,0xf007,
93 0x7d10,0x5712,0x6413,0x4014,0x5715,0x9816,0xc317,0xff18,
98 static u16 cseq_800x600x16[] VAR16 = {
99 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1707,
100 0x230b,0x230c,0x230d,0x230e,
101 0x0412,0x0013,0x2017,
102 0x141b,0x141c,0x141d,0x141e,
105 static u16 ccrtc_800x600x16[] VAR16 = {
106 0x2311,0x7d00,0x6301,0x6302,0x8003,0x6b04,0x1a05,0x9806,0xf007,
107 0x6009,0x000c,0x000d,
108 0x7d10,0x5712,0xc813,0x4014,0x5715,0x9816,0xc317,0xff18,
109 0x001a,0x221b,0x001d,
113 static u16 cseq_800x600x24[] VAR16 = {
114 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1507,
115 0x230b,0x230c,0x230d,0x230e,
116 0x0412,0x0013,0x2017,
117 0x141b,0x141c,0x141d,0x141e,
120 static u16 ccrtc_800x600x24[] VAR16 = {
121 0x2311,0x7d00,0x6301,0x6302,0x8003,0x6b04,0x1a05,0x9806,0xf007,
122 0x6009,0x000c,0x000d,
123 0x7d10,0x5712,0x2c13,0x4014,0x5715,0x9816,0xc317,0xff18,
124 0x001a,0x321b,0x001d,
128 static u16 cseq_1024x768x8[] VAR16 = {
129 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
130 0x760b,0x760c,0x760d,0x760e,
131 0x0412,0x0013,0x2017,
132 0x341b,0x341c,0x341d,0x341e,
135 static u16 ccrtc_1024x768x8[] VAR16 = {
136 0x2911,0xa300,0x7f01,0x7f02,0x8603,0x8304,0x9405,0x2406,0xf507,
137 0x6009,0x000c,0x000d,
138 0x0310,0xff12,0x8013,0x4014,0xff15,0x2416,0xc317,0xff18,
139 0x001a,0x221b,0x001d,
143 static u16 cseq_1024x768x16[] VAR16 = {
144 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1707,
145 0x760b,0x760c,0x760d,0x760e,
146 0x0412,0x0013,0x2017,
147 0x341b,0x341c,0x341d,0x341e,
150 static u16 ccrtc_1024x768x16[] VAR16 = {
151 0x2911,0xa300,0x7f01,0x7f02,0x8603,0x8304,0x9405,0x2406,0xf507,
152 0x6009,0x000c,0x000d,
153 0x0310,0xff12,0x0013,0x4014,0xff15,0x2416,0xc317,0xff18,
154 0x001a,0x321b,0x001d,
158 static u16 cseq_1024x768x24[] VAR16 = {
159 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1507,
160 0x760b,0x760c,0x760d,0x760e,
161 0x0412,0x0013,0x2017,
162 0x341b,0x341c,0x341d,0x341e,
165 static u16 ccrtc_1024x768x24[] VAR16 = {
166 0x2911,0xa300,0x7f01,0x7f02,0x8603,0x8304,0x9405,0x2406,0xf507,
167 0x6009,0x000c,0x000d,
168 0x0310,0xff12,0x8013,0x4014,0xff15,0x2416,0xc317,0xff18,
169 0x001a,0x321b,0x001d,
173 static u16 cseq_1280x1024x8[] VAR16 = {
174 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
175 0x760b,0x760c,0x760d,0x760e,
176 0x0412,0x0013,0x2017,
177 0x341b,0x341c,0x341d,0x341e,
180 static u16 ccrtc_1280x1024x8[] VAR16 = {
181 0x2911,0xc300,0x9f01,0x9f02,0x8603,0x8304,0x9405,0x2406,0xf707,
182 0x6009,0x000c,0x000d,
183 0x0310,0xff12,0xa013,0x4014,0xff15,0x2416,0xc317,0xff18,
184 0x001a,0x221b,0x001d,
188 static u16 cseq_1280x1024x16[] VAR16 = {
189 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1707,
190 0x760b,0x760c,0x760d,0x760e,
191 0x0412,0x0013,0x2017,
192 0x341b,0x341c,0x341d,0x341e,
195 static u16 ccrtc_1280x1024x16[] VAR16 = {
196 0x2911,0xc300,0x9f01,0x9f02,0x8603,0x8304,0x9405,0x2406,0xf707,
197 0x6009,0x000c,0x000d,
198 0x0310,0xff12,0x4013,0x4014,0xff15,0x2416,0xc317,0xff18,
199 0x001a,0x321b,0x001d,
204 static u16 cseq_1600x1200x8[] VAR16 = {
205 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
206 0x760b,0x760c,0x760d,0x760e,
207 0x0412,0x0013,0x2017,
208 0x341b,0x341c,0x341d,0x341e,
211 static u16 ccrtc_1600x1200x8[] VAR16 = {
212 0x2911,0xc300,0x9f01,0x9f02,0x8603,0x8304,0x9405,0x2406,0xf707,
213 0x6009,0x000c,0x000d,
214 0x0310,0xff12,0xc813,0x4014,0xff15,0x2416,0xc317,0xff18,
215 0x001a,0x221b,0x001d,
219 struct cirrus_mode_s {
221 struct vgamode_s info;
223 u16 hidden_dac; /* 0x3c6 */
224 u16 *seq; /* 0x3c4 */
225 u16 *graph; /* 0x3ce */
226 u16 *crtc; /* 0x3d4 */
229 static struct cirrus_mode_s cirrus_modes[] VAR16 = {
230 {0x5f,{MM_PACKED,640,480,8},0x00,
231 cseq_640x480x8,cgraph_svgacolor,ccrtc_640x480x8},
232 {0x64,{MM_DIRECT,640,480,16},0xe1,
233 cseq_640x480x16,cgraph_svgacolor,ccrtc_640x480x16},
234 {0x66,{MM_DIRECT,640,480,15},0xf0,
235 cseq_640x480x16,cgraph_svgacolor,ccrtc_640x480x16},
236 {0x71,{MM_DIRECT,640,480,24},0xe5,
237 cseq_640x480x24,cgraph_svgacolor,ccrtc_640x480x24},
239 {0x5c,{MM_PACKED,800,600,8},0x00,
240 cseq_800x600x8,cgraph_svgacolor,ccrtc_800x600x8},
241 {0x65,{MM_DIRECT,800,600,16},0xe1,
242 cseq_800x600x16,cgraph_svgacolor,ccrtc_800x600x16},
243 {0x67,{MM_DIRECT,800,600,15},0xf0,
244 cseq_800x600x16,cgraph_svgacolor,ccrtc_800x600x16},
246 {0x60,{MM_PACKED,1024,768,8},0x00,
247 cseq_1024x768x8,cgraph_svgacolor,ccrtc_1024x768x8},
248 {0x74,{MM_DIRECT,1024,768,16},0xe1,
249 cseq_1024x768x16,cgraph_svgacolor,ccrtc_1024x768x16},
250 {0x68,{MM_DIRECT,1024,768,15},0xf0,
251 cseq_1024x768x16,cgraph_svgacolor,ccrtc_1024x768x16},
253 {0x78,{MM_DIRECT,800,600,24},0xe5,
254 cseq_800x600x24,cgraph_svgacolor,ccrtc_800x600x24},
255 {0x79,{MM_DIRECT,1024,768,24},0xe5,
256 cseq_1024x768x24,cgraph_svgacolor,ccrtc_1024x768x24},
258 {0x6d,{MM_PACKED,1280,1024,8},0x00,
259 cseq_1280x1024x8,cgraph_svgacolor,ccrtc_1280x1024x8},
260 {0x69,{MM_DIRECT,1280,1024,15},0xf0,
261 cseq_1280x1024x16,cgraph_svgacolor,ccrtc_1280x1024x16},
262 {0x75,{MM_DIRECT,1280,1024,16},0xe1,
263 cseq_1280x1024x16,cgraph_svgacolor,ccrtc_1280x1024x16},
265 {0x7b,{MM_PACKED,1600,1200,8},0x00,
266 cseq_1600x1200x8,cgraph_svgacolor,ccrtc_1600x1200x8},
269 static struct cirrus_mode_s mode_switchback VAR16 =
270 {0xfe,{0xff},0,cseq_vga,cgraph_vga,ccrtc_vga};
274 } cirrus_vesa_modelist[] VAR16 = {
308 /****************************************************************
310 ****************************************************************/
313 cirrus_vesamode_to_mode(u16 vesamode)
316 for (i=0; i<ARRAY_SIZE(cirrus_vesa_modelist); i++)
317 if (GET_GLOBAL(cirrus_vesa_modelist[i].vesamode) == vesamode)
318 return GET_GLOBAL(cirrus_vesa_modelist[i].mode);
322 static struct cirrus_mode_s *
323 cirrus_get_modeentry(int mode)
325 int transmode = cirrus_vesamode_to_mode(mode);
328 struct cirrus_mode_s *table_g = cirrus_modes;
329 while (table_g < &cirrus_modes[ARRAY_SIZE(cirrus_modes)]) {
330 u16 tmode = GET_GLOBAL(table_g->mode);
339 clext_find_mode(int mode)
341 struct cirrus_mode_s *table_g = cirrus_get_modeentry(mode);
343 return &table_g->info;
344 return stdvga_find_mode(mode);
348 cirrus_switch_mode_setregs(u16 *data, u16 port)
351 u16 val = GET_GLOBAL(*data);
360 cirrus_switch_mode(struct cirrus_mode_s *table)
362 // Unlock cirrus special
363 stdvga_sequ_write(0x06, 0x12);
364 cirrus_switch_mode_setregs(GET_GLOBAL(table->seq), VGAREG_SEQU_ADDRESS);
365 cirrus_switch_mode_setregs(GET_GLOBAL(table->graph), VGAREG_GRDC_ADDRESS);
366 cirrus_switch_mode_setregs(GET_GLOBAL(table->crtc), stdvga_get_crtc());
368 stdvga_pelmask_write(0x00);
369 stdvga_pelmask_read();
370 stdvga_pelmask_read();
371 stdvga_pelmask_read();
372 stdvga_pelmask_read();
373 stdvga_pelmask_write(GET_GLOBAL(table->hidden_dac));
374 stdvga_pelmask_write(0xff);
376 u8 memmodel = GET_GLOBAL(table->info.memmodel);
378 if (memmodel == MM_PLANAR)
380 else if (memmodel != MM_TEXT)
382 stdvga_attr_mask(0x10, 0x01, on);
386 cirrus_get_memsize(void)
388 // get DRAM band width
389 u8 v = stdvga_sequ_read(0x0f);
390 u8 x = (v >> 3) & 0x03;
391 if (x == 0x03 && v & 0x80)
398 cirrus_enable_16k_granularity(void)
400 stdvga_grdc_mask(0x0b, 0x00, 0x20);
404 cirrus_clear_vram(u16 param)
406 cirrus_enable_16k_granularity();
407 u8 count = cirrus_get_memsize() * 4;
409 for (i=0; i<count; i++) {
410 stdvga_grdc_write(0x09, i);
411 memset16_far(SEG_GRAPH, 0, param, 16 * 1024);
413 stdvga_grdc_write(0x09, 0x00);
417 clext_set_mode(int mode, int flags)
419 dprintf(1, "cirrus mode %x\n", mode);
420 SET_BDA(vbe_mode, 0);
421 struct cirrus_mode_s *table_g = cirrus_get_modeentry(mode);
423 cirrus_switch_mode(table_g);
424 if (!(flags & MF_LINEARFB))
425 cirrus_enable_16k_granularity();
426 if (!(flags & MF_NOCLEARMEM))
427 cirrus_clear_vram(0);
428 SET_BDA(video_mode, mode);
429 SET_BDA(vbe_mode, mode | flags);
432 cirrus_switch_mode(&mode_switchback);
433 dprintf(1, "cirrus mode switch regular\n");
434 return stdvga_set_mode(mode, flags);
440 stdvga_sequ_write(0x06, 0x92);
441 return stdvga_sequ_read(0x06) == 0x12;
445 /****************************************************************
447 ****************************************************************/
450 clext_101280(struct bregs *regs)
452 u8 v = stdvga_crtc_read(stdvga_get_crtc(), 0x27);
466 clext_101281(struct bregs *regs)
473 clext_101282(struct bregs *regs)
475 regs->al = stdvga_crtc_read(stdvga_get_crtc(), 0x27) & 0x03;
480 clext_101285(struct bregs *regs)
482 regs->al = cirrus_get_memsize();
486 clext_10129a(struct bregs *regs)
492 extern void a0h_callback(void);
494 // fatal: not implemented yet
501 clext_1012a0(struct bregs *regs)
503 struct cirrus_mode_s *table_g = cirrus_get_modeentry(regs->al & 0x7f);
504 regs->ah = (table_g ? 1 : 0);
506 regs->di = regs->ds = regs->es = regs->bx = (u32)a0h_callback;
510 clext_1012a1(struct bregs *regs)
512 regs->bx = 0x0e00; // IBM 8512/8513, color
516 clext_1012a2(struct bregs *regs)
518 regs->al = 0x07; // HSync 31.5 - 64.0 kHz
522 clext_1012ae(struct bregs *regs)
524 regs->al = 0x01; // High Refresh 75Hz
528 clext_1012XX(struct bregs *regs)
534 clext_1012(struct bregs *regs)
537 case 0x80: clext_101280(regs); break;
538 case 0x81: clext_101281(regs); break;
539 case 0x82: clext_101282(regs); break;
540 case 0x85: clext_101285(regs); break;
541 case 0x9a: clext_10129a(regs); break;
542 case 0xa0: clext_1012a0(regs); break;
543 case 0xa1: clext_1012a1(regs); break;
544 case 0xa2: clext_1012a2(regs); break;
545 case 0xae: clext_1012ae(regs); break;
546 default: clext_1012XX(regs); break;
551 /****************************************************************
553 ****************************************************************/
556 clext_list_modes(u16 seg, u16 *dest, u16 *last)
559 for (i=0; i<ARRAY_SIZE(cirrus_vesa_modelist) && dest<last; i++) {
560 SET_FARVAR(seg, *dest, GET_GLOBAL(cirrus_vesa_modelist[i].vesamode));
563 stdvga_list_modes(seg, dest, last);
567 cirrus_get_bpp_bytes(void)
569 u8 v = stdvga_sequ_read(0x07) & 0x0e;
579 cirrus_set_line_offset(u16 new_line_offset)
581 new_line_offset /= 8;
582 u16 crtc_addr = stdvga_get_crtc();
583 stdvga_crtc_write(crtc_addr, 0x13, new_line_offset);
584 stdvga_crtc_mask(crtc_addr, 0x1b, 0x10, (new_line_offset & 0x100) >> 4);
588 cirrus_get_line_offset(void)
590 u16 crtc_addr = stdvga_get_crtc();
591 u8 reg13 = stdvga_crtc_read(crtc_addr, 0x13);
592 u8 reg1b = stdvga_crtc_read(crtc_addr, 0x1b);
593 return (((reg1b & 0x10) << 4) + reg13) * 8;
597 cirrus_set_start_addr(u32 addr)
599 u16 crtc_addr = stdvga_get_crtc();
600 stdvga_crtc_write(crtc_addr, 0x0d, addr);
601 stdvga_crtc_write(crtc_addr, 0x0c, addr >> 8);
602 stdvga_crtc_mask(crtc_addr, 0x1d, 0x80, (addr & 0x0800) >> 4);
603 stdvga_crtc_mask(crtc_addr, 0x1b, 0x0d
604 , ((addr & 0x0100) >> 8) | ((addr & 0x0600) >> 7));
608 cirrus_get_start_addr(void)
610 u16 crtc_addr = stdvga_get_crtc();
611 u8 b2 = stdvga_crtc_read(crtc_addr, 0x0c);
612 u8 b1 = stdvga_crtc_read(crtc_addr, 0x0d);
613 u8 b3 = stdvga_crtc_read(crtc_addr, 0x1b);
614 u8 b4 = stdvga_crtc_read(crtc_addr, 0x1d);
615 return (b1 | (b2<<8) | ((b3 & 0x01) << 16) | ((b3 & 0x0c) << 15)
616 | ((b4 & 0x80) << 12));
620 cirrus_vesa_05h(struct bregs *regs)
626 if (regs->dx >= 0x100)
628 stdvga_grdc_write(regs->bl + 9, regs->dx);
629 } else if (regs->bh == 1) {
631 regs->dx = stdvga_grdc_read(regs->bl + 9);
642 cirrus_vesa_06h(struct bregs *regs)
649 if (regs->bl == 0x00) {
650 cirrus_set_line_offset(cirrus_get_bpp_bytes() * regs->cx);
651 } else if (regs->bl == 0x02) {
652 cirrus_set_line_offset(regs->cx);
655 u32 v = cirrus_get_line_offset();
656 regs->cx = v / cirrus_get_bpp_bytes();
658 regs->dx = (cirrus_get_memsize() * 64 * 1024) / v;
663 cirrus_vesa_07h(struct bregs *regs)
665 if (regs->bl == 0x80 || regs->bl == 0x00) {
666 u32 addr = (cirrus_get_bpp_bytes() * regs->cx
667 + cirrus_get_line_offset() * regs->dx);
668 cirrus_set_start_addr(addr / 4);
669 } else if (regs->bl == 0x01) {
670 u32 addr = cirrus_get_start_addr() * 4;
671 u32 linelength = cirrus_get_line_offset();
672 regs->dx = addr / linelength;
673 regs->cx = (addr % linelength) / cirrus_get_bpp_bytes();
683 cirrus_vesa_10h(struct bregs *regs)
685 if (regs->bl == 0x00) {
690 if (regs->bl == 0x01) {
691 SET_BDA(vbe_flag, regs->bh);
695 if (regs->bl == 0x02) {
696 regs->bh = GET_BDA(vbe_flag);
704 cirrus_vesa_not_handled(struct bregs *regs)
711 cirrus_vesa(struct bregs *regs)
714 case 0x05: cirrus_vesa_05h(regs); break;
715 case 0x06: cirrus_vesa_06h(regs); break;
716 case 0x07: cirrus_vesa_07h(regs); break;
717 case 0x10: cirrus_vesa_10h(regs); break;
718 default: cirrus_vesa_not_handled(regs); break;
723 /****************************************************************
725 ****************************************************************/
730 int ret = stdvga_init();
734 dprintf(1, "cirrus init\n");
735 if (! cirrus_check())
737 dprintf(1, "cirrus init 2\n");
741 lfb_addr = (pci_config_readl(GET_GLOBAL(VgaBDF), PCI_BASE_ADDRESS_0)
742 & PCI_BASE_ADDRESS_MEM_MASK);
743 SET_VGA(VBE_framebuffer, lfb_addr);
744 u16 totalmem = cirrus_get_memsize();
745 SET_VGA(VBE_total_memory, totalmem * 64 * 1024);
746 SET_VGA(VBE_win_granularity, 16);
749 stdvga_sequ_write(0x0a, stdvga_sequ_read(0x0f) & 0x18);
751 stdvga_sequ_write(0x07, 0x00);
753 stdvga_grdc_write(0x31, 0x04);
754 stdvga_grdc_write(0x31, 0x00);