vgasrc/clext.c

   1 //  QEMU Cirrus CLGD 54xx VGABIOS Extension.
   2 //
   3 // Copyright (C) 2009  Kevin O'Connor <kevin@koconnor.net>
   4 //  Copyright (c) 2004 Makoto Suzuki (suzu)
   5 //
   6 // This file may be distributed under the terms of the GNU LGPLv3 license.
   7
   8 #include "vgatables.h" // cirrus_init
   9 #include "biosvar.h" // GET_GLOBAL
  10 #include "util.h" // dprintf
  11
  12
  13 /****************************************************************
  14  * tables
  15  ****************************************************************/
  16
  17 struct cirrus_mode_s {
  18     /* + 0 */
  19     u16 mode;
  20     u16 width;
  21     u16 height;
  22     u16 depth;
  23     /* + 8 */
  24     u16 hidden_dac; /* 0x3c6 */
  25     u16 *seq; /* 0x3c4 */
  26     u16 *graph; /* 0x3ce */
  27     u16 *crtc; /* 0x3d4 */
  28     /* +16 */
  29     u8 bitsperpixel;
  30     u8 vesacolortype;
  31     u8 vesaredmask;
  32     u8 vesaredpos;
  33     u8 vesagreenmask;
  34     u8 vesagreenpos;
  35     u8 vesabluemask;
  36     u8 vesabluepos;
  37     /* +24 */
  38     u8 vesareservedmask;
  39     u8 vesareservedpos;
  40 };
  41
  42 /* VGA */
  43 static u16 cseq_vga[] VAR16 = {0x0007,0xffff};
  44 static u16 cgraph_vga[] VAR16 = {0x0009,0x000a,0x000b,0xffff};
  45 static u16 ccrtc_vga[] VAR16 = {0x001a,0x001b,0x001d,0xffff};
  46
  47 /* extensions */
  48 static u16 cgraph_svgacolor[] VAR16 = {
  49     0x0000,0x0001,0x0002,0x0003,0x0004,0x4005,0x0506,0x0f07,0xff08,
  50     0x0009,0x000a,0x000b,
  51     0xffff
  52 };
  53 /* 640x480x8 */
  54 static u16 cseq_640x480x8[] VAR16 = {
  55     0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
  56     0x580b,0x580c,0x580d,0x580e,
  57     0x0412,0x0013,0x2017,
  58     0x331b,0x331c,0x331d,0x331e,
  59     0xffff
  60 };
  61 static u16 ccrtc_640x480x8[] VAR16 = {
  62     0x2c11,
  63     0x5f00,0x4f01,0x4f02,0x8003,0x5204,0x1e05,0x0b06,0x3e07,
  64     0x4009,0x000c,0x000d,
  65     0xea10,0xdf12,0x5013,0x4014,0xdf15,0x0b16,0xc317,0xff18,
  66     0x001a,0x221b,0x001d,
  67     0xffff
  68 };
  69 /* 640x480x16 */
  70 static u16 cseq_640x480x16[] VAR16 = {
  71     0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1707,
  72     0x580b,0x580c,0x580d,0x580e,
  73     0x0412,0x0013,0x2017,
  74     0x331b,0x331c,0x331d,0x331e,
  75     0xffff
  76 };
  77 static u16 ccrtc_640x480x16[] VAR16 = {
  78     0x2c11,
  79     0x5f00,0x4f01,0x4f02,0x8003,0x5204,0x1e05,0x0b06,0x3e07,
  80     0x4009,0x000c,0x000d,
  81     0xea10,0xdf12,0xa013,0x4014,0xdf15,0x0b16,0xc317,0xff18,
  82     0x001a,0x221b,0x001d,
  83     0xffff
  84 };
  85 /* 640x480x24 */
  86 static u16 cseq_640x480x24[] VAR16 = {
  87     0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1507,
  88     0x580b,0x580c,0x580d,0x580e,
  89     0x0412,0x0013,0x2017,
  90     0x331b,0x331c,0x331d,0x331e,
  91     0xffff
  92 };
  93 static u16 ccrtc_640x480x24[] VAR16 = {
  94     0x2c11,
  95     0x5f00,0x4f01,0x4f02,0x8003,0x5204,0x1e05,0x0b06,0x3e07,
  96     0x4009,0x000c,0x000d,
  97     0xea10,0xdf12,0x0013,0x4014,0xdf15,0x0b16,0xc317,0xff18,
  98     0x001a,0x321b,0x001d,
  99     0xffff
 100 };
 101 /* 800x600x8 */
 102 static u16 cseq_800x600x8[] VAR16 = {
 103     0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
 104     0x230b,0x230c,0x230d,0x230e,
 105     0x0412,0x0013,0x2017,
 106     0x141b,0x141c,0x141d,0x141e,
 107     0xffff
 108 };
 109 static u16 ccrtc_800x600x8[] VAR16 = {
 110     0x2311,0x7d00,0x6301,0x6302,0x8003,0x6b04,0x1a05,0x9806,0xf007,
 111     0x6009,0x000c,0x000d,
 112     0x7d10,0x5712,0x6413,0x4014,0x5715,0x9816,0xc317,0xff18,
 113     0x001a,0x221b,0x001d,
 114     0xffff
 115 };
 116 /* 800x600x16 */
 117 static u16 cseq_800x600x16[] VAR16 = {
 118     0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1707,
 119     0x230b,0x230c,0x230d,0x230e,
 120     0x0412,0x0013,0x2017,
 121     0x141b,0x141c,0x141d,0x141e,
 122     0xffff
 123 };
 124 static u16 ccrtc_800x600x16[] VAR16 = {
 125     0x2311,0x7d00,0x6301,0x6302,0x8003,0x6b04,0x1a05,0x9806,0xf007,
 126     0x6009,0x000c,0x000d,
 127     0x7d10,0x5712,0xc813,0x4014,0x5715,0x9816,0xc317,0xff18,
 128     0x001a,0x221b,0x001d,
 129     0xffff
 130 };
 131 /* 800x600x24 */
 132 static u16 cseq_800x600x24[] VAR16 = {
 133     0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1507,
 134     0x230b,0x230c,0x230d,0x230e,
 135     0x0412,0x0013,0x2017,
 136     0x141b,0x141c,0x141d,0x141e,
 137     0xffff
 138 };
 139 static u16 ccrtc_800x600x24[] VAR16 = {
 140     0x2311,0x7d00,0x6301,0x6302,0x8003,0x6b04,0x1a05,0x9806,0xf007,
 141     0x6009,0x000c,0x000d,
 142     0x7d10,0x5712,0x2c13,0x4014,0x5715,0x9816,0xc317,0xff18,
 143     0x001a,0x321b,0x001d,
 144     0xffff
 145 };
 146 /* 1024x768x8 */
 147 static u16 cseq_1024x768x8[] VAR16 = {
 148     0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
 149     0x760b,0x760c,0x760d,0x760e,
 150     0x0412,0x0013,0x2017,
 151     0x341b,0x341c,0x341d,0x341e,
 152     0xffff
 153 };
 154 static u16 ccrtc_1024x768x8[] VAR16 = {
 155     0x2911,0xa300,0x7f01,0x7f02,0x8603,0x8304,0x9405,0x2406,0xf507,
 156     0x6009,0x000c,0x000d,
 157     0x0310,0xff12,0x8013,0x4014,0xff15,0x2416,0xc317,0xff18,
 158     0x001a,0x221b,0x001d,
 159     0xffff
 160 };
 161 /* 1024x768x16 */
 162 static u16 cseq_1024x768x16[] VAR16 = {
 163     0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1707,
 164     0x760b,0x760c,0x760d,0x760e,
 165     0x0412,0x0013,0x2017,
 166     0x341b,0x341c,0x341d,0x341e,
 167     0xffff
 168 };
 169 static u16 ccrtc_1024x768x16[] VAR16 = {
 170     0x2911,0xa300,0x7f01,0x7f02,0x8603,0x8304,0x9405,0x2406,0xf507,
 171     0x6009,0x000c,0x000d,
 172     0x0310,0xff12,0x0013,0x4014,0xff15,0x2416,0xc317,0xff18,
 173     0x001a,0x321b,0x001d,
 174     0xffff
 175 };
 176 /* 1024x768x24 */
 177 static u16 cseq_1024x768x24[] VAR16 = {
 178     0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1507,
 179     0x760b,0x760c,0x760d,0x760e,
 180     0x0412,0x0013,0x2017,
 181     0x341b,0x341c,0x341d,0x341e,
 182     0xffff
 183 };
 184 static u16 ccrtc_1024x768x24[] VAR16 = {
 185     0x2911,0xa300,0x7f01,0x7f02,0x8603,0x8304,0x9405,0x2406,0xf507,
 186     0x6009,0x000c,0x000d,
 187     0x0310,0xff12,0x8013,0x4014,0xff15,0x2416,0xc317,0xff18,
 188     0x001a,0x321b,0x001d,
 189     0xffff
 190 };
 191 /* 1280x1024x8 */
 192 static u16 cseq_1280x1024x8[] VAR16 = {
 193     0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
 194     0x760b,0x760c,0x760d,0x760e,
 195     0x0412,0x0013,0x2017,
 196     0x341b,0x341c,0x341d,0x341e,
 197     0xffff
 198 };
 199 static u16 ccrtc_1280x1024x8[] VAR16 = {
 200     0x2911,0xc300,0x9f01,0x9f02,0x8603,0x8304,0x9405,0x2406,0xf707,
 201     0x6009,0x000c,0x000d,
 202     0x0310,0xff12,0xa013,0x4014,0xff15,0x2416,0xc317,0xff18,
 203     0x001a,0x221b,0x001d,
 204     0xffff
 205 };
 206 /* 1280x1024x16 */
 207 static u16 cseq_1280x1024x16[] VAR16 = {
 208     0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1707,
 209     0x760b,0x760c,0x760d,0x760e,
 210     0x0412,0x0013,0x2017,
 211     0x341b,0x341c,0x341d,0x341e,
 212     0xffff
 213 };
 214 static u16 ccrtc_1280x1024x16[] VAR16 = {
 215     0x2911,0xc300,0x9f01,0x9f02,0x8603,0x8304,0x9405,0x2406,0xf707,
 216     0x6009,0x000c,0x000d,
 217     0x0310,0xff12,0x4013,0x4014,0xff15,0x2416,0xc317,0xff18,
 218     0x001a,0x321b,0x001d,
 219     0xffff
 220 };
 221
 222 /* 1600x1200x8 */
 223 static u16 cseq_1600x1200x8[] VAR16 = {
 224     0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
 225     0x760b,0x760c,0x760d,0x760e,
 226     0x0412,0x0013,0x2017,
 227     0x341b,0x341c,0x341d,0x341e,
 228     0xffff
 229 };
 230 static u16 ccrtc_1600x1200x8[] VAR16 = {
 231     0x2911,0xc300,0x9f01,0x9f02,0x8603,0x8304,0x9405,0x2406,0xf707,
 232     0x6009,0x000c,0x000d,
 233     0x0310,0xff12,0xa013,0x4014,0xff15,0x2416,0xc317,0xff18,
 234     0x001a,0x221b,0x001d,
 235     0xffff
 236 };
 237
 238 static struct cirrus_mode_s cirrus_modes[] VAR16 = {
 239     {0x5f,640,480,8,0x00,
 240      cseq_640x480x8,cgraph_svgacolor,ccrtc_640x480x8,8,
 241      4,0,0,0,0,0,0,0,0},
 242     {0x64,640,480,16,0xe1,
 243      cseq_640x480x16,cgraph_svgacolor,ccrtc_640x480x16,16,
 244      6,5,11,6,5,5,0,0,0},
 245     {0x66,640,480,15,0xf0,
 246      cseq_640x480x16,cgraph_svgacolor,ccrtc_640x480x16,16,
 247      6,5,10,5,5,5,0,1,15},
 248     {0x71,640,480,24,0xe5,
 249      cseq_640x480x24,cgraph_svgacolor,ccrtc_640x480x24,24,
 250      6,8,16,8,8,8,0,0,0},
 251
 252     {0x5c,800,600,8,0x00,
 253      cseq_800x600x8,cgraph_svgacolor,ccrtc_800x600x8,8,
 254      4,0,0,0,0,0,0,0,0},
 255     {0x65,800,600,16,0xe1,
 256      cseq_800x600x16,cgraph_svgacolor,ccrtc_800x600x16,16,
 257      6,5,11,6,5,5,0,0,0},
 258     {0x67,800,600,15,0xf0,
 259      cseq_800x600x16,cgraph_svgacolor,ccrtc_800x600x16,16,
 260      6,5,10,5,5,5,0,1,15},
 261
 262     {0x60,1024,768,8,0x00,
 263      cseq_1024x768x8,cgraph_svgacolor,ccrtc_1024x768x8,8,
 264      4,0,0,0,0,0,0,0,0},
 265     {0x74,1024,768,16,0xe1,
 266      cseq_1024x768x16,cgraph_svgacolor,ccrtc_1024x768x16,16,
 267      6,5,11,6,5,5,0,0,0},
 268     {0x68,1024,768,15,0xf0,
 269      cseq_1024x768x16,cgraph_svgacolor,ccrtc_1024x768x16,16,
 270      6,5,10,5,5,5,0,1,15},
 271
 272     {0x78,800,600,24,0xe5,
 273      cseq_800x600x24,cgraph_svgacolor,ccrtc_800x600x24,24,
 274      6,8,16,8,8,8,0,0,0},
 275     {0x79,1024,768,24,0xe5,
 276      cseq_1024x768x24,cgraph_svgacolor,ccrtc_1024x768x24,24,
 277      6,8,16,8,8,8,0,0,0},
 278
 279     {0x6d,1280,1024,8,0x00,
 280      cseq_1280x1024x8,cgraph_svgacolor,ccrtc_1280x1024x8,8,
 281      4,0,0,0,0,0,0,0,0},
 282     {0x69,1280,1024,15,0xf0,
 283      cseq_1280x1024x16,cgraph_svgacolor,ccrtc_1280x1024x16,16,
 284      6,5,10,5,5,5,0,1,15},
 285     {0x75,1280,1024,16,0xe1,
 286      cseq_1280x1024x16,cgraph_svgacolor,ccrtc_1280x1024x16,16,
 287      6,5,11,6,5,5,0,0,0},
 288
 289     {0x7b,1600,1200,8,0x00,
 290      cseq_1600x1200x8,cgraph_svgacolor,ccrtc_1600x1200x8,8,
 291      4,0,0,0,0,0,0,0,0},
 292
 293     {0xfe,0,0,0,0,cseq_vga,cgraph_vga,ccrtc_vga,0,
 294      0xff,0,0,0,0,0,0,0,0},
 295 };
 296
 297
 298 /****************************************************************
 299  * helper functions
 300  ****************************************************************/
 301
 302 static struct cirrus_mode_s *
 303 cirrus_get_modeentry(u8 mode)
 304 {
 305     struct cirrus_mode_s *table_g = cirrus_modes;
 306     while (table_g < &cirrus_modes[ARRAY_SIZE(cirrus_modes)]) {
 307         u16 tmode = GET_GLOBAL(table_g->mode);
 308         if (tmode == mode)
 309             return table_g;
 310         table_g++;
 311     }
 312     return NULL;
 313 }
 314
 315 static void
 316 cirrus_switch_mode_setregs(u16 *data, u16 port)
 317 {
 318     for (;;) {
 319         u16 val = GET_GLOBAL(*data);
 320         if (val == 0xffff)
 321             return;
 322         outw(val, port);
 323         data++;
 324     }
 325 }
 326
 327 static u16
 328 cirrus_get_crtc(void)
 329 {
 330     if (inb(VGAREG_READ_MISC_OUTPUT) & 1)
 331         return VGAREG_VGA_CRTC_ADDRESS;
 332     return VGAREG_MDA_CRTC_ADDRESS;
 333 }
 334
 335 static void
 336 cirrus_switch_mode(struct cirrus_mode_s *table)
 337 {
 338     // Unlock cirrus special
 339     outw(0x1206, VGAREG_SEQU_ADDRESS);
 340     cirrus_switch_mode_setregs(GET_GLOBAL(table->seq), VGAREG_SEQU_ADDRESS);
 341     cirrus_switch_mode_setregs(GET_GLOBAL(table->graph), VGAREG_GRDC_ADDRESS);
 342     cirrus_switch_mode_setregs(GET_GLOBAL(table->crtc), cirrus_get_crtc());
 343
 344     outb(0x00, VGAREG_PEL_MASK);
 345     inb(VGAREG_PEL_MASK);
 346     inb(VGAREG_PEL_MASK);
 347     inb(VGAREG_PEL_MASK);
 348     inb(VGAREG_PEL_MASK);
 349     outb(GET_GLOBAL(table->hidden_dac), VGAREG_PEL_MASK);
 350     outb(0xff, VGAREG_PEL_MASK);
 351
 352     u8 vesacolortype = GET_GLOBAL(table->vesacolortype);
 353     u8 v = vgahw_get_single_palette_reg(0x10) & 0xfe;
 354     if (vesacolortype == 3)
 355         v |= 0x41;
 356     else if (vesacolortype)
 357         v |= 0x01;
 358     vgahw_set_single_palette_reg(0x10, v);
 359 }
 360
 361 static u8
 362 cirrus_get_memsize(void)
 363 {
 364     // get DRAM band width
 365     outb(0x0f, VGAREG_SEQU_ADDRESS);
 366     u8 v = inb(VGAREG_SEQU_DATA);
 367     u8 x = (v >> 3) & 0x03;
 368     if (x == 0x03) {
 369         if (v & 0x80)
 370             // 4MB
 371             return 0x40;
 372         // 2MB
 373         return 0x20;
 374     }
 375     return 0x04 << x;
 376 }
 377
 378 static void
 379 cirrus_enable_16k_granularity(void)
 380 {
 381     outb(0x0b, VGAREG_GRDC_ADDRESS);
 382     u8 v = inb(VGAREG_GRDC_DATA);
 383     outb(v | 0x20, VGAREG_GRDC_DATA);
 384 }
 385
 386 static void
 387 cirrus_clear_vram(u16 param)
 388 {
 389     cirrus_enable_16k_granularity();
 390     u8 count = cirrus_get_memsize() * 4;
 391     u8 i;
 392     for (i=0; i<count; i++) {
 393         outw((i<<8) | 0x09, VGAREG_GRDC_ADDRESS);
 394         memset16_far(SEG_GRAPH, 0, param, 16 * 1024);
 395     }
 396     outw(0x0009, VGAREG_GRDC_ADDRESS);
 397 }
 398
 399 int
 400 cirrus_set_video_mode(u8 mode, u8 noclearmem)
 401 {
 402     dprintf(1, "cirrus mode %d\n", mode);
 403     SET_BDA(vbe_mode, 0);
 404     struct cirrus_mode_s *table_g = cirrus_get_modeentry(mode);
 405     if (table_g) {
 406         cirrus_switch_mode(table_g);
 407         if (!noclearmem)
 408             cirrus_clear_vram(0xffff);
 409         SET_BDA(video_mode, mode);
 410         return 1;
 411     }
 412     table_g = cirrus_get_modeentry(0xfe);
 413     cirrus_switch_mode(table_g);
 414     dprintf(1, "cirrus mode switch regular\n");
 415     return 0;
 416 }
 417
 418 static int
 419 cirrus_check(void)
 420 {
 421     outw(0x9206, VGAREG_SEQU_ADDRESS);
 422     return inb(VGAREG_SEQU_DATA) == 0x12;
 423 }
 424
 425
 426 /****************************************************************
 427  * extbios
 428  ****************************************************************/
 429
 430 static void
 431 cirrus_extbios_80h(struct bregs *regs)
 432 {
 433     u16 crtc_addr = cirrus_get_crtc();
 434     outb(0x27, crtc_addr);
 435     u8 v = inb(crtc_addr + 1);
 436     if (v == 0xa0)
 437         // 5430
 438         regs->ax = 0x0032;
 439     else if (v == 0xb8)
 440         // 5446
 441         regs->ax = 0x0039;
 442     else
 443         regs->ax = 0x00ff;
 444     regs->bx = 0x00;
 445     return;
 446 }
 447
 448 static void
 449 cirrus_extbios_81h(struct bregs *regs)
 450 {
 451     // XXX
 452     regs->ax = 0x0100;
 453 }
 454
 455 static void
 456 cirrus_extbios_82h(struct bregs *regs)
 457 {
 458     u16 crtc_addr = cirrus_get_crtc();
 459     outb(0x27, crtc_addr);
 460     regs->al = inb(crtc_addr + 1) & 0x03;
 461     regs->ah = 0xAF;
 462 }
 463
 464 static void
 465 cirrus_extbios_85h(struct bregs *regs)
 466 {
 467     regs->al = cirrus_get_memsize();
 468 }
 469
 470 static void
 471 cirrus_extbios_9Ah(struct bregs *regs)
 472 {
 473     regs->ax = 0x4060;
 474     regs->cx = 0x1132;
 475 }
 476
 477 extern void a0h_callback(void);
 478 ASM16(
 479     // fatal: not implemented yet
 480     "a0h_callback:"
 481     "cli\n"
 482     "hlt\n"
 483     "retf");
 484
 485 static void
 486 cirrus_extbios_A0h(struct bregs *regs)
 487 {
 488     struct cirrus_mode_s *table_g = cirrus_get_modeentry(regs->al & 0x7f);
 489     regs->ah = (table_g ? 1 : 0);
 490     regs->si = 0xffff;
 491     regs->di = regs->ds = regs->es = regs->bx = (u32)a0h_callback;
 492 }
 493
 494 static void
 495 cirrus_extbios_A1h(struct bregs *regs)
 496 {
 497     regs->bx = 0x0e00; // IBM 8512/8513, color
 498 }
 499
 500 static void
 501 cirrus_extbios_A2h(struct bregs *regs)
 502 {
 503     regs->al = 0x07; // HSync 31.5 - 64.0 kHz
 504 }
 505
 506 static void
 507 cirrus_extbios_AEh(struct bregs *regs)
 508 {
 509     regs->al = 0x01; // High Refresh 75Hz
 510 }
 511
 512 void
 513 cirrus_extbios(struct bregs *regs)
 514 {
 515     // XXX - regs->bl < 0x80 or > 0xaf call regular handlers.
 516     switch (regs->bl) {
 517     case 0x80: cirrus_extbios_80h(regs); break;
 518     case 0x81: cirrus_extbios_81h(regs); break;
 519     case 0x82: cirrus_extbios_82h(regs); break;
 520     case 0x85: cirrus_extbios_85h(regs); break;
 521     case 0x9a: cirrus_extbios_9Ah(regs); break;
 522     case 0xa0: cirrus_extbios_A0h(regs); break;
 523     case 0xa1: cirrus_extbios_A1h(regs); break;
 524     case 0xa2: cirrus_extbios_A2h(regs); break;
 525     case 0xae: cirrus_extbios_AEh(regs); break;
 526     default: break;
 527     }
 528 }
 529
 530
 531 /****************************************************************
 532  * vesa calls
 533  ****************************************************************/
 534
 535 #if 0
 536 static u16
 537 cirrus_vesamode_to_mode(u16 vesamode)
 538 {
 539     // XXX - convert assembler
 540     return 0;
 541 }
 542
 543 static u8
 544 cirrus_get_bpp_bytes(void)
 545 {
 546     // XXX - convert assembler
 547     return 0;
 548 }
 549
 550 static void
 551 cirrus_set_line_offset(u16 new_line_offset)
 552 {
 553     // XXX - convert assembler
 554 }
 555
 556 static u16
 557 cirrus_get_line_offset(void)
 558 {
 559     // XXX - convert assembler
 560     return 0;
 561 }
 562
 563 static u16
 564 cirrus_get_line_offset_entry(void *table)
 565 {
 566     // XXX - convert assembler
 567     return 0;
 568 }
 569
 570 static void
 571 cirrus_set_start_addr(void *addr)
 572 {
 573     // XXX - convert assembler
 574 }
 575
 576 static void *
 577 cirrus_get_start_addr(void)
 578 {
 579     // XXX - convert assembler
 580     return NULL;
 581 }
 582 #endif
 583
 584 static void
 585 cirrus_vesa_00h(struct bregs *regs)
 586 {
 587     // XXX - convert assembler
 588 }
 589
 590 static void
 591 cirrus_vesa_01h(struct bregs *regs)
 592 {
 593     // XXX - convert assembler
 594 }
 595
 596 static void
 597 cirrus_vesa_02h(struct bregs *regs)
 598 {
 599     // XXX - convert assembler
 600 }
 601
 602 static void
 603 cirrus_vesa_03h(struct bregs *regs)
 604 {
 605     // XXX - convert assembler
 606 }
 607
 608 // XXX - add cirrus_vesa_05h_farentry to vgaentry.S
 609
 610 static void
 611 cirrus_vesa_05h(struct bregs *regs)
 612 {
 613     // XXX - convert assembler
 614 }
 615
 616 static void
 617 cirrus_vesa_06h(struct bregs *regs)
 618 {
 619     // XXX - convert assembler
 620 }
 621
 622 static void
 623 cirrus_vesa_07h(struct bregs *regs)
 624 {
 625     // XXX - convert assembler
 626 }
 627
 628 static void
 629 cirrus_vesa_10h(struct bregs *regs)
 630 {
 631     // XXX - convert assembler
 632 }
 633
 634 static void
 635 cirrus_vesa_not_handled(struct bregs *regs)
 636 {
 637     debug_stub(regs);
 638     regs->ax = 0x014f;
 639 }
 640
 641 void
 642 cirrus_vesa(struct bregs *regs)
 643 {
 644     switch (regs->al) {
 645     case 0x00: cirrus_vesa_00h(regs); break;
 646     case 0x01: cirrus_vesa_01h(regs); break;
 647     case 0x02: cirrus_vesa_02h(regs); break;
 648     case 0x03: cirrus_vesa_03h(regs); break;
 649     case 0x05: cirrus_vesa_05h(regs); break;
 650     case 0x06: cirrus_vesa_06h(regs); break;
 651     case 0x07: cirrus_vesa_07h(regs); break;
 652     case 0x10: cirrus_vesa_10h(regs); break;
 653     default:   cirrus_vesa_not_handled(regs); break;
 654     }
 655 }
 656
 657
 658 /****************************************************************
 659  * init
 660  ****************************************************************/
 661
 662 void
 663 cirrus_init(void)
 664 {
 665     dprintf(1, "cirrus init\n");
 666     if (! cirrus_check())
 667         return;
 668     dprintf(1, "cirrus init 2\n");
 669
 670     // memory setup
 671     outb(0x0f, VGAREG_SEQU_ADDRESS);
 672     u8 v = inb(VGAREG_SEQU_DATA);
 673     outb(((v & 0x18) << 8) | 0x0a, VGAREG_SEQU_ADDRESS);
 674     // set vga mode
 675     outw(0x0007, VGAREG_SEQU_ADDRESS);
 676     // reset bitblt
 677     outw(0x0431, VGAREG_GRDC_ADDRESS);
 678     outw(0x0031, VGAREG_GRDC_ADDRESS);
 679 }