1 // QEMU Cirrus CLGD 54xx VGABIOS Extension.
3 // Copyright (C) 2009 Kevin O'Connor <kevin@koconnor.net>
4 // Copyright (c) 2004 Makoto Suzuki (suzu)
6 // This file may be distributed under the terms of the GNU LGPLv3 license.
8 #include "vgatables.h" // cirrus_init
9 #include "biosvar.h" // GET_GLOBAL
10 #include "util.h" // dprintf
11 #include "bregs.h" // struct bregs
12 #include "vbe.h" // struct vbe_info
15 /****************************************************************
17 ****************************************************************/
19 struct cirrus_mode_s {
26 u16 hidden_dac; /* 0x3c6 */
28 u16 *graph; /* 0x3ce */
29 u16 *crtc; /* 0x3d4 */
45 static u16 cseq_vga[] VAR16 = {0x0007,0xffff};
46 static u16 cgraph_vga[] VAR16 = {0x0009,0x000a,0x000b,0xffff};
47 static u16 ccrtc_vga[] VAR16 = {0x001a,0x001b,0x001d,0xffff};
50 static u16 cgraph_svgacolor[] VAR16 = {
51 0x0000,0x0001,0x0002,0x0003,0x0004,0x4005,0x0506,0x0f07,0xff08,
56 static u16 cseq_640x480x8[] VAR16 = {
57 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
58 0x580b,0x580c,0x580d,0x580e,
60 0x331b,0x331c,0x331d,0x331e,
63 static u16 ccrtc_640x480x8[] VAR16 = {
65 0x5f00,0x4f01,0x4f02,0x8003,0x5204,0x1e05,0x0b06,0x3e07,
67 0xea10,0xdf12,0x5013,0x4014,0xdf15,0x0b16,0xc317,0xff18,
72 static u16 cseq_640x480x16[] VAR16 = {
73 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1707,
74 0x580b,0x580c,0x580d,0x580e,
76 0x331b,0x331c,0x331d,0x331e,
79 static u16 ccrtc_640x480x16[] VAR16 = {
81 0x5f00,0x4f01,0x4f02,0x8003,0x5204,0x1e05,0x0b06,0x3e07,
83 0xea10,0xdf12,0xa013,0x4014,0xdf15,0x0b16,0xc317,0xff18,
88 static u16 cseq_640x480x24[] VAR16 = {
89 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1507,
90 0x580b,0x580c,0x580d,0x580e,
92 0x331b,0x331c,0x331d,0x331e,
95 static u16 ccrtc_640x480x24[] VAR16 = {
97 0x5f00,0x4f01,0x4f02,0x8003,0x5204,0x1e05,0x0b06,0x3e07,
99 0xea10,0xdf12,0x0013,0x4014,0xdf15,0x0b16,0xc317,0xff18,
100 0x001a,0x321b,0x001d,
104 static u16 cseq_800x600x8[] VAR16 = {
105 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
106 0x230b,0x230c,0x230d,0x230e,
107 0x0412,0x0013,0x2017,
108 0x141b,0x141c,0x141d,0x141e,
111 static u16 ccrtc_800x600x8[] VAR16 = {
112 0x2311,0x7d00,0x6301,0x6302,0x8003,0x6b04,0x1a05,0x9806,0xf007,
113 0x6009,0x000c,0x000d,
114 0x7d10,0x5712,0x6413,0x4014,0x5715,0x9816,0xc317,0xff18,
115 0x001a,0x221b,0x001d,
119 static u16 cseq_800x600x16[] VAR16 = {
120 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1707,
121 0x230b,0x230c,0x230d,0x230e,
122 0x0412,0x0013,0x2017,
123 0x141b,0x141c,0x141d,0x141e,
126 static u16 ccrtc_800x600x16[] VAR16 = {
127 0x2311,0x7d00,0x6301,0x6302,0x8003,0x6b04,0x1a05,0x9806,0xf007,
128 0x6009,0x000c,0x000d,
129 0x7d10,0x5712,0xc813,0x4014,0x5715,0x9816,0xc317,0xff18,
130 0x001a,0x221b,0x001d,
134 static u16 cseq_800x600x24[] VAR16 = {
135 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1507,
136 0x230b,0x230c,0x230d,0x230e,
137 0x0412,0x0013,0x2017,
138 0x141b,0x141c,0x141d,0x141e,
141 static u16 ccrtc_800x600x24[] VAR16 = {
142 0x2311,0x7d00,0x6301,0x6302,0x8003,0x6b04,0x1a05,0x9806,0xf007,
143 0x6009,0x000c,0x000d,
144 0x7d10,0x5712,0x2c13,0x4014,0x5715,0x9816,0xc317,0xff18,
145 0x001a,0x321b,0x001d,
149 static u16 cseq_1024x768x8[] VAR16 = {
150 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
151 0x760b,0x760c,0x760d,0x760e,
152 0x0412,0x0013,0x2017,
153 0x341b,0x341c,0x341d,0x341e,
156 static u16 ccrtc_1024x768x8[] VAR16 = {
157 0x2911,0xa300,0x7f01,0x7f02,0x8603,0x8304,0x9405,0x2406,0xf507,
158 0x6009,0x000c,0x000d,
159 0x0310,0xff12,0x8013,0x4014,0xff15,0x2416,0xc317,0xff18,
160 0x001a,0x221b,0x001d,
164 static u16 cseq_1024x768x16[] VAR16 = {
165 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1707,
166 0x760b,0x760c,0x760d,0x760e,
167 0x0412,0x0013,0x2017,
168 0x341b,0x341c,0x341d,0x341e,
171 static u16 ccrtc_1024x768x16[] VAR16 = {
172 0x2911,0xa300,0x7f01,0x7f02,0x8603,0x8304,0x9405,0x2406,0xf507,
173 0x6009,0x000c,0x000d,
174 0x0310,0xff12,0x0013,0x4014,0xff15,0x2416,0xc317,0xff18,
175 0x001a,0x321b,0x001d,
179 static u16 cseq_1024x768x24[] VAR16 = {
180 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1507,
181 0x760b,0x760c,0x760d,0x760e,
182 0x0412,0x0013,0x2017,
183 0x341b,0x341c,0x341d,0x341e,
186 static u16 ccrtc_1024x768x24[] VAR16 = {
187 0x2911,0xa300,0x7f01,0x7f02,0x8603,0x8304,0x9405,0x2406,0xf507,
188 0x6009,0x000c,0x000d,
189 0x0310,0xff12,0x8013,0x4014,0xff15,0x2416,0xc317,0xff18,
190 0x001a,0x321b,0x001d,
194 static u16 cseq_1280x1024x8[] VAR16 = {
195 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
196 0x760b,0x760c,0x760d,0x760e,
197 0x0412,0x0013,0x2017,
198 0x341b,0x341c,0x341d,0x341e,
201 static u16 ccrtc_1280x1024x8[] VAR16 = {
202 0x2911,0xc300,0x9f01,0x9f02,0x8603,0x8304,0x9405,0x2406,0xf707,
203 0x6009,0x000c,0x000d,
204 0x0310,0xff12,0xa013,0x4014,0xff15,0x2416,0xc317,0xff18,
205 0x001a,0x221b,0x001d,
209 static u16 cseq_1280x1024x16[] VAR16 = {
210 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1707,
211 0x760b,0x760c,0x760d,0x760e,
212 0x0412,0x0013,0x2017,
213 0x341b,0x341c,0x341d,0x341e,
216 static u16 ccrtc_1280x1024x16[] VAR16 = {
217 0x2911,0xc300,0x9f01,0x9f02,0x8603,0x8304,0x9405,0x2406,0xf707,
218 0x6009,0x000c,0x000d,
219 0x0310,0xff12,0x4013,0x4014,0xff15,0x2416,0xc317,0xff18,
220 0x001a,0x321b,0x001d,
225 static u16 cseq_1600x1200x8[] VAR16 = {
226 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
227 0x760b,0x760c,0x760d,0x760e,
228 0x0412,0x0013,0x2017,
229 0x341b,0x341c,0x341d,0x341e,
232 static u16 ccrtc_1600x1200x8[] VAR16 = {
233 0x2911,0xc300,0x9f01,0x9f02,0x8603,0x8304,0x9405,0x2406,0xf707,
234 0x6009,0x000c,0x000d,
235 0x0310,0xff12,0xa013,0x4014,0xff15,0x2416,0xc317,0xff18,
236 0x001a,0x221b,0x001d,
240 static struct cirrus_mode_s cirrus_modes[] VAR16 = {
241 {0x5f,640,480,8,0x00,
242 cseq_640x480x8,cgraph_svgacolor,ccrtc_640x480x8,8,
244 {0x64,640,480,16,0xe1,
245 cseq_640x480x16,cgraph_svgacolor,ccrtc_640x480x16,16,
247 {0x66,640,480,15,0xf0,
248 cseq_640x480x16,cgraph_svgacolor,ccrtc_640x480x16,16,
249 6,5,10,5,5,5,0,1,15},
250 {0x71,640,480,24,0xe5,
251 cseq_640x480x24,cgraph_svgacolor,ccrtc_640x480x24,24,
254 {0x5c,800,600,8,0x00,
255 cseq_800x600x8,cgraph_svgacolor,ccrtc_800x600x8,8,
257 {0x65,800,600,16,0xe1,
258 cseq_800x600x16,cgraph_svgacolor,ccrtc_800x600x16,16,
260 {0x67,800,600,15,0xf0,
261 cseq_800x600x16,cgraph_svgacolor,ccrtc_800x600x16,16,
262 6,5,10,5,5,5,0,1,15},
264 {0x60,1024,768,8,0x00,
265 cseq_1024x768x8,cgraph_svgacolor,ccrtc_1024x768x8,8,
267 {0x74,1024,768,16,0xe1,
268 cseq_1024x768x16,cgraph_svgacolor,ccrtc_1024x768x16,16,
270 {0x68,1024,768,15,0xf0,
271 cseq_1024x768x16,cgraph_svgacolor,ccrtc_1024x768x16,16,
272 6,5,10,5,5,5,0,1,15},
274 {0x78,800,600,24,0xe5,
275 cseq_800x600x24,cgraph_svgacolor,ccrtc_800x600x24,24,
277 {0x79,1024,768,24,0xe5,
278 cseq_1024x768x24,cgraph_svgacolor,ccrtc_1024x768x24,24,
281 {0x6d,1280,1024,8,0x00,
282 cseq_1280x1024x8,cgraph_svgacolor,ccrtc_1280x1024x8,8,
284 {0x69,1280,1024,15,0xf0,
285 cseq_1280x1024x16,cgraph_svgacolor,ccrtc_1280x1024x16,16,
286 6,5,10,5,5,5,0,1,15},
287 {0x75,1280,1024,16,0xe1,
288 cseq_1280x1024x16,cgraph_svgacolor,ccrtc_1280x1024x16,16,
291 {0x7b,1600,1200,8,0x00,
292 cseq_1600x1200x8,cgraph_svgacolor,ccrtc_1600x1200x8,8,
295 {0xfe,0,0,0,0,cseq_vga,cgraph_vga,ccrtc_vga,0,
296 0xff,0,0,0,0,0,0,0,0},
300 /****************************************************************
302 ****************************************************************/
304 static struct cirrus_mode_s *
305 cirrus_get_modeentry(u8 mode)
307 struct cirrus_mode_s *table_g = cirrus_modes;
308 while (table_g < &cirrus_modes[ARRAY_SIZE(cirrus_modes)]) {
309 u16 tmode = GET_GLOBAL(table_g->mode);
318 cirrus_switch_mode_setregs(u16 *data, u16 port)
321 u16 val = GET_GLOBAL(*data);
330 cirrus_get_crtc(void)
332 if (inb(VGAREG_READ_MISC_OUTPUT) & 1)
333 return VGAREG_VGA_CRTC_ADDRESS;
334 return VGAREG_MDA_CRTC_ADDRESS;
338 cirrus_switch_mode(struct cirrus_mode_s *table)
340 // Unlock cirrus special
341 outw(0x1206, VGAREG_SEQU_ADDRESS);
342 cirrus_switch_mode_setregs(GET_GLOBAL(table->seq), VGAREG_SEQU_ADDRESS);
343 cirrus_switch_mode_setregs(GET_GLOBAL(table->graph), VGAREG_GRDC_ADDRESS);
344 cirrus_switch_mode_setregs(GET_GLOBAL(table->crtc), cirrus_get_crtc());
346 outb(0x00, VGAREG_PEL_MASK);
347 inb(VGAREG_PEL_MASK);
348 inb(VGAREG_PEL_MASK);
349 inb(VGAREG_PEL_MASK);
350 inb(VGAREG_PEL_MASK);
351 outb(GET_GLOBAL(table->hidden_dac), VGAREG_PEL_MASK);
352 outb(0xff, VGAREG_PEL_MASK);
354 u8 vesacolortype = GET_GLOBAL(table->vesacolortype);
355 u8 v = vgahw_get_single_palette_reg(0x10) & 0xfe;
356 if (vesacolortype == 3)
358 else if (vesacolortype)
360 vgahw_set_single_palette_reg(0x10, v);
364 cirrus_get_memsize(void)
366 // get DRAM band width
367 outb(0x0f, VGAREG_SEQU_ADDRESS);
368 u8 v = inb(VGAREG_SEQU_DATA);
369 u8 x = (v >> 3) & 0x03;
381 cirrus_enable_16k_granularity(void)
383 outb(0x0b, VGAREG_GRDC_ADDRESS);
384 u8 v = inb(VGAREG_GRDC_DATA);
385 outb(v | 0x20, VGAREG_GRDC_DATA);
389 cirrus_clear_vram(u16 param)
391 cirrus_enable_16k_granularity();
392 u8 count = cirrus_get_memsize() * 4;
394 for (i=0; i<count; i++) {
395 outw((i<<8) | 0x09, VGAREG_GRDC_ADDRESS);
396 memset16_far(SEG_GRAPH, 0, param, 16 * 1024);
398 outw(0x0009, VGAREG_GRDC_ADDRESS);
402 cirrus_set_video_mode(u8 mode, u8 noclearmem)
404 dprintf(1, "cirrus mode %d\n", mode);
405 SET_BDA(vbe_mode, 0);
406 struct cirrus_mode_s *table_g = cirrus_get_modeentry(mode);
408 cirrus_switch_mode(table_g);
410 cirrus_clear_vram(0xffff);
411 SET_BDA(video_mode, mode);
414 table_g = cirrus_get_modeentry(0xfe);
415 cirrus_switch_mode(table_g);
416 dprintf(1, "cirrus mode switch regular\n");
423 outw(0x9206, VGAREG_SEQU_ADDRESS);
424 return inb(VGAREG_SEQU_DATA) == 0x12;
428 /****************************************************************
430 ****************************************************************/
433 cirrus_extbios_80h(struct bregs *regs)
435 u16 crtc_addr = cirrus_get_crtc();
436 outb(0x27, crtc_addr);
437 u8 v = inb(crtc_addr + 1);
451 cirrus_extbios_81h(struct bregs *regs)
458 cirrus_extbios_82h(struct bregs *regs)
460 u16 crtc_addr = cirrus_get_crtc();
461 outb(0x27, crtc_addr);
462 regs->al = inb(crtc_addr + 1) & 0x03;
467 cirrus_extbios_85h(struct bregs *regs)
469 regs->al = cirrus_get_memsize();
473 cirrus_extbios_9Ah(struct bregs *regs)
479 extern void a0h_callback(void);
481 // fatal: not implemented yet
488 cirrus_extbios_A0h(struct bregs *regs)
490 struct cirrus_mode_s *table_g = cirrus_get_modeentry(regs->al & 0x7f);
491 regs->ah = (table_g ? 1 : 0);
493 regs->di = regs->ds = regs->es = regs->bx = (u32)a0h_callback;
497 cirrus_extbios_A1h(struct bregs *regs)
499 regs->bx = 0x0e00; // IBM 8512/8513, color
503 cirrus_extbios_A2h(struct bregs *regs)
505 regs->al = 0x07; // HSync 31.5 - 64.0 kHz
509 cirrus_extbios_AEh(struct bregs *regs)
511 regs->al = 0x01; // High Refresh 75Hz
515 cirrus_extbios(struct bregs *regs)
517 // XXX - regs->bl < 0x80 or > 0xaf call regular handlers.
519 case 0x80: cirrus_extbios_80h(regs); break;
520 case 0x81: cirrus_extbios_81h(regs); break;
521 case 0x82: cirrus_extbios_82h(regs); break;
522 case 0x85: cirrus_extbios_85h(regs); break;
523 case 0x9a: cirrus_extbios_9Ah(regs); break;
524 case 0xa0: cirrus_extbios_A0h(regs); break;
525 case 0xa1: cirrus_extbios_A1h(regs); break;
526 case 0xa2: cirrus_extbios_A2h(regs); break;
527 case 0xae: cirrus_extbios_AEh(regs); break;
533 /****************************************************************
535 ****************************************************************/
539 } cirrus_vesa_modelist[] VAR16 = {
573 cirrus_vesamode_to_mode(u16 vesamode)
576 for (i=0; i<ARRAY_SIZE(cirrus_vesa_modelist); i++)
577 if (GET_GLOBAL(cirrus_vesa_modelist[i].vesamode) == vesamode)
578 return GET_GLOBAL(cirrus_vesa_modelist[i].mode);
583 cirrus_get_bpp_bytes(void)
585 outb(0x07, VGAREG_SEQU_ADDRESS);
586 u8 v = inb(VGAREG_SEQU_DATA) & 0x0e;
596 cirrus_set_line_offset(u16 new_line_offset)
598 u16 crtc_addr = cirrus_get_crtc();
599 outb(0x13, crtc_addr);
600 outb(new_line_offset / 8, crtc_addr + 1);
602 outb(0x1b, crtc_addr);
603 u8 v = inb(crtc_addr + 1);
604 outb((((new_line_offset / 8) & 0x100) >> 4) | (v & 0xef), crtc_addr + 1);
608 cirrus_get_line_offset(void)
610 u16 crtc_addr = cirrus_get_crtc();
611 outb(0x13, crtc_addr);
612 u8 reg13 = inb(crtc_addr + 1);
613 outb(0x1b, crtc_addr);
614 u8 reg1b = inb(crtc_addr + 1);
616 return (((reg1b << 4) & 0x100) + reg13) * 8;
620 cirrus_get_line_offset_entry(struct cirrus_mode_s *table_g)
622 u16 *crtc = GET_GLOBAL(table_g->crtc);
627 reg13 = GET_GLOBAL(*c);
628 if ((reg13 & 0xff) == 0x13)
637 reg1b = GET_GLOBAL(*c);
638 if ((reg1b & 0xff) == 0x1b)
644 return (((reg1b << 4) & 0x100) + reg13) * 8;
648 cirrus_set_start_addr(u32 addr)
650 u16 crtc_addr = cirrus_get_crtc();
651 outb(0x0d, crtc_addr);
652 outb(addr, crtc_addr + 1);
654 outb(0x0c, crtc_addr);
655 outb(addr>>8, crtc_addr + 1);
657 outb(0x1d, crtc_addr);
658 u8 v = inb(crtc_addr + 1);
659 outb(((addr & 0x0800) >> 4) | (v & 0x7f), crtc_addr + 1);
661 outb(0x1b, crtc_addr);
662 v = inb(crtc_addr + 1);
663 outb(((addr & 0x0100) >> 8) | ((addr & 0x0600) >> 7) | (v & 0xf2)
668 cirrus_get_start_addr(void)
670 u16 crtc_addr = cirrus_get_crtc();
671 outb(0x0c, crtc_addr);
672 u8 b2 = inb(crtc_addr + 1);
674 outb(0x0d, crtc_addr);
675 u8 b1 = inb(crtc_addr + 1);
677 outb(0x1b, crtc_addr);
678 u8 b3 = inb(crtc_addr + 1);
680 outb(0x1d, crtc_addr);
681 u8 b4 = inb(crtc_addr + 1);
683 return (b1 | (b2<<8) | ((b3 & 0x01) << 16) | ((b3 & 0x0c) << 15)
684 | ((b4 & 0x80) << 12));
688 cirrus_vesa_00h(struct bregs *regs)
691 struct vbe_info *info = (void*)(regs->di+0);
693 if (GET_FARVAR(seg, info->signature) == VBE2_SIGNATURE) {
694 SET_FARVAR(seg, info->oem_revision, 0x0100);
695 SET_FARVAR(seg, info->oem_vendor_string,
696 SEGOFF(get_global_seg(), (u32)VBE_VENDOR_STRING));
697 SET_FARVAR(seg, info->oem_product_string,
698 SEGOFF(get_global_seg(), (u32)VBE_PRODUCT_STRING));
699 SET_FARVAR(seg, info->oem_revision_string,
700 SEGOFF(get_global_seg(), (u32)VBE_REVISION_STRING));
702 SET_FARVAR(seg, info->signature, VESA_SIGNATURE);
704 SET_FARVAR(seg, info->version, 0x0200);
706 SET_FARVAR(seg, info->oem_string
707 , SEGOFF(get_global_seg(), (u32)VBE_OEM_STRING));
708 SET_FARVAR(seg, info->capabilities, 0);
709 SET_FARVAR(seg, info->total_memory, cirrus_get_memsize());
711 u16 *destmode = (void*)info->reserved;
712 SET_FARVAR(seg, info->video_mode, SEGOFF(seg, (u32)destmode));
714 for (i=0; i<ARRAY_SIZE(cirrus_vesa_modelist); i++)
715 SET_FARVAR(seg, destmode[i]
716 , GET_GLOBAL(cirrus_vesa_modelist[i].vesamode));
717 SET_FARVAR(seg, destmode[i], 0xffff);
722 static u32 cirrus_lfb_addr VAR16;
725 cirrus_vesa_01h(struct bregs *regs)
727 u16 mode = cirrus_vesamode_to_mode(regs->cx & 0x3fff);
732 struct cirrus_mode_s *table_g = cirrus_get_modeentry(mode);
733 u32 lfb = GET_GLOBAL(cirrus_lfb_addr); // XXX
734 if ((regs->cx & 0x4000) && !lfb) {
740 struct vbe_mode_info *info = (void*)(regs->di+0);
741 memset_far(seg, info, 0, sizeof(*info));
743 SET_FARVAR(seg, info->mode_attributes, lfb ? 0xbb : 0x3b);
744 SET_FARVAR(seg, info->winA_attributes, 0x07);
745 SET_FARVAR(seg, info->winB_attributes, 0);
746 SET_FARVAR(seg, info->win_granularity, 16);
747 SET_FARVAR(seg, info->win_size, 64);
748 SET_FARVAR(seg, info->winA_seg, SEG_GRAPH);
749 SET_FARVAR(seg, info->winB_seg, 0x0);
750 SET_FARVAR(seg, info->win_func_ptr.segoff, 0x0); // XXX
751 u16 linesize = cirrus_get_line_offset_entry(table_g);
752 SET_FARVAR(seg, info->bytes_per_scanline, linesize);
753 SET_FARVAR(seg, info->xres, GET_GLOBAL(table_g->width));
754 u16 height = GET_GLOBAL(table_g->height);
755 SET_FARVAR(seg, info->yres, height);
756 SET_FARVAR(seg, info->xcharsize, 8);
757 SET_FARVAR(seg, info->ycharsize, 16);
758 SET_FARVAR(seg, info->planes, 1);
759 SET_FARVAR(seg, info->bits_per_pixel, GET_GLOBAL(table_g->depth));
760 SET_FARVAR(seg, info->banks, 1);
761 SET_FARVAR(seg, info->mem_model, GET_GLOBAL(table_g->vesacolortype));
762 SET_FARVAR(seg, info->bank_size, 0);
764 int pages = (cirrus_get_memsize() * 64 * 1024) / (height * linesize);
765 SET_FARVAR(seg, info->pages, pages - 1);
766 SET_FARVAR(seg, info->reserved0, 0);
768 SET_FARVAR(seg, info->red_size, GET_GLOBAL(table_g->vesaredmask));
769 SET_FARVAR(seg, info->red_pos, GET_GLOBAL(table_g->vesaredpos));
770 SET_FARVAR(seg, info->green_size, GET_GLOBAL(table_g->vesagreenmask));
771 SET_FARVAR(seg, info->green_pos, GET_GLOBAL(table_g->vesagreenpos));
772 SET_FARVAR(seg, info->blue_size, GET_GLOBAL(table_g->vesabluemask));
773 SET_FARVAR(seg, info->blue_pos, GET_GLOBAL(table_g->vesabluepos));
774 SET_FARVAR(seg, info->alpha_size, GET_GLOBAL(table_g->vesareservedmask));
775 SET_FARVAR(seg, info->alpha_pos, GET_GLOBAL(table_g->vesareservedpos));
776 u8 directcolor_info = GET_GLOBAL(table_g->bitsperpixel) <= 8;
777 SET_FARVAR(seg, info->directcolor_info, directcolor_info);
779 SET_FARVAR(seg, info->phys_base, lfb);
785 cirrus_vesa_02h(struct bregs *regs)
787 if (regs->bx & 0x3e00) {
791 if ((regs->bx & 0x1ff) < 0x100) {
792 // XXX - call legacy mode switch
797 u16 mode = cirrus_vesamode_to_mode(regs->cx & 0x3fff);
802 struct cirrus_mode_s *table_g = cirrus_get_modeentry(mode);
803 cirrus_switch_mode(table_g);
805 if (!(regs->bx & 0x4000))
806 cirrus_enable_16k_granularity();
807 if (!(regs->bx & 0x8000))
808 cirrus_clear_vram(0);
809 SET_BDA(video_mode, mode);
810 SET_BDA(vbe_mode, regs->bx);
816 cirrus_vesa_03h(struct bregs *regs)
818 u16 mode = GET_BDA(vbe_mode);
820 mode = GET_BDA(video_mode);
826 // XXX - add cirrus_vesa_05h_farentry to vgaentry.S
829 cirrus_vesa_05h(struct bregs *regs)
835 if (regs->dx >= 0x100)
837 outw((regs->dx << 8) | (regs->bl + 9), VGAREG_GRDC_ADDRESS);
838 } else if (regs->bh == 1) {
840 outb(regs->bl + 9, VGAREG_GRDC_ADDRESS);
841 regs->dx = inb(VGAREG_GRDC_DATA);
852 cirrus_vesa_06h(struct bregs *regs)
859 if (regs->bl == 0x00) {
860 cirrus_set_line_offset(cirrus_get_bpp_bytes() * regs->cx);
861 } else if (regs->bl == 0x02) {
862 cirrus_set_line_offset(regs->cx);
865 u32 v = cirrus_get_line_offset();
866 regs->cx = v / cirrus_get_bpp_bytes();
868 regs->dx = (cirrus_get_memsize() * 64 * 1024) / v;
873 cirrus_vesa_07h(struct bregs *regs)
875 if (regs->bl == 0x80 || regs->bl == 0x00) {
876 u32 addr = (cirrus_get_bpp_bytes() * regs->cx
877 + cirrus_get_line_offset() * regs->dx);
878 cirrus_set_start_addr(addr / 4);
879 } else if (regs->bl == 0x01) {
880 u32 addr = cirrus_get_start_addr() * 4;
881 u32 linelength = cirrus_get_line_offset();
882 regs->dx = addr / linelength;
883 regs->cx = (addr % linelength) / cirrus_get_bpp_bytes();
893 cirrus_vesa_10h(struct bregs *regs)
895 if (regs->bl == 0x00) {
900 if (regs->bl == 0x01) {
901 SET_BDA(vbe_flag, regs->bh);
905 if (regs->bl == 0x02) {
906 regs->bh = GET_BDA(vbe_flag);
914 cirrus_vesa_not_handled(struct bregs *regs)
921 cirrus_vesa(struct bregs *regs)
924 case 0x00: cirrus_vesa_00h(regs); break;
925 case 0x01: cirrus_vesa_01h(regs); break;
926 case 0x02: cirrus_vesa_02h(regs); break;
927 case 0x03: cirrus_vesa_03h(regs); break;
928 case 0x05: cirrus_vesa_05h(regs); break;
929 case 0x06: cirrus_vesa_06h(regs); break;
930 case 0x07: cirrus_vesa_07h(regs); break;
931 case 0x10: cirrus_vesa_10h(regs); break;
932 default: cirrus_vesa_not_handled(regs); break;
937 /****************************************************************
939 ****************************************************************/
944 dprintf(1, "cirrus init\n");
945 if (! cirrus_check())
947 dprintf(1, "cirrus init 2\n");
950 outb(0x0f, VGAREG_SEQU_ADDRESS);
951 u8 v = inb(VGAREG_SEQU_DATA);
952 outb(((v & 0x18) << 8) | 0x0a, VGAREG_SEQU_ADDRESS);
954 outw(0x0007, VGAREG_SEQU_ADDRESS);
956 outw(0x0431, VGAREG_GRDC_ADDRESS);
957 outw(0x0031, VGAREG_GRDC_ADDRESS);