vgasrc/clext.c

   1 //  QEMU Cirrus CLGD 54xx VGABIOS Extension.
   2 //
   3 // Copyright (C) 2009  Kevin O'Connor <kevin@koconnor.net>
   4 //  Copyright (c) 2004 Makoto Suzuki (suzu)
   5 //
   6 // This file may be distributed under the terms of the GNU LGPLv3 license.
   7
   8 #include "vgatables.h" // cirrus_init
   9 #include "biosvar.h" // GET_GLOBAL
  10 #include "util.h" // dprintf
  11 #include "bregs.h" // struct bregs
  12 #include "vbe.h" // struct vbe_info
  13
  14
  15 /****************************************************************
  16  * tables
  17  ****************************************************************/
  18
  19 struct cirrus_mode_s {
  20     /* + 0 */
  21     u16 mode;
  22     u16 width;
  23     u16 height;
  24     u16 depth;
  25     /* + 8 */
  26     u16 hidden_dac; /* 0x3c6 */
  27     u16 *seq; /* 0x3c4 */
  28     u16 *graph; /* 0x3ce */
  29     u16 *crtc; /* 0x3d4 */
  30     /* +16 */
  31     u8 bitsperpixel;
  32     u8 vesacolortype;
  33     u8 vesaredmask;
  34     u8 vesaredpos;
  35     u8 vesagreenmask;
  36     u8 vesagreenpos;
  37     u8 vesabluemask;
  38     u8 vesabluepos;
  39     /* +24 */
  40     u8 vesareservedmask;
  41     u8 vesareservedpos;
  42 };
  43
  44 /* VGA */
  45 static u16 cseq_vga[] VAR16 = {0x0007,0xffff};
  46 static u16 cgraph_vga[] VAR16 = {0x0009,0x000a,0x000b,0xffff};
  47 static u16 ccrtc_vga[] VAR16 = {0x001a,0x001b,0x001d,0xffff};
  48
  49 /* extensions */
  50 static u16 cgraph_svgacolor[] VAR16 = {
  51     0x0000,0x0001,0x0002,0x0003,0x0004,0x4005,0x0506,0x0f07,0xff08,
  52     0x0009,0x000a,0x000b,
  53     0xffff
  54 };
  55 /* 640x480x8 */
  56 static u16 cseq_640x480x8[] VAR16 = {
  57     0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
  58     0x580b,0x580c,0x580d,0x580e,
  59     0x0412,0x0013,0x2017,
  60     0x331b,0x331c,0x331d,0x331e,
  61     0xffff
  62 };
  63 static u16 ccrtc_640x480x8[] VAR16 = {
  64     0x2c11,
  65     0x5f00,0x4f01,0x4f02,0x8003,0x5204,0x1e05,0x0b06,0x3e07,
  66     0x4009,0x000c,0x000d,
  67     0xea10,0xdf12,0x5013,0x4014,0xdf15,0x0b16,0xc317,0xff18,
  68     0x001a,0x221b,0x001d,
  69     0xffff
  70 };
  71 /* 640x480x16 */
  72 static u16 cseq_640x480x16[] VAR16 = {
  73     0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1707,
  74     0x580b,0x580c,0x580d,0x580e,
  75     0x0412,0x0013,0x2017,
  76     0x331b,0x331c,0x331d,0x331e,
  77     0xffff
  78 };
  79 static u16 ccrtc_640x480x16[] VAR16 = {
  80     0x2c11,
  81     0x5f00,0x4f01,0x4f02,0x8003,0x5204,0x1e05,0x0b06,0x3e07,
  82     0x4009,0x000c,0x000d,
  83     0xea10,0xdf12,0xa013,0x4014,0xdf15,0x0b16,0xc317,0xff18,
  84     0x001a,0x221b,0x001d,
  85     0xffff
  86 };
  87 /* 640x480x24 */
  88 static u16 cseq_640x480x24[] VAR16 = {
  89     0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1507,
  90     0x580b,0x580c,0x580d,0x580e,
  91     0x0412,0x0013,0x2017,
  92     0x331b,0x331c,0x331d,0x331e,
  93     0xffff
  94 };
  95 static u16 ccrtc_640x480x24[] VAR16 = {
  96     0x2c11,
  97     0x5f00,0x4f01,0x4f02,0x8003,0x5204,0x1e05,0x0b06,0x3e07,
  98     0x4009,0x000c,0x000d,
  99     0xea10,0xdf12,0x0013,0x4014,0xdf15,0x0b16,0xc317,0xff18,
 100     0x001a,0x321b,0x001d,
 101     0xffff
 102 };
 103 /* 800x600x8 */
 104 static u16 cseq_800x600x8[] VAR16 = {
 105     0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
 106     0x230b,0x230c,0x230d,0x230e,
 107     0x0412,0x0013,0x2017,
 108     0x141b,0x141c,0x141d,0x141e,
 109     0xffff
 110 };
 111 static u16 ccrtc_800x600x8[] VAR16 = {
 112     0x2311,0x7d00,0x6301,0x6302,0x8003,0x6b04,0x1a05,0x9806,0xf007,
 113     0x6009,0x000c,0x000d,
 114     0x7d10,0x5712,0x6413,0x4014,0x5715,0x9816,0xc317,0xff18,
 115     0x001a,0x221b,0x001d,
 116     0xffff
 117 };
 118 /* 800x600x16 */
 119 static u16 cseq_800x600x16[] VAR16 = {
 120     0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1707,
 121     0x230b,0x230c,0x230d,0x230e,
 122     0x0412,0x0013,0x2017,
 123     0x141b,0x141c,0x141d,0x141e,
 124     0xffff
 125 };
 126 static u16 ccrtc_800x600x16[] VAR16 = {
 127     0x2311,0x7d00,0x6301,0x6302,0x8003,0x6b04,0x1a05,0x9806,0xf007,
 128     0x6009,0x000c,0x000d,
 129     0x7d10,0x5712,0xc813,0x4014,0x5715,0x9816,0xc317,0xff18,
 130     0x001a,0x221b,0x001d,
 131     0xffff
 132 };
 133 /* 800x600x24 */
 134 static u16 cseq_800x600x24[] VAR16 = {
 135     0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1507,
 136     0x230b,0x230c,0x230d,0x230e,
 137     0x0412,0x0013,0x2017,
 138     0x141b,0x141c,0x141d,0x141e,
 139     0xffff
 140 };
 141 static u16 ccrtc_800x600x24[] VAR16 = {
 142     0x2311,0x7d00,0x6301,0x6302,0x8003,0x6b04,0x1a05,0x9806,0xf007,
 143     0x6009,0x000c,0x000d,
 144     0x7d10,0x5712,0x2c13,0x4014,0x5715,0x9816,0xc317,0xff18,
 145     0x001a,0x321b,0x001d,
 146     0xffff
 147 };
 148 /* 1024x768x8 */
 149 static u16 cseq_1024x768x8[] VAR16 = {
 150     0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
 151     0x760b,0x760c,0x760d,0x760e,
 152     0x0412,0x0013,0x2017,
 153     0x341b,0x341c,0x341d,0x341e,
 154     0xffff
 155 };
 156 static u16 ccrtc_1024x768x8[] VAR16 = {
 157     0x2911,0xa300,0x7f01,0x7f02,0x8603,0x8304,0x9405,0x2406,0xf507,
 158     0x6009,0x000c,0x000d,
 159     0x0310,0xff12,0x8013,0x4014,0xff15,0x2416,0xc317,0xff18,
 160     0x001a,0x221b,0x001d,
 161     0xffff
 162 };
 163 /* 1024x768x16 */
 164 static u16 cseq_1024x768x16[] VAR16 = {
 165     0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1707,
 166     0x760b,0x760c,0x760d,0x760e,
 167     0x0412,0x0013,0x2017,
 168     0x341b,0x341c,0x341d,0x341e,
 169     0xffff
 170 };
 171 static u16 ccrtc_1024x768x16[] VAR16 = {
 172     0x2911,0xa300,0x7f01,0x7f02,0x8603,0x8304,0x9405,0x2406,0xf507,
 173     0x6009,0x000c,0x000d,
 174     0x0310,0xff12,0x0013,0x4014,0xff15,0x2416,0xc317,0xff18,
 175     0x001a,0x321b,0x001d,
 176     0xffff
 177 };
 178 /* 1024x768x24 */
 179 static u16 cseq_1024x768x24[] VAR16 = {
 180     0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1507,
 181     0x760b,0x760c,0x760d,0x760e,
 182     0x0412,0x0013,0x2017,
 183     0x341b,0x341c,0x341d,0x341e,
 184     0xffff
 185 };
 186 static u16 ccrtc_1024x768x24[] VAR16 = {
 187     0x2911,0xa300,0x7f01,0x7f02,0x8603,0x8304,0x9405,0x2406,0xf507,
 188     0x6009,0x000c,0x000d,
 189     0x0310,0xff12,0x8013,0x4014,0xff15,0x2416,0xc317,0xff18,
 190     0x001a,0x321b,0x001d,
 191     0xffff
 192 };
 193 /* 1280x1024x8 */
 194 static u16 cseq_1280x1024x8[] VAR16 = {
 195     0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
 196     0x760b,0x760c,0x760d,0x760e,
 197     0x0412,0x0013,0x2017,
 198     0x341b,0x341c,0x341d,0x341e,
 199     0xffff
 200 };
 201 static u16 ccrtc_1280x1024x8[] VAR16 = {
 202     0x2911,0xc300,0x9f01,0x9f02,0x8603,0x8304,0x9405,0x2406,0xf707,
 203     0x6009,0x000c,0x000d,
 204     0x0310,0xff12,0xa013,0x4014,0xff15,0x2416,0xc317,0xff18,
 205     0x001a,0x221b,0x001d,
 206     0xffff
 207 };
 208 /* 1280x1024x16 */
 209 static u16 cseq_1280x1024x16[] VAR16 = {
 210     0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1707,
 211     0x760b,0x760c,0x760d,0x760e,
 212     0x0412,0x0013,0x2017,
 213     0x341b,0x341c,0x341d,0x341e,
 214     0xffff
 215 };
 216 static u16 ccrtc_1280x1024x16[] VAR16 = {
 217     0x2911,0xc300,0x9f01,0x9f02,0x8603,0x8304,0x9405,0x2406,0xf707,
 218     0x6009,0x000c,0x000d,
 219     0x0310,0xff12,0x4013,0x4014,0xff15,0x2416,0xc317,0xff18,
 220     0x001a,0x321b,0x001d,
 221     0xffff
 222 };
 223
 224 /* 1600x1200x8 */
 225 static u16 cseq_1600x1200x8[] VAR16 = {
 226     0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
 227     0x760b,0x760c,0x760d,0x760e,
 228     0x0412,0x0013,0x2017,
 229     0x341b,0x341c,0x341d,0x341e,
 230     0xffff
 231 };
 232 static u16 ccrtc_1600x1200x8[] VAR16 = {
 233     0x2911,0xc300,0x9f01,0x9f02,0x8603,0x8304,0x9405,0x2406,0xf707,
 234     0x6009,0x000c,0x000d,
 235     0x0310,0xff12,0xa013,0x4014,0xff15,0x2416,0xc317,0xff18,
 236     0x001a,0x221b,0x001d,
 237     0xffff
 238 };
 239
 240 static struct cirrus_mode_s cirrus_modes[] VAR16 = {
 241     {0x5f,640,480,8,0x00,
 242      cseq_640x480x8,cgraph_svgacolor,ccrtc_640x480x8,8,
 243      4,0,0,0,0,0,0,0,0},
 244     {0x64,640,480,16,0xe1,
 245      cseq_640x480x16,cgraph_svgacolor,ccrtc_640x480x16,16,
 246      6,5,11,6,5,5,0,0,0},
 247     {0x66,640,480,15,0xf0,
 248      cseq_640x480x16,cgraph_svgacolor,ccrtc_640x480x16,16,
 249      6,5,10,5,5,5,0,1,15},
 250     {0x71,640,480,24,0xe5,
 251      cseq_640x480x24,cgraph_svgacolor,ccrtc_640x480x24,24,
 252      6,8,16,8,8,8,0,0,0},
 253
 254     {0x5c,800,600,8,0x00,
 255      cseq_800x600x8,cgraph_svgacolor,ccrtc_800x600x8,8,
 256      4,0,0,0,0,0,0,0,0},
 257     {0x65,800,600,16,0xe1,
 258      cseq_800x600x16,cgraph_svgacolor,ccrtc_800x600x16,16,
 259      6,5,11,6,5,5,0,0,0},
 260     {0x67,800,600,15,0xf0,
 261      cseq_800x600x16,cgraph_svgacolor,ccrtc_800x600x16,16,
 262      6,5,10,5,5,5,0,1,15},
 263
 264     {0x60,1024,768,8,0x00,
 265      cseq_1024x768x8,cgraph_svgacolor,ccrtc_1024x768x8,8,
 266      4,0,0,0,0,0,0,0,0},
 267     {0x74,1024,768,16,0xe1,
 268      cseq_1024x768x16,cgraph_svgacolor,ccrtc_1024x768x16,16,
 269      6,5,11,6,5,5,0,0,0},
 270     {0x68,1024,768,15,0xf0,
 271      cseq_1024x768x16,cgraph_svgacolor,ccrtc_1024x768x16,16,
 272      6,5,10,5,5,5,0,1,15},
 273
 274     {0x78,800,600,24,0xe5,
 275      cseq_800x600x24,cgraph_svgacolor,ccrtc_800x600x24,24,
 276      6,8,16,8,8,8,0,0,0},
 277     {0x79,1024,768,24,0xe5,
 278      cseq_1024x768x24,cgraph_svgacolor,ccrtc_1024x768x24,24,
 279      6,8,16,8,8,8,0,0,0},
 280
 281     {0x6d,1280,1024,8,0x00,
 282      cseq_1280x1024x8,cgraph_svgacolor,ccrtc_1280x1024x8,8,
 283      4,0,0,0,0,0,0,0,0},
 284     {0x69,1280,1024,15,0xf0,
 285      cseq_1280x1024x16,cgraph_svgacolor,ccrtc_1280x1024x16,16,
 286      6,5,10,5,5,5,0,1,15},
 287     {0x75,1280,1024,16,0xe1,
 288      cseq_1280x1024x16,cgraph_svgacolor,ccrtc_1280x1024x16,16,
 289      6,5,11,6,5,5,0,0,0},
 290
 291     {0x7b,1600,1200,8,0x00,
 292      cseq_1600x1200x8,cgraph_svgacolor,ccrtc_1600x1200x8,8,
 293      4,0,0,0,0,0,0,0,0},
 294
 295     {0xfe,0,0,0,0,cseq_vga,cgraph_vga,ccrtc_vga,0,
 296      0xff,0,0,0,0,0,0,0,0},
 297 };
 298
 299
 300 /****************************************************************
 301  * helper functions
 302  ****************************************************************/
 303
 304 static struct cirrus_mode_s *
 305 cirrus_get_modeentry(u8 mode)
 306 {
 307     struct cirrus_mode_s *table_g = cirrus_modes;
 308     while (table_g < &cirrus_modes[ARRAY_SIZE(cirrus_modes)]) {
 309         u16 tmode = GET_GLOBAL(table_g->mode);
 310         if (tmode == mode)
 311             return table_g;
 312         table_g++;
 313     }
 314     return NULL;
 315 }
 316
 317 static void
 318 cirrus_switch_mode_setregs(u16 *data, u16 port)
 319 {
 320     for (;;) {
 321         u16 val = GET_GLOBAL(*data);
 322         if (val == 0xffff)
 323             return;
 324         outw(val, port);
 325         data++;
 326     }
 327 }
 328
 329 static u16
 330 cirrus_get_crtc(void)
 331 {
 332     if (inb(VGAREG_READ_MISC_OUTPUT) & 1)
 333         return VGAREG_VGA_CRTC_ADDRESS;
 334     return VGAREG_MDA_CRTC_ADDRESS;
 335 }
 336
 337 static void
 338 cirrus_switch_mode(struct cirrus_mode_s *table)
 339 {
 340     // Unlock cirrus special
 341     outw(0x1206, VGAREG_SEQU_ADDRESS);
 342     cirrus_switch_mode_setregs(GET_GLOBAL(table->seq), VGAREG_SEQU_ADDRESS);
 343     cirrus_switch_mode_setregs(GET_GLOBAL(table->graph), VGAREG_GRDC_ADDRESS);
 344     cirrus_switch_mode_setregs(GET_GLOBAL(table->crtc), cirrus_get_crtc());
 345
 346     outb(0x00, VGAREG_PEL_MASK);
 347     inb(VGAREG_PEL_MASK);
 348     inb(VGAREG_PEL_MASK);
 349     inb(VGAREG_PEL_MASK);
 350     inb(VGAREG_PEL_MASK);
 351     outb(GET_GLOBAL(table->hidden_dac), VGAREG_PEL_MASK);
 352     outb(0xff, VGAREG_PEL_MASK);
 353
 354     u8 vesacolortype = GET_GLOBAL(table->vesacolortype);
 355     u8 v = vgahw_get_single_palette_reg(0x10) & 0xfe;
 356     if (vesacolortype == 3)
 357         v |= 0x41;
 358     else if (vesacolortype)
 359         v |= 0x01;
 360     vgahw_set_single_palette_reg(0x10, v);
 361 }
 362
 363 static u8
 364 cirrus_get_memsize(void)
 365 {
 366     // get DRAM band width
 367     outb(0x0f, VGAREG_SEQU_ADDRESS);
 368     u8 v = inb(VGAREG_SEQU_DATA);
 369     u8 x = (v >> 3) & 0x03;
 370     if (x == 0x03) {
 371         if (v & 0x80)
 372             // 4MB
 373             return 0x40;
 374         // 2MB
 375         return 0x20;
 376     }
 377     return 0x04 << x;
 378 }
 379
 380 static void
 381 cirrus_enable_16k_granularity(void)
 382 {
 383     outb(0x0b, VGAREG_GRDC_ADDRESS);
 384     u8 v = inb(VGAREG_GRDC_DATA);
 385     outb(v | 0x20, VGAREG_GRDC_DATA);
 386 }
 387
 388 static void
 389 cirrus_clear_vram(u16 param)
 390 {
 391     cirrus_enable_16k_granularity();
 392     u8 count = cirrus_get_memsize() * 4;
 393     u8 i;
 394     for (i=0; i<count; i++) {
 395         outw((i<<8) | 0x09, VGAREG_GRDC_ADDRESS);
 396         memset16_far(SEG_GRAPH, 0, param, 16 * 1024);
 397     }
 398     outw(0x0009, VGAREG_GRDC_ADDRESS);
 399 }
 400
 401 int
 402 cirrus_set_video_mode(u8 mode, u8 noclearmem)
 403 {
 404     dprintf(1, "cirrus mode %d\n", mode);
 405     SET_BDA(vbe_mode, 0);
 406     struct cirrus_mode_s *table_g = cirrus_get_modeentry(mode);
 407     if (table_g) {
 408         cirrus_switch_mode(table_g);
 409         if (!noclearmem)
 410             cirrus_clear_vram(0xffff);
 411         SET_BDA(video_mode, mode);
 412         return 1;
 413     }
 414     table_g = cirrus_get_modeentry(0xfe);
 415     cirrus_switch_mode(table_g);
 416     dprintf(1, "cirrus mode switch regular\n");
 417     return 0;
 418 }
 419
 420 static int
 421 cirrus_check(void)
 422 {
 423     outw(0x9206, VGAREG_SEQU_ADDRESS);
 424     return inb(VGAREG_SEQU_DATA) == 0x12;
 425 }
 426
 427
 428 /****************************************************************
 429  * extbios
 430  ****************************************************************/
 431
 432 static void
 433 cirrus_extbios_80h(struct bregs *regs)
 434 {
 435     u16 crtc_addr = cirrus_get_crtc();
 436     outb(0x27, crtc_addr);
 437     u8 v = inb(crtc_addr + 1);
 438     if (v == 0xa0)
 439         // 5430
 440         regs->ax = 0x0032;
 441     else if (v == 0xb8)
 442         // 5446
 443         regs->ax = 0x0039;
 444     else
 445         regs->ax = 0x00ff;
 446     regs->bx = 0x00;
 447     return;
 448 }
 449
 450 static void
 451 cirrus_extbios_81h(struct bregs *regs)
 452 {
 453     // XXX
 454     regs->ax = 0x0100;
 455 }
 456
 457 static void
 458 cirrus_extbios_82h(struct bregs *regs)
 459 {
 460     u16 crtc_addr = cirrus_get_crtc();
 461     outb(0x27, crtc_addr);
 462     regs->al = inb(crtc_addr + 1) & 0x03;
 463     regs->ah = 0xAF;
 464 }
 465
 466 static void
 467 cirrus_extbios_85h(struct bregs *regs)
 468 {
 469     regs->al = cirrus_get_memsize();
 470 }
 471
 472 static void
 473 cirrus_extbios_9Ah(struct bregs *regs)
 474 {
 475     regs->ax = 0x4060;
 476     regs->cx = 0x1132;
 477 }
 478
 479 extern void a0h_callback(void);
 480 ASM16(
 481     // fatal: not implemented yet
 482     "a0h_callback:"
 483     "cli\n"
 484     "hlt\n"
 485     "retf");
 486
 487 static void
 488 cirrus_extbios_A0h(struct bregs *regs)
 489 {
 490     struct cirrus_mode_s *table_g = cirrus_get_modeentry(regs->al & 0x7f);
 491     regs->ah = (table_g ? 1 : 0);
 492     regs->si = 0xffff;
 493     regs->di = regs->ds = regs->es = regs->bx = (u32)a0h_callback;
 494 }
 495
 496 static void
 497 cirrus_extbios_A1h(struct bregs *regs)
 498 {
 499     regs->bx = 0x0e00; // IBM 8512/8513, color
 500 }
 501
 502 static void
 503 cirrus_extbios_A2h(struct bregs *regs)
 504 {
 505     regs->al = 0x07; // HSync 31.5 - 64.0 kHz
 506 }
 507
 508 static void
 509 cirrus_extbios_AEh(struct bregs *regs)
 510 {
 511     regs->al = 0x01; // High Refresh 75Hz
 512 }
 513
 514 void
 515 cirrus_extbios(struct bregs *regs)
 516 {
 517     // XXX - regs->bl < 0x80 or > 0xaf call regular handlers.
 518     switch (regs->bl) {
 519     case 0x80: cirrus_extbios_80h(regs); break;
 520     case 0x81: cirrus_extbios_81h(regs); break;
 521     case 0x82: cirrus_extbios_82h(regs); break;
 522     case 0x85: cirrus_extbios_85h(regs); break;
 523     case 0x9a: cirrus_extbios_9Ah(regs); break;
 524     case 0xa0: cirrus_extbios_A0h(regs); break;
 525     case 0xa1: cirrus_extbios_A1h(regs); break;
 526     case 0xa2: cirrus_extbios_A2h(regs); break;
 527     case 0xae: cirrus_extbios_AEh(regs); break;
 528     default: break;
 529     }
 530 }
 531
 532
 533 /****************************************************************
 534  * vesa calls
 535  ****************************************************************/
 536
 537 static struct {
 538     u16 vesamode, mode;
 539 } cirrus_vesa_modelist[] VAR16 = {
 540     // 640x480x8
 541     { 0x101, 0x5f },
 542     // 640x480x15
 543     { 0x110, 0x66 },
 544     // 640x480x16
 545     { 0x111, 0x64 },
 546     // 640x480x24
 547     { 0x112, 0x71 },
 548     // 800x600x8
 549     { 0x103, 0x5c },
 550     // 800x600x15
 551     { 0x113, 0x67 },
 552     // 800x600x16
 553     { 0x114, 0x65 },
 554     // 800x600x24
 555     { 0x115, 0x78 },
 556     // 1024x768x8
 557     { 0x105, 0x60 },
 558     // 1024x768x15
 559     { 0x116, 0x68 },
 560     // 1024x768x16
 561     { 0x117, 0x74 },
 562     // 1024x768x24
 563     { 0x118, 0x79 },
 564     // 1280x1024x8
 565     { 0x107, 0x6d },
 566     // 1280x1024x15
 567     { 0x119, 0x69 },
 568     // 1280x1024x16
 569     { 0x11a, 0x75 },
 570 };
 571
 572 static u16
 573 cirrus_vesamode_to_mode(u16 vesamode)
 574 {
 575     int i;
 576     for (i=0; i<ARRAY_SIZE(cirrus_vesa_modelist); i++)
 577         if (GET_GLOBAL(cirrus_vesa_modelist[i].vesamode) == vesamode)
 578             return GET_GLOBAL(cirrus_vesa_modelist[i].mode);
 579     return 0;
 580 }
 581
 582 static u8
 583 cirrus_get_bpp_bytes(void)
 584 {
 585     outb(0x07, VGAREG_SEQU_ADDRESS);
 586     u8 v = inb(VGAREG_SEQU_DATA) & 0x0e;
 587     if (v == 0x06)
 588         v &= 0x02;
 589     v >>= 1;
 590     if (v != 0x04)
 591         v++;
 592     return v;
 593 }
 594
 595 static void
 596 cirrus_set_line_offset(u16 new_line_offset)
 597 {
 598     u16 crtc_addr = cirrus_get_crtc();
 599     outb(0x13, crtc_addr);
 600     outb(new_line_offset / 8, crtc_addr + 1);
 601
 602     outb(0x1b, crtc_addr);
 603     u8 v = inb(crtc_addr + 1);
 604     outb((((new_line_offset / 8) & 0x100) >> 4) | (v & 0xef), crtc_addr + 1);
 605 }
 606
 607 static u16
 608 cirrus_get_line_offset(void)
 609 {
 610     u16 crtc_addr = cirrus_get_crtc();
 611     outb(0x13, crtc_addr);
 612     u8 reg13 = inb(crtc_addr + 1);
 613     outb(0x1b, crtc_addr);
 614     u8 reg1b = inb(crtc_addr + 1);
 615
 616     return (((reg1b << 4) & 0x100) + reg13) * 8;
 617 }
 618
 619 static u16
 620 cirrus_get_line_offset_entry(struct cirrus_mode_s *table_g)
 621 {
 622     u16 *crtc = GET_GLOBAL(table_g->crtc);
 623
 624     u16 *c = crtc;
 625     u16 reg13;
 626     for (;;) {
 627         reg13 = GET_GLOBAL(*c);
 628         if ((reg13 & 0xff) == 0x13)
 629             break;
 630         c++;
 631     }
 632     reg13 >>= 8;
 633
 634     c = crtc;
 635     u16 reg1b;
 636     for (;;) {
 637         reg1b = GET_GLOBAL(*c);
 638         if ((reg1b & 0xff) == 0x1b)
 639             break;
 640         c++;
 641     }
 642     reg1b >>= 8;
 643
 644     return (((reg1b << 4) & 0x100) + reg13) * 8;
 645 }
 646
 647 static void
 648 cirrus_set_start_addr(u32 addr)
 649 {
 650     u16 crtc_addr = cirrus_get_crtc();
 651     outb(0x0d, crtc_addr);
 652     outb(addr, crtc_addr + 1);
 653
 654     outb(0x0c, crtc_addr);
 655     outb(addr>>8, crtc_addr + 1);
 656
 657     outb(0x1d, crtc_addr);
 658     u8 v = inb(crtc_addr + 1);
 659     outb(((addr & 0x0800) >> 4) | (v & 0x7f), crtc_addr + 1);
 660
 661     outb(0x1b, crtc_addr);
 662     v = inb(crtc_addr + 1);
 663     outb(((addr & 0x0100) >> 8) | ((addr & 0x0600) >> 7) | (v & 0xf2)
 664          , crtc_addr + 1);
 665 }
 666
 667 static u32
 668 cirrus_get_start_addr(void)
 669 {
 670     u16 crtc_addr = cirrus_get_crtc();
 671     outb(0x0c, crtc_addr);
 672     u8 b2 = inb(crtc_addr + 1);
 673
 674     outb(0x0d, crtc_addr);
 675     u8 b1 = inb(crtc_addr + 1);
 676
 677     outb(0x1b, crtc_addr);
 678     u8 b3 = inb(crtc_addr + 1);
 679
 680     outb(0x1d, crtc_addr);
 681     u8 b4 = inb(crtc_addr + 1);
 682
 683     return (b1 | (b2<<8) | ((b3 & 0x01) << 16) | ((b3 & 0x0c) << 15)
 684             | ((b4 & 0x80) << 12));
 685 }
 686
 687 static void
 688 cirrus_vesa_00h(struct bregs *regs)
 689 {
 690     u16 seg = regs->es;
 691     struct vbe_info *info = (void*)(regs->di+0);
 692
 693     if (GET_FARVAR(seg, info->signature) == VBE2_SIGNATURE) {
 694         SET_FARVAR(seg, info->oem_revision, 0x0100);
 695         SET_FARVAR(seg, info->oem_vendor_string,
 696                    SEGOFF(get_global_seg(), (u32)VBE_VENDOR_STRING));
 697         SET_FARVAR(seg, info->oem_product_string,
 698                    SEGOFF(get_global_seg(), (u32)VBE_PRODUCT_STRING));
 699         SET_FARVAR(seg, info->oem_revision_string,
 700                    SEGOFF(get_global_seg(), (u32)VBE_REVISION_STRING));
 701     }
 702     SET_FARVAR(seg, info->signature, VESA_SIGNATURE);
 703
 704     SET_FARVAR(seg, info->version, 0x0200);
 705
 706     SET_FARVAR(seg, info->oem_string
 707                , SEGOFF(get_global_seg(), (u32)VBE_OEM_STRING));
 708     SET_FARVAR(seg, info->capabilities, 0);
 709     SET_FARVAR(seg, info->total_memory, cirrus_get_memsize());
 710
 711     u16 *destmode = (void*)info->reserved;
 712     SET_FARVAR(seg, info->video_mode, SEGOFF(seg, (u32)destmode));
 713     int i;
 714     for (i=0; i<ARRAY_SIZE(cirrus_vesa_modelist); i++)
 715         SET_FARVAR(seg, destmode[i]
 716                    , GET_GLOBAL(cirrus_vesa_modelist[i].vesamode));
 717     SET_FARVAR(seg, destmode[i], 0xffff);
 718
 719     regs->ax = 0x004f;
 720 }
 721
 722 static u32 cirrus_lfb_addr VAR16;
 723
 724 static void
 725 cirrus_vesa_01h(struct bregs *regs)
 726 {
 727     u16 mode = cirrus_vesamode_to_mode(regs->cx & 0x3fff);
 728     if (!mode) {
 729         regs->ax = 0x014f;
 730         return;
 731     }
 732     struct cirrus_mode_s *table_g = cirrus_get_modeentry(mode);
 733     u32 lfb = GET_GLOBAL(cirrus_lfb_addr); // XXX
 734     if ((regs->cx & 0x4000) && !lfb) {
 735         regs->ax = 0x014f;
 736         return;
 737     }
 738
 739     u16 seg = regs->es;
 740     struct vbe_mode_info *info = (void*)(regs->di+0);
 741     memset_far(seg, info, 0, sizeof(*info));
 742
 743     SET_FARVAR(seg, info->mode_attributes, lfb ? 0xbb : 0x3b);
 744     SET_FARVAR(seg, info->winA_attributes, 0x07);
 745     SET_FARVAR(seg, info->winB_attributes, 0);
 746     SET_FARVAR(seg, info->win_granularity, 16);
 747     SET_FARVAR(seg, info->win_size, 64);
 748     SET_FARVAR(seg, info->winA_seg, SEG_GRAPH);
 749     SET_FARVAR(seg, info->winB_seg, 0x0);
 750     SET_FARVAR(seg, info->win_func_ptr.segoff, 0x0); // XXX
 751     u16 linesize = cirrus_get_line_offset_entry(table_g);
 752     SET_FARVAR(seg, info->bytes_per_scanline, linesize);
 753     SET_FARVAR(seg, info->xres, GET_GLOBAL(table_g->width));
 754     u16 height = GET_GLOBAL(table_g->height);
 755     SET_FARVAR(seg, info->yres, height);
 756     SET_FARVAR(seg, info->xcharsize, 8);
 757     SET_FARVAR(seg, info->ycharsize, 16);
 758     SET_FARVAR(seg, info->planes, 1);
 759     SET_FARVAR(seg, info->bits_per_pixel, GET_GLOBAL(table_g->depth));
 760     SET_FARVAR(seg, info->banks, 1);
 761     SET_FARVAR(seg, info->mem_model, GET_GLOBAL(table_g->vesacolortype));
 762     SET_FARVAR(seg, info->bank_size, 0);
 763
 764     int pages = (cirrus_get_memsize() * 64 * 1024) / (height * linesize);
 765     SET_FARVAR(seg, info->pages, pages - 1);
 766     SET_FARVAR(seg, info->reserved0, 0);
 767
 768     SET_FARVAR(seg, info->red_size, GET_GLOBAL(table_g->vesaredmask));
 769     SET_FARVAR(seg, info->red_pos, GET_GLOBAL(table_g->vesaredpos));
 770     SET_FARVAR(seg, info->green_size, GET_GLOBAL(table_g->vesagreenmask));
 771     SET_FARVAR(seg, info->green_pos, GET_GLOBAL(table_g->vesagreenpos));
 772     SET_FARVAR(seg, info->blue_size, GET_GLOBAL(table_g->vesabluemask));
 773     SET_FARVAR(seg, info->blue_pos, GET_GLOBAL(table_g->vesabluepos));
 774     SET_FARVAR(seg, info->alpha_size, GET_GLOBAL(table_g->vesareservedmask));
 775     SET_FARVAR(seg, info->alpha_pos, GET_GLOBAL(table_g->vesareservedpos));
 776     u8 directcolor_info = GET_GLOBAL(table_g->bitsperpixel) <= 8;
 777     SET_FARVAR(seg, info->directcolor_info, directcolor_info);
 778
 779     SET_FARVAR(seg, info->phys_base, lfb);
 780
 781     regs->ax = 0x004f;
 782 }
 783
 784 static void
 785 cirrus_vesa_02h(struct bregs *regs)
 786 {
 787     if (regs->bx & 0x3e00) {
 788         regs->ax = 0x014f;
 789         return;
 790     }
 791     if ((regs->bx & 0x1ff) < 0x100) {
 792         // XXX - call legacy mode switch
 793         regs->ax = 0x004f;
 794         return;
 795     }
 796
 797     u16 mode = cirrus_vesamode_to_mode(regs->cx & 0x3fff);
 798     if (!mode) {
 799         regs->ax = 0x014f;
 800         return;
 801     }
 802     struct cirrus_mode_s *table_g = cirrus_get_modeentry(mode);
 803     cirrus_switch_mode(table_g);
 804
 805     if (!(regs->bx & 0x4000))
 806         cirrus_enable_16k_granularity();
 807     if (!(regs->bx & 0x8000))
 808         cirrus_clear_vram(0);
 809     SET_BDA(video_mode, mode);
 810     SET_BDA(vbe_mode, regs->bx);
 811
 812     regs->ax = 0x004f;
 813 }
 814
 815 static void
 816 cirrus_vesa_03h(struct bregs *regs)
 817 {
 818     u16 mode = GET_BDA(vbe_mode);
 819     if (!mode)
 820         mode = GET_BDA(video_mode);
 821     regs->bx = mode;
 822
 823     regs->ax = 0x004f;
 824 }
 825
 826 // XXX - add cirrus_vesa_05h_farentry to vgaentry.S
 827
 828 static void
 829 cirrus_vesa_05h(struct bregs *regs)
 830 {
 831     if (regs->bl > 1)
 832         goto fail;
 833     if (regs->bh == 0) {
 834         // set mempage
 835         if (regs->dx >= 0x100)
 836             goto fail;
 837         outw((regs->dx << 8) | (regs->bl + 9), VGAREG_GRDC_ADDRESS);
 838     } else if (regs->bh == 1) {
 839         // get mempage
 840         outb(regs->bl + 9, VGAREG_GRDC_ADDRESS);
 841         regs->dx = inb(VGAREG_GRDC_DATA);
 842     } else
 843         goto fail;
 844
 845     regs->ax = 0x004f;
 846     return;
 847 fail:
 848     regs->ax = 0x014f;
 849 }
 850
 851 static void
 852 cirrus_vesa_06h(struct bregs *regs)
 853 {
 854     if (regs->bl > 2) {
 855         regs->ax = 0x0100;
 856         return;
 857     }
 858
 859     if (regs->bl == 0x00) {
 860         cirrus_set_line_offset(cirrus_get_bpp_bytes() * regs->cx);
 861     } else if (regs->bl == 0x02) {
 862         cirrus_set_line_offset(regs->cx);
 863     }
 864
 865     u32 v = cirrus_get_line_offset();
 866     regs->cx = v / cirrus_get_bpp_bytes();
 867     regs->bx = v;
 868     regs->dx = (cirrus_get_memsize() * 64 * 1024) / v;
 869     regs->ax = 0x004f;
 870 }
 871
 872 static void
 873 cirrus_vesa_07h(struct bregs *regs)
 874 {
 875     if (regs->bl == 0x80 || regs->bl == 0x00) {
 876         u32 addr = (cirrus_get_bpp_bytes() * regs->cx
 877                     + cirrus_get_line_offset() * regs->dx);
 878         cirrus_set_start_addr(addr / 4);
 879     } else if (regs->bl == 0x01) {
 880         u32 addr = cirrus_get_start_addr() * 4;
 881         u32 linelength = cirrus_get_line_offset();
 882         regs->dx = addr / linelength;
 883         regs->cx = (addr % linelength) / cirrus_get_bpp_bytes();
 884     } else {
 885         regs->ax = 0x0100;
 886         return;
 887     }
 888
 889     regs->ax = 0x004f;
 890 }
 891
 892 static void
 893 cirrus_vesa_10h(struct bregs *regs)
 894 {
 895     if (regs->bl == 0x00) {
 896         regs->bx = 0x0f30;
 897         regs->ax = 0x004f;
 898         return;
 899     }
 900     if (regs->bl == 0x01) {
 901         SET_BDA(vbe_flag, regs->bh);
 902         regs->ax = 0x004f;
 903         return;
 904     }
 905     if (regs->bl == 0x02) {
 906         regs->bh = GET_BDA(vbe_flag);
 907         regs->ax = 0x004f;
 908         return;
 909     }
 910     regs->ax = 0x014f;
 911 }
 912
 913 static void
 914 cirrus_vesa_not_handled(struct bregs *regs)
 915 {
 916     debug_stub(regs);
 917     regs->ax = 0x014f;
 918 }
 919
 920 void
 921 cirrus_vesa(struct bregs *regs)
 922 {
 923     switch (regs->al) {
 924     case 0x00: cirrus_vesa_00h(regs); break;
 925     case 0x01: cirrus_vesa_01h(regs); break;
 926     case 0x02: cirrus_vesa_02h(regs); break;
 927     case 0x03: cirrus_vesa_03h(regs); break;
 928     case 0x05: cirrus_vesa_05h(regs); break;
 929     case 0x06: cirrus_vesa_06h(regs); break;
 930     case 0x07: cirrus_vesa_07h(regs); break;
 931     case 0x10: cirrus_vesa_10h(regs); break;
 932     default:   cirrus_vesa_not_handled(regs); break;
 933     }
 934 }
 935
 936
 937 /****************************************************************
 938  * init
 939  ****************************************************************/
 940
 941 void
 942 cirrus_init(void)
 943 {
 944     dprintf(1, "cirrus init\n");
 945     if (! cirrus_check())
 946         return;
 947     dprintf(1, "cirrus init 2\n");
 948
 949     // memory setup
 950     outb(0x0f, VGAREG_SEQU_ADDRESS);
 951     u8 v = inb(VGAREG_SEQU_DATA);
 952     outb(((v & 0x18) << 8) | 0x0a, VGAREG_SEQU_ADDRESS);
 953     // set vga mode
 954     outw(0x0007, VGAREG_SEQU_ADDRESS);
 955     // reset bitblt
 956     outw(0x0431, VGAREG_GRDC_ADDRESS);
 957     outw(0x0031, VGAREG_GRDC_ADDRESS);
 958 }