vgasrc/clext.c

   1 //  QEMU Cirrus CLGD 54xx VGABIOS Extension.
   2 //
   3 // Copyright (C) 2009  Kevin O'Connor <kevin@koconnor.net>
   4 //  Copyright (c) 2004 Makoto Suzuki (suzu)
   5 //
   6 // This file may be distributed under the terms of the GNU LGPLv3 license.
   7
   8 #include "clext.h" // clext_init
   9 #include "vgabios.h" // VBE_VENDOR_STRING
  10 #include "biosvar.h" // GET_GLOBAL
  11 #include "util.h" // dprintf
  12 #include "bregs.h" // struct bregs
  13 #include "vbe.h" // struct vbe_info
  14 #include "stdvga.h" // VGAREG_SEQU_ADDRESS
  15
  16
  17 /****************************************************************
  18  * tables
  19  ****************************************************************/
  20
  21 struct cirrus_mode_s {
  22     u16 mode;
  23     struct vgamode_s info;
  24
  25     u16 hidden_dac; /* 0x3c6 */
  26     u16 *seq; /* 0x3c4 */
  27     u16 *graph; /* 0x3ce */
  28     u16 *crtc; /* 0x3d4 */
  29     u8 bitsperpixel;
  30     u8 vesaredmask;
  31     u8 vesaredpos;
  32     u8 vesagreenmask;
  33     u8 vesagreenpos;
  34     u8 vesabluemask;
  35     u8 vesabluepos;
  36     u8 vesareservedmask;
  37     u8 vesareservedpos;
  38 };
  39
  40 /* VGA */
  41 static u16 cseq_vga[] VAR16 = {0x0007,0xffff};
  42 static u16 cgraph_vga[] VAR16 = {0x0009,0x000a,0x000b,0xffff};
  43 static u16 ccrtc_vga[] VAR16 = {0x001a,0x001b,0x001d,0xffff};
  44
  45 /* extensions */
  46 static u16 cgraph_svgacolor[] VAR16 = {
  47     0x0000,0x0001,0x0002,0x0003,0x0004,0x4005,0x0506,0x0f07,0xff08,
  48     0x0009,0x000a,0x000b,
  49     0xffff
  50 };
  51 /* 640x480x8 */
  52 static u16 cseq_640x480x8[] VAR16 = {
  53     0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
  54     0x580b,0x580c,0x580d,0x580e,
  55     0x0412,0x0013,0x2017,
  56     0x331b,0x331c,0x331d,0x331e,
  57     0xffff
  58 };
  59 static u16 ccrtc_640x480x8[] VAR16 = {
  60     0x2c11,
  61     0x5f00,0x4f01,0x4f02,0x8003,0x5204,0x1e05,0x0b06,0x3e07,
  62     0x4009,0x000c,0x000d,
  63     0xea10,0xdf12,0x5013,0x4014,0xdf15,0x0b16,0xc317,0xff18,
  64     0x001a,0x221b,0x001d,
  65     0xffff
  66 };
  67 /* 640x480x16 */
  68 static u16 cseq_640x480x16[] VAR16 = {
  69     0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1707,
  70     0x580b,0x580c,0x580d,0x580e,
  71     0x0412,0x0013,0x2017,
  72     0x331b,0x331c,0x331d,0x331e,
  73     0xffff
  74 };
  75 static u16 ccrtc_640x480x16[] VAR16 = {
  76     0x2c11,
  77     0x5f00,0x4f01,0x4f02,0x8003,0x5204,0x1e05,0x0b06,0x3e07,
  78     0x4009,0x000c,0x000d,
  79     0xea10,0xdf12,0xa013,0x4014,0xdf15,0x0b16,0xc317,0xff18,
  80     0x001a,0x221b,0x001d,
  81     0xffff
  82 };
  83 /* 640x480x24 */
  84 static u16 cseq_640x480x24[] VAR16 = {
  85     0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1507,
  86     0x580b,0x580c,0x580d,0x580e,
  87     0x0412,0x0013,0x2017,
  88     0x331b,0x331c,0x331d,0x331e,
  89     0xffff
  90 };
  91 static u16 ccrtc_640x480x24[] VAR16 = {
  92     0x2c11,
  93     0x5f00,0x4f01,0x4f02,0x8003,0x5204,0x1e05,0x0b06,0x3e07,
  94     0x4009,0x000c,0x000d,
  95     0xea10,0xdf12,0x0013,0x4014,0xdf15,0x0b16,0xc317,0xff18,
  96     0x001a,0x321b,0x001d,
  97     0xffff
  98 };
  99 /* 800x600x8 */
 100 static u16 cseq_800x600x8[] VAR16 = {
 101     0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
 102     0x230b,0x230c,0x230d,0x230e,
 103     0x0412,0x0013,0x2017,
 104     0x141b,0x141c,0x141d,0x141e,
 105     0xffff
 106 };
 107 static u16 ccrtc_800x600x8[] VAR16 = {
 108     0x2311,0x7d00,0x6301,0x6302,0x8003,0x6b04,0x1a05,0x9806,0xf007,
 109     0x6009,0x000c,0x000d,
 110     0x7d10,0x5712,0x6413,0x4014,0x5715,0x9816,0xc317,0xff18,
 111     0x001a,0x221b,0x001d,
 112     0xffff
 113 };
 114 /* 800x600x16 */
 115 static u16 cseq_800x600x16[] VAR16 = {
 116     0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1707,
 117     0x230b,0x230c,0x230d,0x230e,
 118     0x0412,0x0013,0x2017,
 119     0x141b,0x141c,0x141d,0x141e,
 120     0xffff
 121 };
 122 static u16 ccrtc_800x600x16[] VAR16 = {
 123     0x2311,0x7d00,0x6301,0x6302,0x8003,0x6b04,0x1a05,0x9806,0xf007,
 124     0x6009,0x000c,0x000d,
 125     0x7d10,0x5712,0xc813,0x4014,0x5715,0x9816,0xc317,0xff18,
 126     0x001a,0x221b,0x001d,
 127     0xffff
 128 };
 129 /* 800x600x24 */
 130 static u16 cseq_800x600x24[] VAR16 = {
 131     0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1507,
 132     0x230b,0x230c,0x230d,0x230e,
 133     0x0412,0x0013,0x2017,
 134     0x141b,0x141c,0x141d,0x141e,
 135     0xffff
 136 };
 137 static u16 ccrtc_800x600x24[] VAR16 = {
 138     0x2311,0x7d00,0x6301,0x6302,0x8003,0x6b04,0x1a05,0x9806,0xf007,
 139     0x6009,0x000c,0x000d,
 140     0x7d10,0x5712,0x2c13,0x4014,0x5715,0x9816,0xc317,0xff18,
 141     0x001a,0x321b,0x001d,
 142     0xffff
 143 };
 144 /* 1024x768x8 */
 145 static u16 cseq_1024x768x8[] VAR16 = {
 146     0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
 147     0x760b,0x760c,0x760d,0x760e,
 148     0x0412,0x0013,0x2017,
 149     0x341b,0x341c,0x341d,0x341e,
 150     0xffff
 151 };
 152 static u16 ccrtc_1024x768x8[] VAR16 = {
 153     0x2911,0xa300,0x7f01,0x7f02,0x8603,0x8304,0x9405,0x2406,0xf507,
 154     0x6009,0x000c,0x000d,
 155     0x0310,0xff12,0x8013,0x4014,0xff15,0x2416,0xc317,0xff18,
 156     0x001a,0x221b,0x001d,
 157     0xffff
 158 };
 159 /* 1024x768x16 */
 160 static u16 cseq_1024x768x16[] VAR16 = {
 161     0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1707,
 162     0x760b,0x760c,0x760d,0x760e,
 163     0x0412,0x0013,0x2017,
 164     0x341b,0x341c,0x341d,0x341e,
 165     0xffff
 166 };
 167 static u16 ccrtc_1024x768x16[] VAR16 = {
 168     0x2911,0xa300,0x7f01,0x7f02,0x8603,0x8304,0x9405,0x2406,0xf507,
 169     0x6009,0x000c,0x000d,
 170     0x0310,0xff12,0x0013,0x4014,0xff15,0x2416,0xc317,0xff18,
 171     0x001a,0x321b,0x001d,
 172     0xffff
 173 };
 174 /* 1024x768x24 */
 175 static u16 cseq_1024x768x24[] VAR16 = {
 176     0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1507,
 177     0x760b,0x760c,0x760d,0x760e,
 178     0x0412,0x0013,0x2017,
 179     0x341b,0x341c,0x341d,0x341e,
 180     0xffff
 181 };
 182 static u16 ccrtc_1024x768x24[] VAR16 = {
 183     0x2911,0xa300,0x7f01,0x7f02,0x8603,0x8304,0x9405,0x2406,0xf507,
 184     0x6009,0x000c,0x000d,
 185     0x0310,0xff12,0x8013,0x4014,0xff15,0x2416,0xc317,0xff18,
 186     0x001a,0x321b,0x001d,
 187     0xffff
 188 };
 189 /* 1280x1024x8 */
 190 static u16 cseq_1280x1024x8[] VAR16 = {
 191     0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
 192     0x760b,0x760c,0x760d,0x760e,
 193     0x0412,0x0013,0x2017,
 194     0x341b,0x341c,0x341d,0x341e,
 195     0xffff
 196 };
 197 static u16 ccrtc_1280x1024x8[] VAR16 = {
 198     0x2911,0xc300,0x9f01,0x9f02,0x8603,0x8304,0x9405,0x2406,0xf707,
 199     0x6009,0x000c,0x000d,
 200     0x0310,0xff12,0xa013,0x4014,0xff15,0x2416,0xc317,0xff18,
 201     0x001a,0x221b,0x001d,
 202     0xffff
 203 };
 204 /* 1280x1024x16 */
 205 static u16 cseq_1280x1024x16[] VAR16 = {
 206     0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1707,
 207     0x760b,0x760c,0x760d,0x760e,
 208     0x0412,0x0013,0x2017,
 209     0x341b,0x341c,0x341d,0x341e,
 210     0xffff
 211 };
 212 static u16 ccrtc_1280x1024x16[] VAR16 = {
 213     0x2911,0xc300,0x9f01,0x9f02,0x8603,0x8304,0x9405,0x2406,0xf707,
 214     0x6009,0x000c,0x000d,
 215     0x0310,0xff12,0x4013,0x4014,0xff15,0x2416,0xc317,0xff18,
 216     0x001a,0x321b,0x001d,
 217     0xffff
 218 };
 219
 220 /* 1600x1200x8 */
 221 static u16 cseq_1600x1200x8[] VAR16 = {
 222     0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
 223     0x760b,0x760c,0x760d,0x760e,
 224     0x0412,0x0013,0x2017,
 225     0x341b,0x341c,0x341d,0x341e,
 226     0xffff
 227 };
 228 static u16 ccrtc_1600x1200x8[] VAR16 = {
 229     0x2911,0xc300,0x9f01,0x9f02,0x8603,0x8304,0x9405,0x2406,0xf707,
 230     0x6009,0x000c,0x000d,
 231     0x0310,0xff12,0xa013,0x4014,0xff15,0x2416,0xc317,0xff18,
 232     0x001a,0x221b,0x001d,
 233     0xffff
 234 };
 235
 236 static struct cirrus_mode_s cirrus_modes[] VAR16 = {
 237     {0x5f,{MM_PACKED,640,480,8},0x00,
 238      cseq_640x480x8,cgraph_svgacolor,ccrtc_640x480x8,8,
 239      0,0,0,0,0,0,0,0},
 240     {0x64,{MM_DIRECT,640,480,16},0xe1,
 241      cseq_640x480x16,cgraph_svgacolor,ccrtc_640x480x16,16,
 242      5,11,6,5,5,0,0,0},
 243     {0x66,{MM_DIRECT,640,480,15},0xf0,
 244      cseq_640x480x16,cgraph_svgacolor,ccrtc_640x480x16,16,
 245      5,10,5,5,5,0,1,15},
 246     {0x71,{MM_DIRECT,640,480,24},0xe5,
 247      cseq_640x480x24,cgraph_svgacolor,ccrtc_640x480x24,24,
 248      8,16,8,8,8,0,0,0},
 249
 250     {0x5c,{MM_PACKED,800,600,8},0x00,
 251      cseq_800x600x8,cgraph_svgacolor,ccrtc_800x600x8,8,
 252      0,0,0,0,0,0,0,0},
 253     {0x65,{MM_DIRECT,800,600,16},0xe1,
 254      cseq_800x600x16,cgraph_svgacolor,ccrtc_800x600x16,16,
 255      5,11,6,5,5,0,0,0},
 256     {0x67,{MM_DIRECT,800,600,15},0xf0,
 257      cseq_800x600x16,cgraph_svgacolor,ccrtc_800x600x16,16,
 258      5,10,5,5,5,0,1,15},
 259
 260     {0x60,{MM_PACKED,1024,768,8},0x00,
 261      cseq_1024x768x8,cgraph_svgacolor,ccrtc_1024x768x8,8,
 262      0,0,0,0,0,0,0,0},
 263     {0x74,{MM_DIRECT,1024,768,16},0xe1,
 264      cseq_1024x768x16,cgraph_svgacolor,ccrtc_1024x768x16,16,
 265      5,11,6,5,5,0,0,0},
 266     {0x68,{MM_DIRECT,1024,768,15},0xf0,
 267      cseq_1024x768x16,cgraph_svgacolor,ccrtc_1024x768x16,16,
 268      5,10,5,5,5,0,1,15},
 269
 270     {0x78,{MM_DIRECT,800,600,24},0xe5,
 271      cseq_800x600x24,cgraph_svgacolor,ccrtc_800x600x24,24,
 272      8,16,8,8,8,0,0,0},
 273     {0x79,{MM_DIRECT,1024,768,24},0xe5,
 274      cseq_1024x768x24,cgraph_svgacolor,ccrtc_1024x768x24,24,
 275      8,16,8,8,8,0,0,0},
 276
 277     {0x6d,{MM_PACKED,1280,1024,8},0x00,
 278      cseq_1280x1024x8,cgraph_svgacolor,ccrtc_1280x1024x8,8,
 279      0,0,0,0,0,0,0,0},
 280     {0x69,{MM_DIRECT,1280,1024,15},0xf0,
 281      cseq_1280x1024x16,cgraph_svgacolor,ccrtc_1280x1024x16,16,
 282      5,10,5,5,5,0,1,15},
 283     {0x75,{MM_DIRECT,1280,1024,16},0xe1,
 284      cseq_1280x1024x16,cgraph_svgacolor,ccrtc_1280x1024x16,16,
 285      5,11,6,5,5,0,0,0},
 286
 287     {0x7b,{MM_PACKED,1600,1200,8},0x00,
 288      cseq_1600x1200x8,cgraph_svgacolor,ccrtc_1600x1200x8,8,
 289      0,0,0,0,0,0,0,0},
 290 };
 291
 292 static struct cirrus_mode_s mode_switchback VAR16 =
 293     {0xfe,{0xff,0,0,0},0,cseq_vga,cgraph_vga,ccrtc_vga,0,
 294      0,0,0,0,0,0,0,0};
 295
 296
 297 /****************************************************************
 298  * helper functions
 299  ****************************************************************/
 300
 301 static struct cirrus_mode_s *
 302 cirrus_get_modeentry(u8 mode)
 303 {
 304     struct cirrus_mode_s *table_g = cirrus_modes;
 305     while (table_g < &cirrus_modes[ARRAY_SIZE(cirrus_modes)]) {
 306         u16 tmode = GET_GLOBAL(table_g->mode);
 307         if (tmode == mode)
 308             return table_g;
 309         table_g++;
 310     }
 311     return NULL;
 312 }
 313
 314 struct vgamode_s *
 315 clext_find_mode(int mode)
 316 {
 317     struct cirrus_mode_s *table_g = cirrus_get_modeentry(mode);
 318     if (table_g)
 319         return &table_g->info;
 320     return stdvga_find_mode(mode);
 321 }
 322
 323 static void
 324 cirrus_switch_mode_setregs(u16 *data, u16 port)
 325 {
 326     for (;;) {
 327         u16 val = GET_GLOBAL(*data);
 328         if (val == 0xffff)
 329             return;
 330         outw(val, port);
 331         data++;
 332     }
 333 }
 334
 335 static void
 336 cirrus_switch_mode(struct cirrus_mode_s *table)
 337 {
 338     // Unlock cirrus special
 339     outw(0x1206, VGAREG_SEQU_ADDRESS);
 340     cirrus_switch_mode_setregs(GET_GLOBAL(table->seq), VGAREG_SEQU_ADDRESS);
 341     cirrus_switch_mode_setregs(GET_GLOBAL(table->graph), VGAREG_GRDC_ADDRESS);
 342     cirrus_switch_mode_setregs(GET_GLOBAL(table->crtc), stdvga_get_crtc());
 343
 344     outb(0x00, VGAREG_PEL_MASK);
 345     inb(VGAREG_PEL_MASK);
 346     inb(VGAREG_PEL_MASK);
 347     inb(VGAREG_PEL_MASK);
 348     inb(VGAREG_PEL_MASK);
 349     outb(GET_GLOBAL(table->hidden_dac), VGAREG_PEL_MASK);
 350     outb(0xff, VGAREG_PEL_MASK);
 351
 352     u8 memmodel = GET_GLOBAL(table->info.memmodel);
 353     u8 v = stdvga_get_single_palette_reg(0x10) & 0xfe;
 354     if (memmodel == MM_PLANAR)
 355         v |= 0x41;
 356     else if (memmodel != MM_TEXT)
 357         v |= 0x01;
 358     stdvga_set_single_palette_reg(0x10, v);
 359 }
 360
 361 static u8
 362 cirrus_get_memsize(void)
 363 {
 364     // get DRAM band width
 365     outb(0x0f, VGAREG_SEQU_ADDRESS);
 366     u8 v = inb(VGAREG_SEQU_DATA);
 367     u8 x = (v >> 3) & 0x03;
 368     if (x == 0x03) {
 369         if (v & 0x80)
 370             // 4MB
 371             return 0x40;
 372         // 2MB
 373         return 0x20;
 374     }
 375     return 0x04 << x;
 376 }
 377
 378 static void
 379 cirrus_enable_16k_granularity(void)
 380 {
 381     outb(0x0b, VGAREG_GRDC_ADDRESS);
 382     u8 v = inb(VGAREG_GRDC_DATA);
 383     outb(v | 0x20, VGAREG_GRDC_DATA);
 384 }
 385
 386 static void
 387 cirrus_clear_vram(u16 param)
 388 {
 389     cirrus_enable_16k_granularity();
 390     u8 count = cirrus_get_memsize() * 4;
 391     u8 i;
 392     for (i=0; i<count; i++) {
 393         outw((i<<8) | 0x09, VGAREG_GRDC_ADDRESS);
 394         memset16_far(SEG_GRAPH, 0, param, 16 * 1024);
 395     }
 396     outw(0x0009, VGAREG_GRDC_ADDRESS);
 397 }
 398
 399 int
 400 clext_set_mode(int mode, int flags)
 401 {
 402     dprintf(1, "cirrus mode %d\n", mode);
 403     SET_BDA(vbe_mode, 0);
 404     struct cirrus_mode_s *table_g = cirrus_get_modeentry(mode);
 405     if (table_g) {
 406         cirrus_switch_mode(table_g);
 407         if (!(flags & MF_NOCLEARMEM))
 408             cirrus_clear_vram(0xffff);
 409         SET_BDA(video_mode, mode);
 410         return 0;
 411     }
 412     cirrus_switch_mode(&mode_switchback);
 413     dprintf(1, "cirrus mode switch regular\n");
 414     return stdvga_set_mode(mode, flags);
 415 }
 416
 417 static int
 418 cirrus_check(void)
 419 {
 420     outw(0x9206, VGAREG_SEQU_ADDRESS);
 421     return inb(VGAREG_SEQU_DATA) == 0x12;
 422 }
 423
 424
 425 /****************************************************************
 426  * extbios
 427  ****************************************************************/
 428
 429 static void
 430 cirrus_extbios_80h(struct bregs *regs)
 431 {
 432     u16 crtc_addr = stdvga_get_crtc();
 433     outb(0x27, crtc_addr);
 434     u8 v = inb(crtc_addr + 1);
 435     if (v == 0xa0)
 436         // 5430
 437         regs->ax = 0x0032;
 438     else if (v == 0xb8)
 439         // 5446
 440         regs->ax = 0x0039;
 441     else
 442         regs->ax = 0x00ff;
 443     regs->bx = 0x00;
 444     return;
 445 }
 446
 447 static void
 448 cirrus_extbios_81h(struct bregs *regs)
 449 {
 450     // XXX
 451     regs->ax = 0x0100;
 452 }
 453
 454 static void
 455 cirrus_extbios_82h(struct bregs *regs)
 456 {
 457     u16 crtc_addr = stdvga_get_crtc();
 458     outb(0x27, crtc_addr);
 459     regs->al = inb(crtc_addr + 1) & 0x03;
 460     regs->ah = 0xAF;
 461 }
 462
 463 static void
 464 cirrus_extbios_85h(struct bregs *regs)
 465 {
 466     regs->al = cirrus_get_memsize();
 467 }
 468
 469 static void
 470 cirrus_extbios_9Ah(struct bregs *regs)
 471 {
 472     regs->ax = 0x4060;
 473     regs->cx = 0x1132;
 474 }
 475
 476 extern void a0h_callback(void);
 477 ASM16(
 478     // fatal: not implemented yet
 479     "a0h_callback:"
 480     "cli\n"
 481     "hlt\n"
 482     "retf");
 483
 484 static void
 485 cirrus_extbios_A0h(struct bregs *regs)
 486 {
 487     struct cirrus_mode_s *table_g = cirrus_get_modeentry(regs->al & 0x7f);
 488     regs->ah = (table_g ? 1 : 0);
 489     regs->si = 0xffff;
 490     regs->di = regs->ds = regs->es = regs->bx = (u32)a0h_callback;
 491 }
 492
 493 static void
 494 cirrus_extbios_A1h(struct bregs *regs)
 495 {
 496     regs->bx = 0x0e00; // IBM 8512/8513, color
 497 }
 498
 499 static void
 500 cirrus_extbios_A2h(struct bregs *regs)
 501 {
 502     regs->al = 0x07; // HSync 31.5 - 64.0 kHz
 503 }
 504
 505 static void
 506 cirrus_extbios_AEh(struct bregs *regs)
 507 {
 508     regs->al = 0x01; // High Refresh 75Hz
 509 }
 510
 511 void
 512 cirrus_extbios(struct bregs *regs)
 513 {
 514     // XXX - regs->bl < 0x80 or > 0xaf call regular handlers.
 515     switch (regs->bl) {
 516     case 0x80: cirrus_extbios_80h(regs); break;
 517     case 0x81: cirrus_extbios_81h(regs); break;
 518     case 0x82: cirrus_extbios_82h(regs); break;
 519     case 0x85: cirrus_extbios_85h(regs); break;
 520     case 0x9a: cirrus_extbios_9Ah(regs); break;
 521     case 0xa0: cirrus_extbios_A0h(regs); break;
 522     case 0xa1: cirrus_extbios_A1h(regs); break;
 523     case 0xa2: cirrus_extbios_A2h(regs); break;
 524     case 0xae: cirrus_extbios_AEh(regs); break;
 525     default: break;
 526     }
 527 }
 528
 529
 530 /****************************************************************
 531  * vesa calls
 532  ****************************************************************/
 533
 534 static struct {
 535     u16 vesamode, mode;
 536 } cirrus_vesa_modelist[] VAR16 = {
 537     // 640x480x8
 538     { 0x101, 0x5f },
 539     // 640x480x15
 540     { 0x110, 0x66 },
 541     // 640x480x16
 542     { 0x111, 0x64 },
 543     // 640x480x24
 544     { 0x112, 0x71 },
 545     // 800x600x8
 546     { 0x103, 0x5c },
 547     // 800x600x15
 548     { 0x113, 0x67 },
 549     // 800x600x16
 550     { 0x114, 0x65 },
 551     // 800x600x24
 552     { 0x115, 0x78 },
 553     // 1024x768x8
 554     { 0x105, 0x60 },
 555     // 1024x768x15
 556     { 0x116, 0x68 },
 557     // 1024x768x16
 558     { 0x117, 0x74 },
 559     // 1024x768x24
 560     { 0x118, 0x79 },
 561     // 1280x1024x8
 562     { 0x107, 0x6d },
 563     // 1280x1024x15
 564     { 0x119, 0x69 },
 565     // 1280x1024x16
 566     { 0x11a, 0x75 },
 567 };
 568
 569 void
 570 clext_list_modes(u16 seg, u16 *dest, u16 *last)
 571 {
 572     int i;
 573     for (i=0; i<ARRAY_SIZE(cirrus_vesa_modelist) && dest<last; i++) {
 574         SET_FARVAR(seg, *dest, GET_GLOBAL(cirrus_vesa_modelist[i].vesamode));
 575         dest++;
 576     }
 577     stdvga_list_modes(seg, dest, last);
 578 }
 579
 580 static u16
 581 cirrus_vesamode_to_mode(u16 vesamode)
 582 {
 583     int i;
 584     for (i=0; i<ARRAY_SIZE(cirrus_vesa_modelist); i++)
 585         if (GET_GLOBAL(cirrus_vesa_modelist[i].vesamode) == vesamode)
 586             return GET_GLOBAL(cirrus_vesa_modelist[i].mode);
 587     return 0;
 588 }
 589
 590 static u8
 591 cirrus_get_bpp_bytes(void)
 592 {
 593     outb(0x07, VGAREG_SEQU_ADDRESS);
 594     u8 v = inb(VGAREG_SEQU_DATA) & 0x0e;
 595     if (v == 0x06)
 596         v &= 0x02;
 597     v >>= 1;
 598     if (v != 0x04)
 599         v++;
 600     return v;
 601 }
 602
 603 static void
 604 cirrus_set_line_offset(u16 new_line_offset)
 605 {
 606     u16 crtc_addr = stdvga_get_crtc();
 607     outb(0x13, crtc_addr);
 608     outb(new_line_offset / 8, crtc_addr + 1);
 609
 610     outb(0x1b, crtc_addr);
 611     u8 v = inb(crtc_addr + 1);
 612     outb((((new_line_offset / 8) & 0x100) >> 4) | (v & 0xef), crtc_addr + 1);
 613 }
 614
 615 static u16
 616 cirrus_get_line_offset(void)
 617 {
 618     u16 crtc_addr = stdvga_get_crtc();
 619     outb(0x13, crtc_addr);
 620     u8 reg13 = inb(crtc_addr + 1);
 621     outb(0x1b, crtc_addr);
 622     u8 reg1b = inb(crtc_addr + 1);
 623
 624     return (((reg1b << 4) & 0x100) + reg13) * 8;
 625 }
 626
 627 static u16
 628 cirrus_get_line_offset_entry(struct cirrus_mode_s *table_g)
 629 {
 630     u16 *crtc = GET_GLOBAL(table_g->crtc);
 631
 632     u16 *c = crtc;
 633     u16 reg13;
 634     for (;;) {
 635         reg13 = GET_GLOBAL(*c);
 636         if ((reg13 & 0xff) == 0x13)
 637             break;
 638         c++;
 639     }
 640     reg13 >>= 8;
 641
 642     c = crtc;
 643     u16 reg1b;
 644     for (;;) {
 645         reg1b = GET_GLOBAL(*c);
 646         if ((reg1b & 0xff) == 0x1b)
 647             break;
 648         c++;
 649     }
 650     reg1b >>= 8;
 651
 652     return (((reg1b << 4) & 0x100) + reg13) * 8;
 653 }
 654
 655 static void
 656 cirrus_set_start_addr(u32 addr)
 657 {
 658     u16 crtc_addr = stdvga_get_crtc();
 659     outb(0x0d, crtc_addr);
 660     outb(addr, crtc_addr + 1);
 661
 662     outb(0x0c, crtc_addr);
 663     outb(addr>>8, crtc_addr + 1);
 664
 665     outb(0x1d, crtc_addr);
 666     u8 v = inb(crtc_addr + 1);
 667     outb(((addr & 0x0800) >> 4) | (v & 0x7f), crtc_addr + 1);
 668
 669     outb(0x1b, crtc_addr);
 670     v = inb(crtc_addr + 1);
 671     outb(((addr & 0x0100) >> 8) | ((addr & 0x0600) >> 7) | (v & 0xf2)
 672          , crtc_addr + 1);
 673 }
 674
 675 static u32
 676 cirrus_get_start_addr(void)
 677 {
 678     u16 crtc_addr = stdvga_get_crtc();
 679     outb(0x0c, crtc_addr);
 680     u8 b2 = inb(crtc_addr + 1);
 681
 682     outb(0x0d, crtc_addr);
 683     u8 b1 = inb(crtc_addr + 1);
 684
 685     outb(0x1b, crtc_addr);
 686     u8 b3 = inb(crtc_addr + 1);
 687
 688     outb(0x1d, crtc_addr);
 689     u8 b4 = inb(crtc_addr + 1);
 690
 691     return (b1 | (b2<<8) | ((b3 & 0x01) << 16) | ((b3 & 0x0c) << 15)
 692             | ((b4 & 0x80) << 12));
 693 }
 694
 695 static void
 696 cirrus_vesa_00h(struct bregs *regs)
 697 {
 698     u16 seg = regs->es;
 699     struct vbe_info *info = (void*)(regs->di+0);
 700
 701     if (GET_FARVAR(seg, info->signature) == VBE2_SIGNATURE) {
 702         SET_FARVAR(seg, info->oem_revision, 0x0100);
 703         SET_FARVAR(seg, info->oem_vendor_string,
 704                    SEGOFF(get_global_seg(), (u32)VBE_VENDOR_STRING));
 705         SET_FARVAR(seg, info->oem_product_string,
 706                    SEGOFF(get_global_seg(), (u32)VBE_PRODUCT_STRING));
 707         SET_FARVAR(seg, info->oem_revision_string,
 708                    SEGOFF(get_global_seg(), (u32)VBE_REVISION_STRING));
 709     }
 710     SET_FARVAR(seg, info->signature, VESA_SIGNATURE);
 711
 712     SET_FARVAR(seg, info->version, 0x0200);
 713
 714     SET_FARVAR(seg, info->oem_string
 715                , SEGOFF(get_global_seg(), (u32)VBE_OEM_STRING));
 716     SET_FARVAR(seg, info->capabilities, 0);
 717     SET_FARVAR(seg, info->total_memory, cirrus_get_memsize());
 718
 719     u16 *destmode = (void*)info->reserved;
 720     u16 *last = (void*)&info->reserved[sizeof(info->reserved)];
 721     SET_FARVAR(seg, info->video_mode, SEGOFF(seg, (u32)destmode));
 722     clext_list_modes(seg, destmode, last);
 723
 724     regs->ax = 0x004f;
 725 }
 726
 727 static u32 cirrus_lfb_addr VAR16;
 728
 729 static void
 730 cirrus_vesa_01h(struct bregs *regs)
 731 {
 732     u16 mode = cirrus_vesamode_to_mode(regs->cx & 0x3fff);
 733     if (!mode) {
 734         regs->ax = 0x014f;
 735         return;
 736     }
 737     struct cirrus_mode_s *table_g = cirrus_get_modeentry(mode);
 738     u32 lfb = GET_GLOBAL(cirrus_lfb_addr); // XXX
 739     if ((regs->cx & 0x4000) && !lfb) {
 740         regs->ax = 0x014f;
 741         return;
 742     }
 743
 744     u16 seg = regs->es;
 745     struct vbe_mode_info *info = (void*)(regs->di+0);
 746     memset_far(seg, info, 0, sizeof(*info));
 747
 748     SET_FARVAR(seg, info->mode_attributes, lfb ? 0xbb : 0x3b);
 749     SET_FARVAR(seg, info->winA_attributes, 0x07);
 750     SET_FARVAR(seg, info->winB_attributes, 0);
 751     SET_FARVAR(seg, info->win_granularity, 16);
 752     SET_FARVAR(seg, info->win_size, 64);
 753     SET_FARVAR(seg, info->winA_seg, SEG_GRAPH);
 754     SET_FARVAR(seg, info->winB_seg, 0x0);
 755     SET_FARVAR(seg, info->win_func_ptr.segoff, 0x0); // XXX
 756     u16 linesize = cirrus_get_line_offset_entry(table_g);
 757     SET_FARVAR(seg, info->bytes_per_scanline, linesize);
 758     SET_FARVAR(seg, info->xres, GET_GLOBAL(table_g->info.width));
 759     u16 height = GET_GLOBAL(table_g->info.height);
 760     SET_FARVAR(seg, info->yres, height);
 761     SET_FARVAR(seg, info->xcharsize, 8);
 762     SET_FARVAR(seg, info->ycharsize, 16);
 763     SET_FARVAR(seg, info->planes, 1);
 764     SET_FARVAR(seg, info->bits_per_pixel, GET_GLOBAL(table_g->info.depth));
 765     SET_FARVAR(seg, info->banks, 1);
 766     SET_FARVAR(seg, info->mem_model, GET_GLOBAL(table_g->info.memmodel));
 767     SET_FARVAR(seg, info->bank_size, 0);
 768
 769     int pages = (cirrus_get_memsize() * 64 * 1024) / (height * linesize);
 770     SET_FARVAR(seg, info->pages, pages - 1);
 771     SET_FARVAR(seg, info->reserved0, 0);
 772
 773     SET_FARVAR(seg, info->red_size, GET_GLOBAL(table_g->vesaredmask));
 774     SET_FARVAR(seg, info->red_pos, GET_GLOBAL(table_g->vesaredpos));
 775     SET_FARVAR(seg, info->green_size, GET_GLOBAL(table_g->vesagreenmask));
 776     SET_FARVAR(seg, info->green_pos, GET_GLOBAL(table_g->vesagreenpos));
 777     SET_FARVAR(seg, info->blue_size, GET_GLOBAL(table_g->vesabluemask));
 778     SET_FARVAR(seg, info->blue_pos, GET_GLOBAL(table_g->vesabluepos));
 779     SET_FARVAR(seg, info->alpha_size, GET_GLOBAL(table_g->vesareservedmask));
 780     SET_FARVAR(seg, info->alpha_pos, GET_GLOBAL(table_g->vesareservedpos));
 781     u8 directcolor_info = GET_GLOBAL(table_g->bitsperpixel) <= 8;
 782     SET_FARVAR(seg, info->directcolor_info, directcolor_info);
 783
 784     SET_FARVAR(seg, info->phys_base, lfb);
 785
 786     regs->ax = 0x004f;
 787 }
 788
 789 static void
 790 cirrus_vesa_02h(struct bregs *regs)
 791 {
 792     if (regs->bx & 0x3e00) {
 793         regs->ax = 0x014f;
 794         return;
 795     }
 796     if ((regs->bx & 0x1ff) < 0x100) {
 797         // XXX - call legacy mode switch
 798         regs->ax = 0x004f;
 799         return;
 800     }
 801
 802     u16 mode = cirrus_vesamode_to_mode(regs->cx & 0x3fff);
 803     if (!mode) {
 804         regs->ax = 0x014f;
 805         return;
 806     }
 807     struct cirrus_mode_s *table_g = cirrus_get_modeentry(mode);
 808     cirrus_switch_mode(table_g);
 809
 810     if (!(regs->bx & 0x4000))
 811         cirrus_enable_16k_granularity();
 812     if (!(regs->bx & 0x8000))
 813         cirrus_clear_vram(0);
 814     SET_BDA(video_mode, mode);
 815     SET_BDA(vbe_mode, regs->bx);
 816
 817     regs->ax = 0x004f;
 818 }
 819
 820 static void
 821 cirrus_vesa_03h(struct bregs *regs)
 822 {
 823     u16 mode = GET_BDA(vbe_mode);
 824     if (!mode)
 825         mode = GET_BDA(video_mode);
 826     regs->bx = mode;
 827
 828     regs->ax = 0x004f;
 829 }
 830
 831 // XXX - add cirrus_vesa_05h_farentry to vgaentry.S
 832
 833 static void
 834 cirrus_vesa_05h(struct bregs *regs)
 835 {
 836     if (regs->bl > 1)
 837         goto fail;
 838     if (regs->bh == 0) {
 839         // set mempage
 840         if (regs->dx >= 0x100)
 841             goto fail;
 842         outw((regs->dx << 8) | (regs->bl + 9), VGAREG_GRDC_ADDRESS);
 843     } else if (regs->bh == 1) {
 844         // get mempage
 845         outb(regs->bl + 9, VGAREG_GRDC_ADDRESS);
 846         regs->dx = inb(VGAREG_GRDC_DATA);
 847     } else
 848         goto fail;
 849
 850     regs->ax = 0x004f;
 851     return;
 852 fail:
 853     regs->ax = 0x014f;
 854 }
 855
 856 static void
 857 cirrus_vesa_06h(struct bregs *regs)
 858 {
 859     if (regs->bl > 2) {
 860         regs->ax = 0x0100;
 861         return;
 862     }
 863
 864     if (regs->bl == 0x00) {
 865         cirrus_set_line_offset(cirrus_get_bpp_bytes() * regs->cx);
 866     } else if (regs->bl == 0x02) {
 867         cirrus_set_line_offset(regs->cx);
 868     }
 869
 870     u32 v = cirrus_get_line_offset();
 871     regs->cx = v / cirrus_get_bpp_bytes();
 872     regs->bx = v;
 873     regs->dx = (cirrus_get_memsize() * 64 * 1024) / v;
 874     regs->ax = 0x004f;
 875 }
 876
 877 static void
 878 cirrus_vesa_07h(struct bregs *regs)
 879 {
 880     if (regs->bl == 0x80 || regs->bl == 0x00) {
 881         u32 addr = (cirrus_get_bpp_bytes() * regs->cx
 882                     + cirrus_get_line_offset() * regs->dx);
 883         cirrus_set_start_addr(addr / 4);
 884     } else if (regs->bl == 0x01) {
 885         u32 addr = cirrus_get_start_addr() * 4;
 886         u32 linelength = cirrus_get_line_offset();
 887         regs->dx = addr / linelength;
 888         regs->cx = (addr % linelength) / cirrus_get_bpp_bytes();
 889     } else {
 890         regs->ax = 0x0100;
 891         return;
 892     }
 893
 894     regs->ax = 0x004f;
 895 }
 896
 897 static void
 898 cirrus_vesa_10h(struct bregs *regs)
 899 {
 900     if (regs->bl == 0x00) {
 901         regs->bx = 0x0f30;
 902         regs->ax = 0x004f;
 903         return;
 904     }
 905     if (regs->bl == 0x01) {
 906         SET_BDA(vbe_flag, regs->bh);
 907         regs->ax = 0x004f;
 908         return;
 909     }
 910     if (regs->bl == 0x02) {
 911         regs->bh = GET_BDA(vbe_flag);
 912         regs->ax = 0x004f;
 913         return;
 914     }
 915     regs->ax = 0x014f;
 916 }
 917
 918 static void
 919 cirrus_vesa_not_handled(struct bregs *regs)
 920 {
 921     debug_stub(regs);
 922     regs->ax = 0x014f;
 923 }
 924
 925 void
 926 cirrus_vesa(struct bregs *regs)
 927 {
 928     switch (regs->al) {
 929     case 0x00: cirrus_vesa_00h(regs); break;
 930     case 0x01: cirrus_vesa_01h(regs); break;
 931     case 0x02: cirrus_vesa_02h(regs); break;
 932     case 0x03: cirrus_vesa_03h(regs); break;
 933     case 0x05: cirrus_vesa_05h(regs); break;
 934     case 0x06: cirrus_vesa_06h(regs); break;
 935     case 0x07: cirrus_vesa_07h(regs); break;
 936     case 0x10: cirrus_vesa_10h(regs); break;
 937     default:   cirrus_vesa_not_handled(regs); break;
 938     }
 939 }
 940
 941
 942 /****************************************************************
 943  * init
 944  ****************************************************************/
 945
 946 int
 947 clext_init(void)
 948 {
 949     int ret = stdvga_init();
 950     if (ret)
 951         return ret;
 952
 953     dprintf(1, "cirrus init\n");
 954     if (! cirrus_check())
 955         return -1;
 956     dprintf(1, "cirrus init 2\n");
 957
 958     // memory setup
 959     outb(0x0f, VGAREG_SEQU_ADDRESS);
 960     u8 v = inb(VGAREG_SEQU_DATA);
 961     outb(((v & 0x18) << 8) | 0x0a, VGAREG_SEQU_ADDRESS);
 962     // set vga mode
 963     outw(0x0007, VGAREG_SEQU_ADDRESS);
 964     // reset bitblt
 965     outw(0x0431, VGAREG_GRDC_ADDRESS);
 966     outw(0x0031, VGAREG_GRDC_ADDRESS);
 967
 968     return 0;
 969 }