vgasrc/clext.c

   1 //  QEMU Cirrus CLGD 54xx VGABIOS Extension.
   2 //
   3 // Copyright (C) 2009  Kevin O'Connor <kevin@koconnor.net>
   4 //  Copyright (c) 2004 Makoto Suzuki (suzu)
   5 //
   6 // This file may be distributed under the terms of the GNU LGPLv3 license.
   7
   8 #include "clext.h" // clext_init
   9 #include "vgabios.h" // VBE_VENDOR_STRING
  10 #include "biosvar.h" // GET_GLOBAL
  11 #include "util.h" // dprintf
  12 #include "bregs.h" // struct bregs
  13 #include "vbe.h" // struct vbe_info
  14 #include "stdvga.h" // VGAREG_SEQU_ADDRESS
  15
  16
  17 /****************************************************************
  18  * tables
  19  ****************************************************************/
  20
  21 /* VGA */
  22 static u16 cseq_vga[] VAR16 = {0x0007,0xffff};
  23 static u16 cgraph_vga[] VAR16 = {0x0009,0x000a,0x000b,0xffff};
  24 static u16 ccrtc_vga[] VAR16 = {0x001a,0x001b,0x001d,0xffff};
  25
  26 /* extensions */
  27 static u16 cgraph_svgacolor[] VAR16 = {
  28     0x0000,0x0001,0x0002,0x0003,0x0004,0x4005,0x0506,0x0f07,0xff08,
  29     0x0009,0x000a,0x000b,
  30     0xffff
  31 };
  32 /* 640x480x8 */
  33 static u16 cseq_640x480x8[] VAR16 = {
  34     0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
  35     0x580b,0x580c,0x580d,0x580e,
  36     0x0412,0x0013,0x2017,
  37     0x331b,0x331c,0x331d,0x331e,
  38     0xffff
  39 };
  40 static u16 ccrtc_640x480x8[] VAR16 = {
  41     0x2c11,
  42     0x5f00,0x4f01,0x4f02,0x8003,0x5204,0x1e05,0x0b06,0x3e07,
  43     0x4009,0x000c,0x000d,
  44     0xea10,0xdf12,0x5013,0x4014,0xdf15,0x0b16,0xc317,0xff18,
  45     0x001a,0x221b,0x001d,
  46     0xffff
  47 };
  48 /* 640x480x16 */
  49 static u16 cseq_640x480x16[] VAR16 = {
  50     0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1707,
  51     0x580b,0x580c,0x580d,0x580e,
  52     0x0412,0x0013,0x2017,
  53     0x331b,0x331c,0x331d,0x331e,
  54     0xffff
  55 };
  56 static u16 ccrtc_640x480x16[] VAR16 = {
  57     0x2c11,
  58     0x5f00,0x4f01,0x4f02,0x8003,0x5204,0x1e05,0x0b06,0x3e07,
  59     0x4009,0x000c,0x000d,
  60     0xea10,0xdf12,0xa013,0x4014,0xdf15,0x0b16,0xc317,0xff18,
  61     0x001a,0x221b,0x001d,
  62     0xffff
  63 };
  64 /* 640x480x24 */
  65 static u16 cseq_640x480x24[] VAR16 = {
  66     0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1507,
  67     0x580b,0x580c,0x580d,0x580e,
  68     0x0412,0x0013,0x2017,
  69     0x331b,0x331c,0x331d,0x331e,
  70     0xffff
  71 };
  72 static u16 ccrtc_640x480x24[] VAR16 = {
  73     0x2c11,
  74     0x5f00,0x4f01,0x4f02,0x8003,0x5204,0x1e05,0x0b06,0x3e07,
  75     0x4009,0x000c,0x000d,
  76     0xea10,0xdf12,0xf013,0x4014,0xdf15,0x0b16,0xc317,0xff18,
  77     0x001a,0x221b,0x001d,
  78     0xffff
  79 };
  80 /* 800x600x8 */
  81 static u16 cseq_800x600x8[] VAR16 = {
  82     0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
  83     0x230b,0x230c,0x230d,0x230e,
  84     0x0412,0x0013,0x2017,
  85     0x141b,0x141c,0x141d,0x141e,
  86     0xffff
  87 };
  88 static u16 ccrtc_800x600x8[] VAR16 = {
  89     0x2311,0x7d00,0x6301,0x6302,0x8003,0x6b04,0x1a05,0x9806,0xf007,
  90     0x6009,0x000c,0x000d,
  91     0x7d10,0x5712,0x6413,0x4014,0x5715,0x9816,0xc317,0xff18,
  92     0x001a,0x221b,0x001d,
  93     0xffff
  94 };
  95 /* 800x600x16 */
  96 static u16 cseq_800x600x16[] VAR16 = {
  97     0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1707,
  98     0x230b,0x230c,0x230d,0x230e,
  99     0x0412,0x0013,0x2017,
 100     0x141b,0x141c,0x141d,0x141e,
 101     0xffff
 102 };
 103 static u16 ccrtc_800x600x16[] VAR16 = {
 104     0x2311,0x7d00,0x6301,0x6302,0x8003,0x6b04,0x1a05,0x9806,0xf007,
 105     0x6009,0x000c,0x000d,
 106     0x7d10,0x5712,0xc813,0x4014,0x5715,0x9816,0xc317,0xff18,
 107     0x001a,0x221b,0x001d,
 108     0xffff
 109 };
 110 /* 800x600x24 */
 111 static u16 cseq_800x600x24[] VAR16 = {
 112     0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1507,
 113     0x230b,0x230c,0x230d,0x230e,
 114     0x0412,0x0013,0x2017,
 115     0x141b,0x141c,0x141d,0x141e,
 116     0xffff
 117 };
 118 static u16 ccrtc_800x600x24[] VAR16 = {
 119     0x2311,0x7d00,0x6301,0x6302,0x8003,0x6b04,0x1a05,0x9806,0xf007,
 120     0x6009,0x000c,0x000d,
 121     0x7d10,0x5712,0x2c13,0x4014,0x5715,0x9816,0xc317,0xff18,
 122     0x001a,0x321b,0x001d,
 123     0xffff
 124 };
 125 /* 1024x768x8 */
 126 static u16 cseq_1024x768x8[] VAR16 = {
 127     0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
 128     0x760b,0x760c,0x760d,0x760e,
 129     0x0412,0x0013,0x2017,
 130     0x341b,0x341c,0x341d,0x341e,
 131     0xffff
 132 };
 133 static u16 ccrtc_1024x768x8[] VAR16 = {
 134     0x2911,0xa300,0x7f01,0x7f02,0x8603,0x8304,0x9405,0x2406,0xf507,
 135     0x6009,0x000c,0x000d,
 136     0x0310,0xff12,0x8013,0x4014,0xff15,0x2416,0xc317,0xff18,
 137     0x001a,0x221b,0x001d,
 138     0xffff
 139 };
 140 /* 1024x768x16 */
 141 static u16 cseq_1024x768x16[] VAR16 = {
 142     0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1707,
 143     0x760b,0x760c,0x760d,0x760e,
 144     0x0412,0x0013,0x2017,
 145     0x341b,0x341c,0x341d,0x341e,
 146     0xffff
 147 };
 148 static u16 ccrtc_1024x768x16[] VAR16 = {
 149     0x2911,0xa300,0x7f01,0x7f02,0x8603,0x8304,0x9405,0x2406,0xf507,
 150     0x6009,0x000c,0x000d,
 151     0x0310,0xff12,0x0013,0x4014,0xff15,0x2416,0xc317,0xff18,
 152     0x001a,0x321b,0x001d,
 153     0xffff
 154 };
 155 /* 1024x768x24 */
 156 static u16 cseq_1024x768x24[] VAR16 = {
 157     0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1507,
 158     0x760b,0x760c,0x760d,0x760e,
 159     0x0412,0x0013,0x2017,
 160     0x341b,0x341c,0x341d,0x341e,
 161     0xffff
 162 };
 163 static u16 ccrtc_1024x768x24[] VAR16 = {
 164     0x2911,0xa300,0x7f01,0x7f02,0x8603,0x8304,0x9405,0x2406,0xf507,
 165     0x6009,0x000c,0x000d,
 166     0x0310,0xff12,0x8013,0x4014,0xff15,0x2416,0xc317,0xff18,
 167     0x001a,0x321b,0x001d,
 168     0xffff
 169 };
 170 /* 1280x1024x8 */
 171 static u16 cseq_1280x1024x8[] VAR16 = {
 172     0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
 173     0x760b,0x760c,0x760d,0x760e,
 174     0x0412,0x0013,0x2017,
 175     0x341b,0x341c,0x341d,0x341e,
 176     0xffff
 177 };
 178 static u16 ccrtc_1280x1024x8[] VAR16 = {
 179     0x2911,0xc300,0x9f01,0x9f02,0x8603,0x8304,0x9405,0x2406,0xf707,
 180     0x6009,0x000c,0x000d,
 181     0x0310,0xff12,0xa013,0x4014,0xff15,0x2416,0xc317,0xff18,
 182     0x001a,0x221b,0x001d,
 183     0xffff
 184 };
 185 /* 1280x1024x16 */
 186 static u16 cseq_1280x1024x16[] VAR16 = {
 187     0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1707,
 188     0x760b,0x760c,0x760d,0x760e,
 189     0x0412,0x0013,0x2017,
 190     0x341b,0x341c,0x341d,0x341e,
 191     0xffff
 192 };
 193 static u16 ccrtc_1280x1024x16[] VAR16 = {
 194     0x2911,0xc300,0x9f01,0x9f02,0x8603,0x8304,0x9405,0x2406,0xf707,
 195     0x6009,0x000c,0x000d,
 196     0x0310,0xff12,0x4013,0x4014,0xff15,0x2416,0xc317,0xff18,
 197     0x001a,0x321b,0x001d,
 198     0xffff
 199 };
 200
 201 /* 1600x1200x8 */
 202 static u16 cseq_1600x1200x8[] VAR16 = {
 203     0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
 204     0x760b,0x760c,0x760d,0x760e,
 205     0x0412,0x0013,0x2017,
 206     0x341b,0x341c,0x341d,0x341e,
 207     0xffff
 208 };
 209 static u16 ccrtc_1600x1200x8[] VAR16 = {
 210     0x2911,0xc300,0x9f01,0x9f02,0x8603,0x8304,0x9405,0x2406,0xf707,
 211     0x6009,0x000c,0x000d,
 212     0x0310,0xff12,0xc813,0x4014,0xff15,0x2416,0xc317,0xff18,
 213     0x001a,0x221b,0x001d,
 214     0xffff
 215 };
 216
 217 struct cirrus_mode_s {
 218     u16 mode;
 219     struct vgamode_s info;
 220
 221     u16 hidden_dac; /* 0x3c6 */
 222     u16 *seq; /* 0x3c4 */
 223     u16 *graph; /* 0x3ce */
 224     u16 *crtc; /* 0x3d4 */
 225 };
 226
 227 static struct cirrus_mode_s cirrus_modes[] VAR16 = {
 228     {0x5f,{MM_PACKED,640,480,8},0x00,
 229      cseq_640x480x8,cgraph_svgacolor,ccrtc_640x480x8},
 230     {0x64,{MM_DIRECT,640,480,16},0xe1,
 231      cseq_640x480x16,cgraph_svgacolor,ccrtc_640x480x16},
 232     {0x66,{MM_DIRECT,640,480,15},0xf0,
 233      cseq_640x480x16,cgraph_svgacolor,ccrtc_640x480x16},
 234     {0x71,{MM_DIRECT,640,480,24},0xe5,
 235      cseq_640x480x24,cgraph_svgacolor,ccrtc_640x480x24},
 236
 237     {0x5c,{MM_PACKED,800,600,8},0x00,
 238      cseq_800x600x8,cgraph_svgacolor,ccrtc_800x600x8},
 239     {0x65,{MM_DIRECT,800,600,16},0xe1,
 240      cseq_800x600x16,cgraph_svgacolor,ccrtc_800x600x16},
 241     {0x67,{MM_DIRECT,800,600,15},0xf0,
 242      cseq_800x600x16,cgraph_svgacolor,ccrtc_800x600x16},
 243
 244     {0x60,{MM_PACKED,1024,768,8},0x00,
 245      cseq_1024x768x8,cgraph_svgacolor,ccrtc_1024x768x8},
 246     {0x74,{MM_DIRECT,1024,768,16},0xe1,
 247      cseq_1024x768x16,cgraph_svgacolor,ccrtc_1024x768x16},
 248     {0x68,{MM_DIRECT,1024,768,15},0xf0,
 249      cseq_1024x768x16,cgraph_svgacolor,ccrtc_1024x768x16},
 250
 251     {0x78,{MM_DIRECT,800,600,24},0xe5,
 252      cseq_800x600x24,cgraph_svgacolor,ccrtc_800x600x24},
 253     {0x79,{MM_DIRECT,1024,768,24},0xe5,
 254      cseq_1024x768x24,cgraph_svgacolor,ccrtc_1024x768x24},
 255
 256     {0x6d,{MM_PACKED,1280,1024,8},0x00,
 257      cseq_1280x1024x8,cgraph_svgacolor,ccrtc_1280x1024x8},
 258     {0x69,{MM_DIRECT,1280,1024,15},0xf0,
 259      cseq_1280x1024x16,cgraph_svgacolor,ccrtc_1280x1024x16},
 260     {0x75,{MM_DIRECT,1280,1024,16},0xe1,
 261      cseq_1280x1024x16,cgraph_svgacolor,ccrtc_1280x1024x16},
 262
 263     {0x7b,{MM_PACKED,1600,1200,8},0x00,
 264      cseq_1600x1200x8,cgraph_svgacolor,ccrtc_1600x1200x8},
 265 };
 266
 267 static struct cirrus_mode_s mode_switchback VAR16 =
 268     {0xfe,{0xff},0,cseq_vga,cgraph_vga,ccrtc_vga};
 269
 270 static struct {
 271     u16 vesamode, mode;
 272 } cirrus_vesa_modelist[] VAR16 = {
 273     // 640x480x8
 274     { 0x101, 0x5f },
 275     // 640x480x15
 276     { 0x110, 0x66 },
 277     // 640x480x16
 278     { 0x111, 0x64 },
 279     // 640x480x24
 280     { 0x112, 0x71 },
 281     // 800x600x8
 282     { 0x103, 0x5c },
 283     // 800x600x15
 284     { 0x113, 0x67 },
 285     // 800x600x16
 286     { 0x114, 0x65 },
 287     // 800x600x24
 288     { 0x115, 0x78 },
 289     // 1024x768x8
 290     { 0x105, 0x60 },
 291     // 1024x768x15
 292     { 0x116, 0x68 },
 293     // 1024x768x16
 294     { 0x117, 0x74 },
 295     // 1024x768x24
 296     { 0x118, 0x79 },
 297     // 1280x1024x8
 298     { 0x107, 0x6d },
 299     // 1280x1024x15
 300     { 0x119, 0x69 },
 301     // 1280x1024x16
 302     { 0x11a, 0x75 },
 303 };
 304
 305
 306 /****************************************************************
 307  * helper functions
 308  ****************************************************************/
 309
 310 static u16
 311 cirrus_vesamode_to_mode(u16 vesamode)
 312 {
 313     int i;
 314     for (i=0; i<ARRAY_SIZE(cirrus_vesa_modelist); i++)
 315         if (GET_GLOBAL(cirrus_vesa_modelist[i].vesamode) == vesamode)
 316             return GET_GLOBAL(cirrus_vesa_modelist[i].mode);
 317     return 0;
 318 }
 319
 320 static struct cirrus_mode_s *
 321 cirrus_get_modeentry(int mode)
 322 {
 323     int transmode = cirrus_vesamode_to_mode(mode);
 324     if (transmode)
 325         mode = transmode;
 326     struct cirrus_mode_s *table_g = cirrus_modes;
 327     while (table_g < &cirrus_modes[ARRAY_SIZE(cirrus_modes)]) {
 328         u16 tmode = GET_GLOBAL(table_g->mode);
 329         if (tmode == mode)
 330             return table_g;
 331         table_g++;
 332     }
 333     return NULL;
 334 }
 335
 336 struct vgamode_s *
 337 clext_find_mode(int mode)
 338 {
 339     struct cirrus_mode_s *table_g = cirrus_get_modeentry(mode);
 340     if (table_g)
 341         return &table_g->info;
 342     return stdvga_find_mode(mode);
 343 }
 344
 345 static void
 346 cirrus_switch_mode_setregs(u16 *data, u16 port)
 347 {
 348     for (;;) {
 349         u16 val = GET_GLOBAL(*data);
 350         if (val == 0xffff)
 351             return;
 352         outw(val, port);
 353         data++;
 354     }
 355 }
 356
 357 static void
 358 cirrus_switch_mode(struct cirrus_mode_s *table)
 359 {
 360     // Unlock cirrus special
 361     outw(0x1206, VGAREG_SEQU_ADDRESS);
 362     cirrus_switch_mode_setregs(GET_GLOBAL(table->seq), VGAREG_SEQU_ADDRESS);
 363     cirrus_switch_mode_setregs(GET_GLOBAL(table->graph), VGAREG_GRDC_ADDRESS);
 364     cirrus_switch_mode_setregs(GET_GLOBAL(table->crtc), stdvga_get_crtc());
 365
 366     outb(0x00, VGAREG_PEL_MASK);
 367     inb(VGAREG_PEL_MASK);
 368     inb(VGAREG_PEL_MASK);
 369     inb(VGAREG_PEL_MASK);
 370     inb(VGAREG_PEL_MASK);
 371     outb(GET_GLOBAL(table->hidden_dac), VGAREG_PEL_MASK);
 372     outb(0xff, VGAREG_PEL_MASK);
 373
 374     u8 memmodel = GET_GLOBAL(table->info.memmodel);
 375     u8 v = stdvga_get_single_palette_reg(0x10) & 0xfe;
 376     if (memmodel == MM_PLANAR)
 377         v |= 0x41;
 378     else if (memmodel != MM_TEXT)
 379         v |= 0x01;
 380     stdvga_set_single_palette_reg(0x10, v);
 381 }
 382
 383 static u8
 384 cirrus_get_memsize(void)
 385 {
 386     // get DRAM band width
 387     outb(0x0f, VGAREG_SEQU_ADDRESS);
 388     u8 v = inb(VGAREG_SEQU_DATA);
 389     u8 x = (v >> 3) & 0x03;
 390     if (x == 0x03) {
 391         if (v & 0x80)
 392             // 4MB
 393             return 0x40;
 394         // 2MB
 395         return 0x20;
 396     }
 397     return 0x04 << x;
 398 }
 399
 400 static void
 401 cirrus_enable_16k_granularity(void)
 402 {
 403     outb(0x0b, VGAREG_GRDC_ADDRESS);
 404     u8 v = inb(VGAREG_GRDC_DATA);
 405     outb(v | 0x20, VGAREG_GRDC_DATA);
 406 }
 407
 408 static void
 409 cirrus_clear_vram(u16 param)
 410 {
 411     cirrus_enable_16k_granularity();
 412     u8 count = cirrus_get_memsize() * 4;
 413     u8 i;
 414     for (i=0; i<count; i++) {
 415         outw((i<<8) | 0x09, VGAREG_GRDC_ADDRESS);
 416         memset16_far(SEG_GRAPH, 0, param, 16 * 1024);
 417     }
 418     outw(0x0009, VGAREG_GRDC_ADDRESS);
 419 }
 420
 421 int
 422 clext_set_mode(int mode, int flags)
 423 {
 424     dprintf(1, "cirrus mode %d\n", mode);
 425     SET_BDA(vbe_mode, 0);
 426     struct cirrus_mode_s *table_g = cirrus_get_modeentry(mode);
 427     if (table_g) {
 428         cirrus_switch_mode(table_g);
 429         if (!(flags & MF_LINEARFB))
 430             cirrus_enable_16k_granularity();
 431         if (!(flags & MF_NOCLEARMEM))
 432             cirrus_clear_vram(0);
 433         SET_BDA(video_mode, mode);
 434         SET_BDA(vbe_mode, mode | flags);
 435         return 0;
 436     }
 437     cirrus_switch_mode(&mode_switchback);
 438     dprintf(1, "cirrus mode switch regular\n");
 439     return stdvga_set_mode(mode, flags);
 440 }
 441
 442 static int
 443 cirrus_check(void)
 444 {
 445     outw(0x9206, VGAREG_SEQU_ADDRESS);
 446     return inb(VGAREG_SEQU_DATA) == 0x12;
 447 }
 448
 449
 450 /****************************************************************
 451  * extbios
 452  ****************************************************************/
 453
 454 static void
 455 cirrus_extbios_80h(struct bregs *regs)
 456 {
 457     u16 crtc_addr = stdvga_get_crtc();
 458     outb(0x27, crtc_addr);
 459     u8 v = inb(crtc_addr + 1);
 460     if (v == 0xa0)
 461         // 5430
 462         regs->ax = 0x0032;
 463     else if (v == 0xb8)
 464         // 5446
 465         regs->ax = 0x0039;
 466     else
 467         regs->ax = 0x00ff;
 468     regs->bx = 0x00;
 469     return;
 470 }
 471
 472 static void
 473 cirrus_extbios_81h(struct bregs *regs)
 474 {
 475     // XXX
 476     regs->ax = 0x0100;
 477 }
 478
 479 static void
 480 cirrus_extbios_82h(struct bregs *regs)
 481 {
 482     u16 crtc_addr = stdvga_get_crtc();
 483     outb(0x27, crtc_addr);
 484     regs->al = inb(crtc_addr + 1) & 0x03;
 485     regs->ah = 0xAF;
 486 }
 487
 488 static void
 489 cirrus_extbios_85h(struct bregs *regs)
 490 {
 491     regs->al = cirrus_get_memsize();
 492 }
 493
 494 static void
 495 cirrus_extbios_9Ah(struct bregs *regs)
 496 {
 497     regs->ax = 0x4060;
 498     regs->cx = 0x1132;
 499 }
 500
 501 extern void a0h_callback(void);
 502 ASM16(
 503     // fatal: not implemented yet
 504     "a0h_callback:"
 505     "cli\n"
 506     "hlt\n"
 507     "retf");
 508
 509 static void
 510 cirrus_extbios_A0h(struct bregs *regs)
 511 {
 512     struct cirrus_mode_s *table_g = cirrus_get_modeentry(regs->al & 0x7f);
 513     regs->ah = (table_g ? 1 : 0);
 514     regs->si = 0xffff;
 515     regs->di = regs->ds = regs->es = regs->bx = (u32)a0h_callback;
 516 }
 517
 518 static void
 519 cirrus_extbios_A1h(struct bregs *regs)
 520 {
 521     regs->bx = 0x0e00; // IBM 8512/8513, color
 522 }
 523
 524 static void
 525 cirrus_extbios_A2h(struct bregs *regs)
 526 {
 527     regs->al = 0x07; // HSync 31.5 - 64.0 kHz
 528 }
 529
 530 static void
 531 cirrus_extbios_AEh(struct bregs *regs)
 532 {
 533     regs->al = 0x01; // High Refresh 75Hz
 534 }
 535
 536 void
 537 cirrus_extbios(struct bregs *regs)
 538 {
 539     // XXX - regs->bl < 0x80 or > 0xaf call regular handlers.
 540     switch (regs->bl) {
 541     case 0x80: cirrus_extbios_80h(regs); break;
 542     case 0x81: cirrus_extbios_81h(regs); break;
 543     case 0x82: cirrus_extbios_82h(regs); break;
 544     case 0x85: cirrus_extbios_85h(regs); break;
 545     case 0x9a: cirrus_extbios_9Ah(regs); break;
 546     case 0xa0: cirrus_extbios_A0h(regs); break;
 547     case 0xa1: cirrus_extbios_A1h(regs); break;
 548     case 0xa2: cirrus_extbios_A2h(regs); break;
 549     case 0xae: cirrus_extbios_AEh(regs); break;
 550     default: break;
 551     }
 552 }
 553
 554
 555 /****************************************************************
 556  * vesa calls
 557  ****************************************************************/
 558
 559 void
 560 clext_list_modes(u16 seg, u16 *dest, u16 *last)
 561 {
 562     int i;
 563     for (i=0; i<ARRAY_SIZE(cirrus_vesa_modelist) && dest<last; i++) {
 564         SET_FARVAR(seg, *dest, GET_GLOBAL(cirrus_vesa_modelist[i].vesamode));
 565         dest++;
 566     }
 567     stdvga_list_modes(seg, dest, last);
 568 }
 569
 570 static u8
 571 cirrus_get_bpp_bytes(void)
 572 {
 573     outb(0x07, VGAREG_SEQU_ADDRESS);
 574     u8 v = inb(VGAREG_SEQU_DATA) & 0x0e;
 575     if (v == 0x06)
 576         v &= 0x02;
 577     v >>= 1;
 578     if (v != 0x04)
 579         v++;
 580     return v;
 581 }
 582
 583 static void
 584 cirrus_set_line_offset(u16 new_line_offset)
 585 {
 586     new_line_offset /= 8;
 587     u16 crtc_addr = stdvga_get_crtc();
 588     outb(0x13, crtc_addr);
 589     outb(new_line_offset, crtc_addr + 1);
 590
 591     outb(0x1b, crtc_addr);
 592     u8 v = inb(crtc_addr + 1);
 593     outb(((new_line_offset & 0x100) >> 4) | (v & 0xef), crtc_addr + 1);
 594 }
 595
 596 static u16
 597 cirrus_get_line_offset(void)
 598 {
 599     u16 crtc_addr = stdvga_get_crtc();
 600     outb(0x13, crtc_addr);
 601     u8 reg13 = inb(crtc_addr + 1);
 602     outb(0x1b, crtc_addr);
 603     u8 reg1b = inb(crtc_addr + 1);
 604
 605     return (((reg1b & 0x10) << 4) + reg13) * 8;
 606 }
 607
 608 static void
 609 cirrus_set_start_addr(u32 addr)
 610 {
 611     u16 crtc_addr = stdvga_get_crtc();
 612     outb(0x0d, crtc_addr);
 613     outb(addr, crtc_addr + 1);
 614
 615     outb(0x0c, crtc_addr);
 616     outb(addr>>8, crtc_addr + 1);
 617
 618     outb(0x1d, crtc_addr);
 619     u8 v = inb(crtc_addr + 1);
 620     outb(((addr & 0x0800) >> 4) | (v & 0x7f), crtc_addr + 1);
 621
 622     outb(0x1b, crtc_addr);
 623     v = inb(crtc_addr + 1);
 624     outb(((addr & 0x0100) >> 8) | ((addr & 0x0600) >> 7) | (v & 0xf2)
 625          , crtc_addr + 1);
 626 }
 627
 628 static u32
 629 cirrus_get_start_addr(void)
 630 {
 631     u16 crtc_addr = stdvga_get_crtc();
 632     outb(0x0c, crtc_addr);
 633     u8 b2 = inb(crtc_addr + 1);
 634
 635     outb(0x0d, crtc_addr);
 636     u8 b1 = inb(crtc_addr + 1);
 637
 638     outb(0x1b, crtc_addr);
 639     u8 b3 = inb(crtc_addr + 1);
 640
 641     outb(0x1d, crtc_addr);
 642     u8 b4 = inb(crtc_addr + 1);
 643
 644     return (b1 | (b2<<8) | ((b3 & 0x01) << 16) | ((b3 & 0x0c) << 15)
 645             | ((b4 & 0x80) << 12));
 646 }
 647
 648 static void
 649 cirrus_vesa_05h(struct bregs *regs)
 650 {
 651     if (regs->bl > 1)
 652         goto fail;
 653     if (regs->bh == 0) {
 654         // set mempage
 655         if (regs->dx >= 0x100)
 656             goto fail;
 657         outw((regs->dx << 8) | (regs->bl + 9), VGAREG_GRDC_ADDRESS);
 658     } else if (regs->bh == 1) {
 659         // get mempage
 660         outb(regs->bl + 9, VGAREG_GRDC_ADDRESS);
 661         regs->dx = inb(VGAREG_GRDC_DATA);
 662     } else
 663         goto fail;
 664
 665     regs->ax = 0x004f;
 666     return;
 667 fail:
 668     regs->ax = 0x014f;
 669 }
 670
 671 static void
 672 cirrus_vesa_06h(struct bregs *regs)
 673 {
 674     if (regs->bl > 2) {
 675         regs->ax = 0x0100;
 676         return;
 677     }
 678
 679     if (regs->bl == 0x00) {
 680         cirrus_set_line_offset(cirrus_get_bpp_bytes() * regs->cx);
 681     } else if (regs->bl == 0x02) {
 682         cirrus_set_line_offset(regs->cx);
 683     }
 684
 685     u32 v = cirrus_get_line_offset();
 686     regs->cx = v / cirrus_get_bpp_bytes();
 687     regs->bx = v;
 688     regs->dx = (cirrus_get_memsize() * 64 * 1024) / v;
 689     regs->ax = 0x004f;
 690 }
 691
 692 static void
 693 cirrus_vesa_07h(struct bregs *regs)
 694 {
 695     if (regs->bl == 0x80 || regs->bl == 0x00) {
 696         u32 addr = (cirrus_get_bpp_bytes() * regs->cx
 697                     + cirrus_get_line_offset() * regs->dx);
 698         cirrus_set_start_addr(addr / 4);
 699     } else if (regs->bl == 0x01) {
 700         u32 addr = cirrus_get_start_addr() * 4;
 701         u32 linelength = cirrus_get_line_offset();
 702         regs->dx = addr / linelength;
 703         regs->cx = (addr % linelength) / cirrus_get_bpp_bytes();
 704     } else {
 705         regs->ax = 0x0100;
 706         return;
 707     }
 708
 709     regs->ax = 0x004f;
 710 }
 711
 712 static void
 713 cirrus_vesa_10h(struct bregs *regs)
 714 {
 715     if (regs->bl == 0x00) {
 716         regs->bx = 0x0f30;
 717         regs->ax = 0x004f;
 718         return;
 719     }
 720     if (regs->bl == 0x01) {
 721         SET_BDA(vbe_flag, regs->bh);
 722         regs->ax = 0x004f;
 723         return;
 724     }
 725     if (regs->bl == 0x02) {
 726         regs->bh = GET_BDA(vbe_flag);
 727         regs->ax = 0x004f;
 728         return;
 729     }
 730     regs->ax = 0x014f;
 731 }
 732
 733 static void
 734 cirrus_vesa_not_handled(struct bregs *regs)
 735 {
 736     debug_stub(regs);
 737     regs->ax = 0x014f;
 738 }
 739
 740 void
 741 cirrus_vesa(struct bregs *regs)
 742 {
 743     switch (regs->al) {
 744     case 0x05: cirrus_vesa_05h(regs); break;
 745     case 0x06: cirrus_vesa_06h(regs); break;
 746     case 0x07: cirrus_vesa_07h(regs); break;
 747     case 0x10: cirrus_vesa_10h(regs); break;
 748     default:   cirrus_vesa_not_handled(regs); break;
 749     }
 750 }
 751
 752
 753 /****************************************************************
 754  * init
 755  ****************************************************************/
 756
 757 int
 758 clext_init(void)
 759 {
 760     int ret = stdvga_init();
 761     if (ret)
 762         return ret;
 763
 764     dprintf(1, "cirrus init\n");
 765     if (! cirrus_check())
 766         return -1;
 767     dprintf(1, "cirrus init 2\n");
 768
 769     u16 totalmem = cirrus_get_memsize();
 770     SET_VGA(VBE_total_memory, totalmem * 64 * 1024);
 771     SET_VGA(VBE_win_granularity, 16);
 772
 773     // memory setup
 774     outb(0x0f, VGAREG_SEQU_ADDRESS);
 775     u8 v = inb(VGAREG_SEQU_DATA);
 776     outb(((v & 0x18) << 8) | 0x0a, VGAREG_SEQU_ADDRESS);
 777     // set vga mode
 778     outw(0x0007, VGAREG_SEQU_ADDRESS);
 779     // reset bitblt
 780     outw(0x0431, VGAREG_GRDC_ADDRESS);
 781     outw(0x0031, VGAREG_GRDC_ADDRESS);
 782
 783     return 0;
 784 }