1 // QEMU Cirrus CLGD 54xx VGABIOS Extension.
3 // Copyright (C) 2009 Kevin O'Connor <kevin@koconnor.net>
4 // Copyright (c) 2004 Makoto Suzuki (suzu)
6 // This file may be distributed under the terms of the GNU LGPLv3 license.
8 #include "vgabios.h" // cirrus_init
9 #include "biosvar.h" // GET_GLOBAL
10 #include "util.h" // dprintf
11 #include "bregs.h" // struct bregs
12 #include "vbe.h" // struct vbe_info
13 #include "stdvga.h" // VGAREG_SEQU_ADDRESS
16 /****************************************************************
18 ****************************************************************/
20 struct cirrus_mode_s {
27 u16 hidden_dac; /* 0x3c6 */
29 u16 *graph; /* 0x3ce */
30 u16 *crtc; /* 0x3d4 */
46 static u16 cseq_vga[] VAR16 = {0x0007,0xffff};
47 static u16 cgraph_vga[] VAR16 = {0x0009,0x000a,0x000b,0xffff};
48 static u16 ccrtc_vga[] VAR16 = {0x001a,0x001b,0x001d,0xffff};
51 static u16 cgraph_svgacolor[] VAR16 = {
52 0x0000,0x0001,0x0002,0x0003,0x0004,0x4005,0x0506,0x0f07,0xff08,
57 static u16 cseq_640x480x8[] VAR16 = {
58 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
59 0x580b,0x580c,0x580d,0x580e,
61 0x331b,0x331c,0x331d,0x331e,
64 static u16 ccrtc_640x480x8[] VAR16 = {
66 0x5f00,0x4f01,0x4f02,0x8003,0x5204,0x1e05,0x0b06,0x3e07,
68 0xea10,0xdf12,0x5013,0x4014,0xdf15,0x0b16,0xc317,0xff18,
73 static u16 cseq_640x480x16[] VAR16 = {
74 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1707,
75 0x580b,0x580c,0x580d,0x580e,
77 0x331b,0x331c,0x331d,0x331e,
80 static u16 ccrtc_640x480x16[] VAR16 = {
82 0x5f00,0x4f01,0x4f02,0x8003,0x5204,0x1e05,0x0b06,0x3e07,
84 0xea10,0xdf12,0xa013,0x4014,0xdf15,0x0b16,0xc317,0xff18,
89 static u16 cseq_640x480x24[] VAR16 = {
90 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1507,
91 0x580b,0x580c,0x580d,0x580e,
93 0x331b,0x331c,0x331d,0x331e,
96 static u16 ccrtc_640x480x24[] VAR16 = {
98 0x5f00,0x4f01,0x4f02,0x8003,0x5204,0x1e05,0x0b06,0x3e07,
100 0xea10,0xdf12,0x0013,0x4014,0xdf15,0x0b16,0xc317,0xff18,
101 0x001a,0x321b,0x001d,
105 static u16 cseq_800x600x8[] VAR16 = {
106 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
107 0x230b,0x230c,0x230d,0x230e,
108 0x0412,0x0013,0x2017,
109 0x141b,0x141c,0x141d,0x141e,
112 static u16 ccrtc_800x600x8[] VAR16 = {
113 0x2311,0x7d00,0x6301,0x6302,0x8003,0x6b04,0x1a05,0x9806,0xf007,
114 0x6009,0x000c,0x000d,
115 0x7d10,0x5712,0x6413,0x4014,0x5715,0x9816,0xc317,0xff18,
116 0x001a,0x221b,0x001d,
120 static u16 cseq_800x600x16[] VAR16 = {
121 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1707,
122 0x230b,0x230c,0x230d,0x230e,
123 0x0412,0x0013,0x2017,
124 0x141b,0x141c,0x141d,0x141e,
127 static u16 ccrtc_800x600x16[] VAR16 = {
128 0x2311,0x7d00,0x6301,0x6302,0x8003,0x6b04,0x1a05,0x9806,0xf007,
129 0x6009,0x000c,0x000d,
130 0x7d10,0x5712,0xc813,0x4014,0x5715,0x9816,0xc317,0xff18,
131 0x001a,0x221b,0x001d,
135 static u16 cseq_800x600x24[] VAR16 = {
136 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1507,
137 0x230b,0x230c,0x230d,0x230e,
138 0x0412,0x0013,0x2017,
139 0x141b,0x141c,0x141d,0x141e,
142 static u16 ccrtc_800x600x24[] VAR16 = {
143 0x2311,0x7d00,0x6301,0x6302,0x8003,0x6b04,0x1a05,0x9806,0xf007,
144 0x6009,0x000c,0x000d,
145 0x7d10,0x5712,0x2c13,0x4014,0x5715,0x9816,0xc317,0xff18,
146 0x001a,0x321b,0x001d,
150 static u16 cseq_1024x768x8[] VAR16 = {
151 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
152 0x760b,0x760c,0x760d,0x760e,
153 0x0412,0x0013,0x2017,
154 0x341b,0x341c,0x341d,0x341e,
157 static u16 ccrtc_1024x768x8[] VAR16 = {
158 0x2911,0xa300,0x7f01,0x7f02,0x8603,0x8304,0x9405,0x2406,0xf507,
159 0x6009,0x000c,0x000d,
160 0x0310,0xff12,0x8013,0x4014,0xff15,0x2416,0xc317,0xff18,
161 0x001a,0x221b,0x001d,
165 static u16 cseq_1024x768x16[] VAR16 = {
166 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1707,
167 0x760b,0x760c,0x760d,0x760e,
168 0x0412,0x0013,0x2017,
169 0x341b,0x341c,0x341d,0x341e,
172 static u16 ccrtc_1024x768x16[] VAR16 = {
173 0x2911,0xa300,0x7f01,0x7f02,0x8603,0x8304,0x9405,0x2406,0xf507,
174 0x6009,0x000c,0x000d,
175 0x0310,0xff12,0x0013,0x4014,0xff15,0x2416,0xc317,0xff18,
176 0x001a,0x321b,0x001d,
180 static u16 cseq_1024x768x24[] VAR16 = {
181 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1507,
182 0x760b,0x760c,0x760d,0x760e,
183 0x0412,0x0013,0x2017,
184 0x341b,0x341c,0x341d,0x341e,
187 static u16 ccrtc_1024x768x24[] VAR16 = {
188 0x2911,0xa300,0x7f01,0x7f02,0x8603,0x8304,0x9405,0x2406,0xf507,
189 0x6009,0x000c,0x000d,
190 0x0310,0xff12,0x8013,0x4014,0xff15,0x2416,0xc317,0xff18,
191 0x001a,0x321b,0x001d,
195 static u16 cseq_1280x1024x8[] VAR16 = {
196 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
197 0x760b,0x760c,0x760d,0x760e,
198 0x0412,0x0013,0x2017,
199 0x341b,0x341c,0x341d,0x341e,
202 static u16 ccrtc_1280x1024x8[] VAR16 = {
203 0x2911,0xc300,0x9f01,0x9f02,0x8603,0x8304,0x9405,0x2406,0xf707,
204 0x6009,0x000c,0x000d,
205 0x0310,0xff12,0xa013,0x4014,0xff15,0x2416,0xc317,0xff18,
206 0x001a,0x221b,0x001d,
210 static u16 cseq_1280x1024x16[] VAR16 = {
211 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1707,
212 0x760b,0x760c,0x760d,0x760e,
213 0x0412,0x0013,0x2017,
214 0x341b,0x341c,0x341d,0x341e,
217 static u16 ccrtc_1280x1024x16[] VAR16 = {
218 0x2911,0xc300,0x9f01,0x9f02,0x8603,0x8304,0x9405,0x2406,0xf707,
219 0x6009,0x000c,0x000d,
220 0x0310,0xff12,0x4013,0x4014,0xff15,0x2416,0xc317,0xff18,
221 0x001a,0x321b,0x001d,
226 static u16 cseq_1600x1200x8[] VAR16 = {
227 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
228 0x760b,0x760c,0x760d,0x760e,
229 0x0412,0x0013,0x2017,
230 0x341b,0x341c,0x341d,0x341e,
233 static u16 ccrtc_1600x1200x8[] VAR16 = {
234 0x2911,0xc300,0x9f01,0x9f02,0x8603,0x8304,0x9405,0x2406,0xf707,
235 0x6009,0x000c,0x000d,
236 0x0310,0xff12,0xa013,0x4014,0xff15,0x2416,0xc317,0xff18,
237 0x001a,0x221b,0x001d,
241 static struct cirrus_mode_s cirrus_modes[] VAR16 = {
242 {0x5f,640,480,8,0x00,
243 cseq_640x480x8,cgraph_svgacolor,ccrtc_640x480x8,8,
245 {0x64,640,480,16,0xe1,
246 cseq_640x480x16,cgraph_svgacolor,ccrtc_640x480x16,16,
248 {0x66,640,480,15,0xf0,
249 cseq_640x480x16,cgraph_svgacolor,ccrtc_640x480x16,16,
250 6,5,10,5,5,5,0,1,15},
251 {0x71,640,480,24,0xe5,
252 cseq_640x480x24,cgraph_svgacolor,ccrtc_640x480x24,24,
255 {0x5c,800,600,8,0x00,
256 cseq_800x600x8,cgraph_svgacolor,ccrtc_800x600x8,8,
258 {0x65,800,600,16,0xe1,
259 cseq_800x600x16,cgraph_svgacolor,ccrtc_800x600x16,16,
261 {0x67,800,600,15,0xf0,
262 cseq_800x600x16,cgraph_svgacolor,ccrtc_800x600x16,16,
263 6,5,10,5,5,5,0,1,15},
265 {0x60,1024,768,8,0x00,
266 cseq_1024x768x8,cgraph_svgacolor,ccrtc_1024x768x8,8,
268 {0x74,1024,768,16,0xe1,
269 cseq_1024x768x16,cgraph_svgacolor,ccrtc_1024x768x16,16,
271 {0x68,1024,768,15,0xf0,
272 cseq_1024x768x16,cgraph_svgacolor,ccrtc_1024x768x16,16,
273 6,5,10,5,5,5,0,1,15},
275 {0x78,800,600,24,0xe5,
276 cseq_800x600x24,cgraph_svgacolor,ccrtc_800x600x24,24,
278 {0x79,1024,768,24,0xe5,
279 cseq_1024x768x24,cgraph_svgacolor,ccrtc_1024x768x24,24,
282 {0x6d,1280,1024,8,0x00,
283 cseq_1280x1024x8,cgraph_svgacolor,ccrtc_1280x1024x8,8,
285 {0x69,1280,1024,15,0xf0,
286 cseq_1280x1024x16,cgraph_svgacolor,ccrtc_1280x1024x16,16,
287 6,5,10,5,5,5,0,1,15},
288 {0x75,1280,1024,16,0xe1,
289 cseq_1280x1024x16,cgraph_svgacolor,ccrtc_1280x1024x16,16,
292 {0x7b,1600,1200,8,0x00,
293 cseq_1600x1200x8,cgraph_svgacolor,ccrtc_1600x1200x8,8,
296 {0xfe,0,0,0,0,cseq_vga,cgraph_vga,ccrtc_vga,0,
297 0xff,0,0,0,0,0,0,0,0},
301 /****************************************************************
303 ****************************************************************/
305 static struct cirrus_mode_s *
306 cirrus_get_modeentry(u8 mode)
308 struct cirrus_mode_s *table_g = cirrus_modes;
309 while (table_g < &cirrus_modes[ARRAY_SIZE(cirrus_modes)]) {
310 u16 tmode = GET_GLOBAL(table_g->mode);
319 cirrus_switch_mode_setregs(u16 *data, u16 port)
322 u16 val = GET_GLOBAL(*data);
331 cirrus_switch_mode(struct cirrus_mode_s *table)
333 // Unlock cirrus special
334 outw(0x1206, VGAREG_SEQU_ADDRESS);
335 cirrus_switch_mode_setregs(GET_GLOBAL(table->seq), VGAREG_SEQU_ADDRESS);
336 cirrus_switch_mode_setregs(GET_GLOBAL(table->graph), VGAREG_GRDC_ADDRESS);
337 cirrus_switch_mode_setregs(GET_GLOBAL(table->crtc), stdvga_get_crtc());
339 outb(0x00, VGAREG_PEL_MASK);
340 inb(VGAREG_PEL_MASK);
341 inb(VGAREG_PEL_MASK);
342 inb(VGAREG_PEL_MASK);
343 inb(VGAREG_PEL_MASK);
344 outb(GET_GLOBAL(table->hidden_dac), VGAREG_PEL_MASK);
345 outb(0xff, VGAREG_PEL_MASK);
347 u8 vesacolortype = GET_GLOBAL(table->vesacolortype);
348 u8 v = stdvga_get_single_palette_reg(0x10) & 0xfe;
349 if (vesacolortype == 3)
351 else if (vesacolortype)
353 stdvga_set_single_palette_reg(0x10, v);
357 cirrus_get_memsize(void)
359 // get DRAM band width
360 outb(0x0f, VGAREG_SEQU_ADDRESS);
361 u8 v = inb(VGAREG_SEQU_DATA);
362 u8 x = (v >> 3) & 0x03;
374 cirrus_enable_16k_granularity(void)
376 outb(0x0b, VGAREG_GRDC_ADDRESS);
377 u8 v = inb(VGAREG_GRDC_DATA);
378 outb(v | 0x20, VGAREG_GRDC_DATA);
382 cirrus_clear_vram(u16 param)
384 cirrus_enable_16k_granularity();
385 u8 count = cirrus_get_memsize() * 4;
387 for (i=0; i<count; i++) {
388 outw((i<<8) | 0x09, VGAREG_GRDC_ADDRESS);
389 memset16_far(SEG_GRAPH, 0, param, 16 * 1024);
391 outw(0x0009, VGAREG_GRDC_ADDRESS);
395 cirrus_set_video_mode(u8 mode, u8 noclearmem)
397 dprintf(1, "cirrus mode %d\n", mode);
398 SET_BDA(vbe_mode, 0);
399 struct cirrus_mode_s *table_g = cirrus_get_modeentry(mode);
401 cirrus_switch_mode(table_g);
403 cirrus_clear_vram(0xffff);
404 SET_BDA(video_mode, mode);
407 table_g = cirrus_get_modeentry(0xfe);
408 cirrus_switch_mode(table_g);
409 dprintf(1, "cirrus mode switch regular\n");
416 outw(0x9206, VGAREG_SEQU_ADDRESS);
417 return inb(VGAREG_SEQU_DATA) == 0x12;
421 /****************************************************************
423 ****************************************************************/
426 cirrus_extbios_80h(struct bregs *regs)
428 u16 crtc_addr = stdvga_get_crtc();
429 outb(0x27, crtc_addr);
430 u8 v = inb(crtc_addr + 1);
444 cirrus_extbios_81h(struct bregs *regs)
451 cirrus_extbios_82h(struct bregs *regs)
453 u16 crtc_addr = stdvga_get_crtc();
454 outb(0x27, crtc_addr);
455 regs->al = inb(crtc_addr + 1) & 0x03;
460 cirrus_extbios_85h(struct bregs *regs)
462 regs->al = cirrus_get_memsize();
466 cirrus_extbios_9Ah(struct bregs *regs)
472 extern void a0h_callback(void);
474 // fatal: not implemented yet
481 cirrus_extbios_A0h(struct bregs *regs)
483 struct cirrus_mode_s *table_g = cirrus_get_modeentry(regs->al & 0x7f);
484 regs->ah = (table_g ? 1 : 0);
486 regs->di = regs->ds = regs->es = regs->bx = (u32)a0h_callback;
490 cirrus_extbios_A1h(struct bregs *regs)
492 regs->bx = 0x0e00; // IBM 8512/8513, color
496 cirrus_extbios_A2h(struct bregs *regs)
498 regs->al = 0x07; // HSync 31.5 - 64.0 kHz
502 cirrus_extbios_AEh(struct bregs *regs)
504 regs->al = 0x01; // High Refresh 75Hz
508 cirrus_extbios(struct bregs *regs)
510 // XXX - regs->bl < 0x80 or > 0xaf call regular handlers.
512 case 0x80: cirrus_extbios_80h(regs); break;
513 case 0x81: cirrus_extbios_81h(regs); break;
514 case 0x82: cirrus_extbios_82h(regs); break;
515 case 0x85: cirrus_extbios_85h(regs); break;
516 case 0x9a: cirrus_extbios_9Ah(regs); break;
517 case 0xa0: cirrus_extbios_A0h(regs); break;
518 case 0xa1: cirrus_extbios_A1h(regs); break;
519 case 0xa2: cirrus_extbios_A2h(regs); break;
520 case 0xae: cirrus_extbios_AEh(regs); break;
526 /****************************************************************
528 ****************************************************************/
532 } cirrus_vesa_modelist[] VAR16 = {
566 cirrus_vesamode_to_mode(u16 vesamode)
569 for (i=0; i<ARRAY_SIZE(cirrus_vesa_modelist); i++)
570 if (GET_GLOBAL(cirrus_vesa_modelist[i].vesamode) == vesamode)
571 return GET_GLOBAL(cirrus_vesa_modelist[i].mode);
576 cirrus_get_bpp_bytes(void)
578 outb(0x07, VGAREG_SEQU_ADDRESS);
579 u8 v = inb(VGAREG_SEQU_DATA) & 0x0e;
589 cirrus_set_line_offset(u16 new_line_offset)
591 u16 crtc_addr = stdvga_get_crtc();
592 outb(0x13, crtc_addr);
593 outb(new_line_offset / 8, crtc_addr + 1);
595 outb(0x1b, crtc_addr);
596 u8 v = inb(crtc_addr + 1);
597 outb((((new_line_offset / 8) & 0x100) >> 4) | (v & 0xef), crtc_addr + 1);
601 cirrus_get_line_offset(void)
603 u16 crtc_addr = stdvga_get_crtc();
604 outb(0x13, crtc_addr);
605 u8 reg13 = inb(crtc_addr + 1);
606 outb(0x1b, crtc_addr);
607 u8 reg1b = inb(crtc_addr + 1);
609 return (((reg1b << 4) & 0x100) + reg13) * 8;
613 cirrus_get_line_offset_entry(struct cirrus_mode_s *table_g)
615 u16 *crtc = GET_GLOBAL(table_g->crtc);
620 reg13 = GET_GLOBAL(*c);
621 if ((reg13 & 0xff) == 0x13)
630 reg1b = GET_GLOBAL(*c);
631 if ((reg1b & 0xff) == 0x1b)
637 return (((reg1b << 4) & 0x100) + reg13) * 8;
641 cirrus_set_start_addr(u32 addr)
643 u16 crtc_addr = stdvga_get_crtc();
644 outb(0x0d, crtc_addr);
645 outb(addr, crtc_addr + 1);
647 outb(0x0c, crtc_addr);
648 outb(addr>>8, crtc_addr + 1);
650 outb(0x1d, crtc_addr);
651 u8 v = inb(crtc_addr + 1);
652 outb(((addr & 0x0800) >> 4) | (v & 0x7f), crtc_addr + 1);
654 outb(0x1b, crtc_addr);
655 v = inb(crtc_addr + 1);
656 outb(((addr & 0x0100) >> 8) | ((addr & 0x0600) >> 7) | (v & 0xf2)
661 cirrus_get_start_addr(void)
663 u16 crtc_addr = stdvga_get_crtc();
664 outb(0x0c, crtc_addr);
665 u8 b2 = inb(crtc_addr + 1);
667 outb(0x0d, crtc_addr);
668 u8 b1 = inb(crtc_addr + 1);
670 outb(0x1b, crtc_addr);
671 u8 b3 = inb(crtc_addr + 1);
673 outb(0x1d, crtc_addr);
674 u8 b4 = inb(crtc_addr + 1);
676 return (b1 | (b2<<8) | ((b3 & 0x01) << 16) | ((b3 & 0x0c) << 15)
677 | ((b4 & 0x80) << 12));
681 cirrus_vesa_00h(struct bregs *regs)
684 struct vbe_info *info = (void*)(regs->di+0);
686 if (GET_FARVAR(seg, info->signature) == VBE2_SIGNATURE) {
687 SET_FARVAR(seg, info->oem_revision, 0x0100);
688 SET_FARVAR(seg, info->oem_vendor_string,
689 SEGOFF(get_global_seg(), (u32)VBE_VENDOR_STRING));
690 SET_FARVAR(seg, info->oem_product_string,
691 SEGOFF(get_global_seg(), (u32)VBE_PRODUCT_STRING));
692 SET_FARVAR(seg, info->oem_revision_string,
693 SEGOFF(get_global_seg(), (u32)VBE_REVISION_STRING));
695 SET_FARVAR(seg, info->signature, VESA_SIGNATURE);
697 SET_FARVAR(seg, info->version, 0x0200);
699 SET_FARVAR(seg, info->oem_string
700 , SEGOFF(get_global_seg(), (u32)VBE_OEM_STRING));
701 SET_FARVAR(seg, info->capabilities, 0);
702 SET_FARVAR(seg, info->total_memory, cirrus_get_memsize());
704 u16 *destmode = (void*)info->reserved;
705 SET_FARVAR(seg, info->video_mode, SEGOFF(seg, (u32)destmode));
707 for (i=0; i<ARRAY_SIZE(cirrus_vesa_modelist); i++)
708 SET_FARVAR(seg, destmode[i]
709 , GET_GLOBAL(cirrus_vesa_modelist[i].vesamode));
710 SET_FARVAR(seg, destmode[i], 0xffff);
715 static u32 cirrus_lfb_addr VAR16;
718 cirrus_vesa_01h(struct bregs *regs)
720 u16 mode = cirrus_vesamode_to_mode(regs->cx & 0x3fff);
725 struct cirrus_mode_s *table_g = cirrus_get_modeentry(mode);
726 u32 lfb = GET_GLOBAL(cirrus_lfb_addr); // XXX
727 if ((regs->cx & 0x4000) && !lfb) {
733 struct vbe_mode_info *info = (void*)(regs->di+0);
734 memset_far(seg, info, 0, sizeof(*info));
736 SET_FARVAR(seg, info->mode_attributes, lfb ? 0xbb : 0x3b);
737 SET_FARVAR(seg, info->winA_attributes, 0x07);
738 SET_FARVAR(seg, info->winB_attributes, 0);
739 SET_FARVAR(seg, info->win_granularity, 16);
740 SET_FARVAR(seg, info->win_size, 64);
741 SET_FARVAR(seg, info->winA_seg, SEG_GRAPH);
742 SET_FARVAR(seg, info->winB_seg, 0x0);
743 SET_FARVAR(seg, info->win_func_ptr.segoff, 0x0); // XXX
744 u16 linesize = cirrus_get_line_offset_entry(table_g);
745 SET_FARVAR(seg, info->bytes_per_scanline, linesize);
746 SET_FARVAR(seg, info->xres, GET_GLOBAL(table_g->width));
747 u16 height = GET_GLOBAL(table_g->height);
748 SET_FARVAR(seg, info->yres, height);
749 SET_FARVAR(seg, info->xcharsize, 8);
750 SET_FARVAR(seg, info->ycharsize, 16);
751 SET_FARVAR(seg, info->planes, 1);
752 SET_FARVAR(seg, info->bits_per_pixel, GET_GLOBAL(table_g->depth));
753 SET_FARVAR(seg, info->banks, 1);
754 SET_FARVAR(seg, info->mem_model, GET_GLOBAL(table_g->vesacolortype));
755 SET_FARVAR(seg, info->bank_size, 0);
757 int pages = (cirrus_get_memsize() * 64 * 1024) / (height * linesize);
758 SET_FARVAR(seg, info->pages, pages - 1);
759 SET_FARVAR(seg, info->reserved0, 0);
761 SET_FARVAR(seg, info->red_size, GET_GLOBAL(table_g->vesaredmask));
762 SET_FARVAR(seg, info->red_pos, GET_GLOBAL(table_g->vesaredpos));
763 SET_FARVAR(seg, info->green_size, GET_GLOBAL(table_g->vesagreenmask));
764 SET_FARVAR(seg, info->green_pos, GET_GLOBAL(table_g->vesagreenpos));
765 SET_FARVAR(seg, info->blue_size, GET_GLOBAL(table_g->vesabluemask));
766 SET_FARVAR(seg, info->blue_pos, GET_GLOBAL(table_g->vesabluepos));
767 SET_FARVAR(seg, info->alpha_size, GET_GLOBAL(table_g->vesareservedmask));
768 SET_FARVAR(seg, info->alpha_pos, GET_GLOBAL(table_g->vesareservedpos));
769 u8 directcolor_info = GET_GLOBAL(table_g->bitsperpixel) <= 8;
770 SET_FARVAR(seg, info->directcolor_info, directcolor_info);
772 SET_FARVAR(seg, info->phys_base, lfb);
778 cirrus_vesa_02h(struct bregs *regs)
780 if (regs->bx & 0x3e00) {
784 if ((regs->bx & 0x1ff) < 0x100) {
785 // XXX - call legacy mode switch
790 u16 mode = cirrus_vesamode_to_mode(regs->cx & 0x3fff);
795 struct cirrus_mode_s *table_g = cirrus_get_modeentry(mode);
796 cirrus_switch_mode(table_g);
798 if (!(regs->bx & 0x4000))
799 cirrus_enable_16k_granularity();
800 if (!(regs->bx & 0x8000))
801 cirrus_clear_vram(0);
802 SET_BDA(video_mode, mode);
803 SET_BDA(vbe_mode, regs->bx);
809 cirrus_vesa_03h(struct bregs *regs)
811 u16 mode = GET_BDA(vbe_mode);
813 mode = GET_BDA(video_mode);
819 // XXX - add cirrus_vesa_05h_farentry to vgaentry.S
822 cirrus_vesa_05h(struct bregs *regs)
828 if (regs->dx >= 0x100)
830 outw((regs->dx << 8) | (regs->bl + 9), VGAREG_GRDC_ADDRESS);
831 } else if (regs->bh == 1) {
833 outb(regs->bl + 9, VGAREG_GRDC_ADDRESS);
834 regs->dx = inb(VGAREG_GRDC_DATA);
845 cirrus_vesa_06h(struct bregs *regs)
852 if (regs->bl == 0x00) {
853 cirrus_set_line_offset(cirrus_get_bpp_bytes() * regs->cx);
854 } else if (regs->bl == 0x02) {
855 cirrus_set_line_offset(regs->cx);
858 u32 v = cirrus_get_line_offset();
859 regs->cx = v / cirrus_get_bpp_bytes();
861 regs->dx = (cirrus_get_memsize() * 64 * 1024) / v;
866 cirrus_vesa_07h(struct bregs *regs)
868 if (regs->bl == 0x80 || regs->bl == 0x00) {
869 u32 addr = (cirrus_get_bpp_bytes() * regs->cx
870 + cirrus_get_line_offset() * regs->dx);
871 cirrus_set_start_addr(addr / 4);
872 } else if (regs->bl == 0x01) {
873 u32 addr = cirrus_get_start_addr() * 4;
874 u32 linelength = cirrus_get_line_offset();
875 regs->dx = addr / linelength;
876 regs->cx = (addr % linelength) / cirrus_get_bpp_bytes();
886 cirrus_vesa_10h(struct bregs *regs)
888 if (regs->bl == 0x00) {
893 if (regs->bl == 0x01) {
894 SET_BDA(vbe_flag, regs->bh);
898 if (regs->bl == 0x02) {
899 regs->bh = GET_BDA(vbe_flag);
907 cirrus_vesa_not_handled(struct bregs *regs)
914 cirrus_vesa(struct bregs *regs)
917 case 0x00: cirrus_vesa_00h(regs); break;
918 case 0x01: cirrus_vesa_01h(regs); break;
919 case 0x02: cirrus_vesa_02h(regs); break;
920 case 0x03: cirrus_vesa_03h(regs); break;
921 case 0x05: cirrus_vesa_05h(regs); break;
922 case 0x06: cirrus_vesa_06h(regs); break;
923 case 0x07: cirrus_vesa_07h(regs); break;
924 case 0x10: cirrus_vesa_10h(regs); break;
925 default: cirrus_vesa_not_handled(regs); break;
930 /****************************************************************
932 ****************************************************************/
937 dprintf(1, "cirrus init\n");
938 if (! cirrus_check())
940 dprintf(1, "cirrus init 2\n");
943 outb(0x0f, VGAREG_SEQU_ADDRESS);
944 u8 v = inb(VGAREG_SEQU_DATA);
945 outb(((v & 0x18) << 8) | 0x0a, VGAREG_SEQU_ADDRESS);
947 outw(0x0007, VGAREG_SEQU_ADDRESS);
949 outw(0x0431, VGAREG_GRDC_ADDRESS);
950 outw(0x0031, VGAREG_GRDC_ADDRESS);