1 // QEMU Cirrus CLGD 54xx VGABIOS Extension.
3 // Copyright (C) 2009 Kevin O'Connor <kevin@koconnor.net>
4 // Copyright (c) 2004 Makoto Suzuki (suzu)
6 // This file may be distributed under the terms of the GNU LGPLv3 license.
8 #include "clext.h" // clext_init
9 #include "vgabios.h" // VBE_VENDOR_STRING
10 #include "biosvar.h" // GET_GLOBAL
11 #include "util.h" // dprintf
12 #include "bregs.h" // struct bregs
13 #include "vbe.h" // struct vbe_info
14 #include "stdvga.h" // VGAREG_SEQU_ADDRESS
17 /****************************************************************
19 ****************************************************************/
21 struct cirrus_mode_s {
29 u16 hidden_dac; /* 0x3c6 */
31 u16 *graph; /* 0x3ce */
32 u16 *crtc; /* 0x3d4 */
47 static u16 cseq_vga[] VAR16 = {0x0007,0xffff};
48 static u16 cgraph_vga[] VAR16 = {0x0009,0x000a,0x000b,0xffff};
49 static u16 ccrtc_vga[] VAR16 = {0x001a,0x001b,0x001d,0xffff};
52 static u16 cgraph_svgacolor[] VAR16 = {
53 0x0000,0x0001,0x0002,0x0003,0x0004,0x4005,0x0506,0x0f07,0xff08,
58 static u16 cseq_640x480x8[] VAR16 = {
59 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
60 0x580b,0x580c,0x580d,0x580e,
62 0x331b,0x331c,0x331d,0x331e,
65 static u16 ccrtc_640x480x8[] VAR16 = {
67 0x5f00,0x4f01,0x4f02,0x8003,0x5204,0x1e05,0x0b06,0x3e07,
69 0xea10,0xdf12,0x5013,0x4014,0xdf15,0x0b16,0xc317,0xff18,
74 static u16 cseq_640x480x16[] VAR16 = {
75 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1707,
76 0x580b,0x580c,0x580d,0x580e,
78 0x331b,0x331c,0x331d,0x331e,
81 static u16 ccrtc_640x480x16[] VAR16 = {
83 0x5f00,0x4f01,0x4f02,0x8003,0x5204,0x1e05,0x0b06,0x3e07,
85 0xea10,0xdf12,0xa013,0x4014,0xdf15,0x0b16,0xc317,0xff18,
90 static u16 cseq_640x480x24[] VAR16 = {
91 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1507,
92 0x580b,0x580c,0x580d,0x580e,
94 0x331b,0x331c,0x331d,0x331e,
97 static u16 ccrtc_640x480x24[] VAR16 = {
99 0x5f00,0x4f01,0x4f02,0x8003,0x5204,0x1e05,0x0b06,0x3e07,
100 0x4009,0x000c,0x000d,
101 0xea10,0xdf12,0x0013,0x4014,0xdf15,0x0b16,0xc317,0xff18,
102 0x001a,0x321b,0x001d,
106 static u16 cseq_800x600x8[] VAR16 = {
107 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
108 0x230b,0x230c,0x230d,0x230e,
109 0x0412,0x0013,0x2017,
110 0x141b,0x141c,0x141d,0x141e,
113 static u16 ccrtc_800x600x8[] VAR16 = {
114 0x2311,0x7d00,0x6301,0x6302,0x8003,0x6b04,0x1a05,0x9806,0xf007,
115 0x6009,0x000c,0x000d,
116 0x7d10,0x5712,0x6413,0x4014,0x5715,0x9816,0xc317,0xff18,
117 0x001a,0x221b,0x001d,
121 static u16 cseq_800x600x16[] VAR16 = {
122 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1707,
123 0x230b,0x230c,0x230d,0x230e,
124 0x0412,0x0013,0x2017,
125 0x141b,0x141c,0x141d,0x141e,
128 static u16 ccrtc_800x600x16[] VAR16 = {
129 0x2311,0x7d00,0x6301,0x6302,0x8003,0x6b04,0x1a05,0x9806,0xf007,
130 0x6009,0x000c,0x000d,
131 0x7d10,0x5712,0xc813,0x4014,0x5715,0x9816,0xc317,0xff18,
132 0x001a,0x221b,0x001d,
136 static u16 cseq_800x600x24[] VAR16 = {
137 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1507,
138 0x230b,0x230c,0x230d,0x230e,
139 0x0412,0x0013,0x2017,
140 0x141b,0x141c,0x141d,0x141e,
143 static u16 ccrtc_800x600x24[] VAR16 = {
144 0x2311,0x7d00,0x6301,0x6302,0x8003,0x6b04,0x1a05,0x9806,0xf007,
145 0x6009,0x000c,0x000d,
146 0x7d10,0x5712,0x2c13,0x4014,0x5715,0x9816,0xc317,0xff18,
147 0x001a,0x321b,0x001d,
151 static u16 cseq_1024x768x8[] VAR16 = {
152 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
153 0x760b,0x760c,0x760d,0x760e,
154 0x0412,0x0013,0x2017,
155 0x341b,0x341c,0x341d,0x341e,
158 static u16 ccrtc_1024x768x8[] VAR16 = {
159 0x2911,0xa300,0x7f01,0x7f02,0x8603,0x8304,0x9405,0x2406,0xf507,
160 0x6009,0x000c,0x000d,
161 0x0310,0xff12,0x8013,0x4014,0xff15,0x2416,0xc317,0xff18,
162 0x001a,0x221b,0x001d,
166 static u16 cseq_1024x768x16[] VAR16 = {
167 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1707,
168 0x760b,0x760c,0x760d,0x760e,
169 0x0412,0x0013,0x2017,
170 0x341b,0x341c,0x341d,0x341e,
173 static u16 ccrtc_1024x768x16[] VAR16 = {
174 0x2911,0xa300,0x7f01,0x7f02,0x8603,0x8304,0x9405,0x2406,0xf507,
175 0x6009,0x000c,0x000d,
176 0x0310,0xff12,0x0013,0x4014,0xff15,0x2416,0xc317,0xff18,
177 0x001a,0x321b,0x001d,
181 static u16 cseq_1024x768x24[] VAR16 = {
182 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1507,
183 0x760b,0x760c,0x760d,0x760e,
184 0x0412,0x0013,0x2017,
185 0x341b,0x341c,0x341d,0x341e,
188 static u16 ccrtc_1024x768x24[] VAR16 = {
189 0x2911,0xa300,0x7f01,0x7f02,0x8603,0x8304,0x9405,0x2406,0xf507,
190 0x6009,0x000c,0x000d,
191 0x0310,0xff12,0x8013,0x4014,0xff15,0x2416,0xc317,0xff18,
192 0x001a,0x321b,0x001d,
196 static u16 cseq_1280x1024x8[] VAR16 = {
197 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
198 0x760b,0x760c,0x760d,0x760e,
199 0x0412,0x0013,0x2017,
200 0x341b,0x341c,0x341d,0x341e,
203 static u16 ccrtc_1280x1024x8[] VAR16 = {
204 0x2911,0xc300,0x9f01,0x9f02,0x8603,0x8304,0x9405,0x2406,0xf707,
205 0x6009,0x000c,0x000d,
206 0x0310,0xff12,0xa013,0x4014,0xff15,0x2416,0xc317,0xff18,
207 0x001a,0x221b,0x001d,
211 static u16 cseq_1280x1024x16[] VAR16 = {
212 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1707,
213 0x760b,0x760c,0x760d,0x760e,
214 0x0412,0x0013,0x2017,
215 0x341b,0x341c,0x341d,0x341e,
218 static u16 ccrtc_1280x1024x16[] VAR16 = {
219 0x2911,0xc300,0x9f01,0x9f02,0x8603,0x8304,0x9405,0x2406,0xf707,
220 0x6009,0x000c,0x000d,
221 0x0310,0xff12,0x4013,0x4014,0xff15,0x2416,0xc317,0xff18,
222 0x001a,0x321b,0x001d,
227 static u16 cseq_1600x1200x8[] VAR16 = {
228 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
229 0x760b,0x760c,0x760d,0x760e,
230 0x0412,0x0013,0x2017,
231 0x341b,0x341c,0x341d,0x341e,
234 static u16 ccrtc_1600x1200x8[] VAR16 = {
235 0x2911,0xc300,0x9f01,0x9f02,0x8603,0x8304,0x9405,0x2406,0xf707,
236 0x6009,0x000c,0x000d,
237 0x0310,0xff12,0xa013,0x4014,0xff15,0x2416,0xc317,0xff18,
238 0x001a,0x221b,0x001d,
242 static struct cirrus_mode_s cirrus_modes[] VAR16 = {
243 {0x5f,MM_PACKED,640,480,8,0x00,
244 cseq_640x480x8,cgraph_svgacolor,ccrtc_640x480x8,8,
246 {0x64,MM_DIRECT,640,480,16,0xe1,
247 cseq_640x480x16,cgraph_svgacolor,ccrtc_640x480x16,16,
249 {0x66,MM_DIRECT,640,480,15,0xf0,
250 cseq_640x480x16,cgraph_svgacolor,ccrtc_640x480x16,16,
252 {0x71,MM_DIRECT,640,480,24,0xe5,
253 cseq_640x480x24,cgraph_svgacolor,ccrtc_640x480x24,24,
256 {0x5c,MM_PACKED,800,600,8,0x00,
257 cseq_800x600x8,cgraph_svgacolor,ccrtc_800x600x8,8,
259 {0x65,MM_DIRECT,800,600,16,0xe1,
260 cseq_800x600x16,cgraph_svgacolor,ccrtc_800x600x16,16,
262 {0x67,MM_DIRECT,800,600,15,0xf0,
263 cseq_800x600x16,cgraph_svgacolor,ccrtc_800x600x16,16,
266 {0x60,MM_PACKED,1024,768,8,0x00,
267 cseq_1024x768x8,cgraph_svgacolor,ccrtc_1024x768x8,8,
269 {0x74,MM_DIRECT,1024,768,16,0xe1,
270 cseq_1024x768x16,cgraph_svgacolor,ccrtc_1024x768x16,16,
272 {0x68,MM_DIRECT,1024,768,15,0xf0,
273 cseq_1024x768x16,cgraph_svgacolor,ccrtc_1024x768x16,16,
276 {0x78,MM_DIRECT,800,600,24,0xe5,
277 cseq_800x600x24,cgraph_svgacolor,ccrtc_800x600x24,24,
279 {0x79,MM_DIRECT,1024,768,24,0xe5,
280 cseq_1024x768x24,cgraph_svgacolor,ccrtc_1024x768x24,24,
283 {0x6d,MM_PACKED,1280,1024,8,0x00,
284 cseq_1280x1024x8,cgraph_svgacolor,ccrtc_1280x1024x8,8,
286 {0x69,MM_DIRECT,1280,1024,15,0xf0,
287 cseq_1280x1024x16,cgraph_svgacolor,ccrtc_1280x1024x16,16,
289 {0x75,MM_DIRECT,1280,1024,16,0xe1,
290 cseq_1280x1024x16,cgraph_svgacolor,ccrtc_1280x1024x16,16,
293 {0x7b,MM_PACKED,1600,1200,8,0x00,
294 cseq_1600x1200x8,cgraph_svgacolor,ccrtc_1600x1200x8,8,
297 {0xfe,0xff,0,0,0,0,cseq_vga,cgraph_vga,ccrtc_vga,0,
302 /****************************************************************
304 ****************************************************************/
306 static struct cirrus_mode_s *
307 cirrus_get_modeentry(u8 mode)
309 struct cirrus_mode_s *table_g = cirrus_modes;
310 while (table_g < &cirrus_modes[ARRAY_SIZE(cirrus_modes)]) {
311 u16 tmode = GET_GLOBAL(table_g->mode);
320 cirrus_switch_mode_setregs(u16 *data, u16 port)
323 u16 val = GET_GLOBAL(*data);
332 cirrus_switch_mode(struct cirrus_mode_s *table)
334 // Unlock cirrus special
335 outw(0x1206, VGAREG_SEQU_ADDRESS);
336 cirrus_switch_mode_setregs(GET_GLOBAL(table->seq), VGAREG_SEQU_ADDRESS);
337 cirrus_switch_mode_setregs(GET_GLOBAL(table->graph), VGAREG_GRDC_ADDRESS);
338 cirrus_switch_mode_setregs(GET_GLOBAL(table->crtc), stdvga_get_crtc());
340 outb(0x00, VGAREG_PEL_MASK);
341 inb(VGAREG_PEL_MASK);
342 inb(VGAREG_PEL_MASK);
343 inb(VGAREG_PEL_MASK);
344 inb(VGAREG_PEL_MASK);
345 outb(GET_GLOBAL(table->hidden_dac), VGAREG_PEL_MASK);
346 outb(0xff, VGAREG_PEL_MASK);
348 u8 memmodel = GET_GLOBAL(table->memmodel);
349 u8 v = stdvga_get_single_palette_reg(0x10) & 0xfe;
350 if (memmodel == MM_PLANAR)
352 else if (memmodel != MM_TEXT)
354 stdvga_set_single_palette_reg(0x10, v);
358 cirrus_get_memsize(void)
360 // get DRAM band width
361 outb(0x0f, VGAREG_SEQU_ADDRESS);
362 u8 v = inb(VGAREG_SEQU_DATA);
363 u8 x = (v >> 3) & 0x03;
375 cirrus_enable_16k_granularity(void)
377 outb(0x0b, VGAREG_GRDC_ADDRESS);
378 u8 v = inb(VGAREG_GRDC_DATA);
379 outb(v | 0x20, VGAREG_GRDC_DATA);
383 cirrus_clear_vram(u16 param)
385 cirrus_enable_16k_granularity();
386 u8 count = cirrus_get_memsize() * 4;
388 for (i=0; i<count; i++) {
389 outw((i<<8) | 0x09, VGAREG_GRDC_ADDRESS);
390 memset16_far(SEG_GRAPH, 0, param, 16 * 1024);
392 outw(0x0009, VGAREG_GRDC_ADDRESS);
396 clext_set_mode(int mode, int flags)
398 dprintf(1, "cirrus mode %d\n", mode);
399 SET_BDA(vbe_mode, 0);
400 struct cirrus_mode_s *table_g = cirrus_get_modeentry(mode);
402 cirrus_switch_mode(table_g);
403 if (!(flags & MF_NOCLEARMEM))
404 cirrus_clear_vram(0xffff);
405 SET_BDA(video_mode, mode);
408 table_g = cirrus_get_modeentry(0xfe);
409 cirrus_switch_mode(table_g);
410 dprintf(1, "cirrus mode switch regular\n");
411 return stdvga_set_mode(mode, flags);
417 outw(0x9206, VGAREG_SEQU_ADDRESS);
418 return inb(VGAREG_SEQU_DATA) == 0x12;
422 /****************************************************************
424 ****************************************************************/
427 cirrus_extbios_80h(struct bregs *regs)
429 u16 crtc_addr = stdvga_get_crtc();
430 outb(0x27, crtc_addr);
431 u8 v = inb(crtc_addr + 1);
445 cirrus_extbios_81h(struct bregs *regs)
452 cirrus_extbios_82h(struct bregs *regs)
454 u16 crtc_addr = stdvga_get_crtc();
455 outb(0x27, crtc_addr);
456 regs->al = inb(crtc_addr + 1) & 0x03;
461 cirrus_extbios_85h(struct bregs *regs)
463 regs->al = cirrus_get_memsize();
467 cirrus_extbios_9Ah(struct bregs *regs)
473 extern void a0h_callback(void);
475 // fatal: not implemented yet
482 cirrus_extbios_A0h(struct bregs *regs)
484 struct cirrus_mode_s *table_g = cirrus_get_modeentry(regs->al & 0x7f);
485 regs->ah = (table_g ? 1 : 0);
487 regs->di = regs->ds = regs->es = regs->bx = (u32)a0h_callback;
491 cirrus_extbios_A1h(struct bregs *regs)
493 regs->bx = 0x0e00; // IBM 8512/8513, color
497 cirrus_extbios_A2h(struct bregs *regs)
499 regs->al = 0x07; // HSync 31.5 - 64.0 kHz
503 cirrus_extbios_AEh(struct bregs *regs)
505 regs->al = 0x01; // High Refresh 75Hz
509 cirrus_extbios(struct bregs *regs)
511 // XXX - regs->bl < 0x80 or > 0xaf call regular handlers.
513 case 0x80: cirrus_extbios_80h(regs); break;
514 case 0x81: cirrus_extbios_81h(regs); break;
515 case 0x82: cirrus_extbios_82h(regs); break;
516 case 0x85: cirrus_extbios_85h(regs); break;
517 case 0x9a: cirrus_extbios_9Ah(regs); break;
518 case 0xa0: cirrus_extbios_A0h(regs); break;
519 case 0xa1: cirrus_extbios_A1h(regs); break;
520 case 0xa2: cirrus_extbios_A2h(regs); break;
521 case 0xae: cirrus_extbios_AEh(regs); break;
527 /****************************************************************
529 ****************************************************************/
533 } cirrus_vesa_modelist[] VAR16 = {
567 cirrus_vesamode_to_mode(u16 vesamode)
570 for (i=0; i<ARRAY_SIZE(cirrus_vesa_modelist); i++)
571 if (GET_GLOBAL(cirrus_vesa_modelist[i].vesamode) == vesamode)
572 return GET_GLOBAL(cirrus_vesa_modelist[i].mode);
577 cirrus_get_bpp_bytes(void)
579 outb(0x07, VGAREG_SEQU_ADDRESS);
580 u8 v = inb(VGAREG_SEQU_DATA) & 0x0e;
590 cirrus_set_line_offset(u16 new_line_offset)
592 u16 crtc_addr = stdvga_get_crtc();
593 outb(0x13, crtc_addr);
594 outb(new_line_offset / 8, crtc_addr + 1);
596 outb(0x1b, crtc_addr);
597 u8 v = inb(crtc_addr + 1);
598 outb((((new_line_offset / 8) & 0x100) >> 4) | (v & 0xef), crtc_addr + 1);
602 cirrus_get_line_offset(void)
604 u16 crtc_addr = stdvga_get_crtc();
605 outb(0x13, crtc_addr);
606 u8 reg13 = inb(crtc_addr + 1);
607 outb(0x1b, crtc_addr);
608 u8 reg1b = inb(crtc_addr + 1);
610 return (((reg1b << 4) & 0x100) + reg13) * 8;
614 cirrus_get_line_offset_entry(struct cirrus_mode_s *table_g)
616 u16 *crtc = GET_GLOBAL(table_g->crtc);
621 reg13 = GET_GLOBAL(*c);
622 if ((reg13 & 0xff) == 0x13)
631 reg1b = GET_GLOBAL(*c);
632 if ((reg1b & 0xff) == 0x1b)
638 return (((reg1b << 4) & 0x100) + reg13) * 8;
642 cirrus_set_start_addr(u32 addr)
644 u16 crtc_addr = stdvga_get_crtc();
645 outb(0x0d, crtc_addr);
646 outb(addr, crtc_addr + 1);
648 outb(0x0c, crtc_addr);
649 outb(addr>>8, crtc_addr + 1);
651 outb(0x1d, crtc_addr);
652 u8 v = inb(crtc_addr + 1);
653 outb(((addr & 0x0800) >> 4) | (v & 0x7f), crtc_addr + 1);
655 outb(0x1b, crtc_addr);
656 v = inb(crtc_addr + 1);
657 outb(((addr & 0x0100) >> 8) | ((addr & 0x0600) >> 7) | (v & 0xf2)
662 cirrus_get_start_addr(void)
664 u16 crtc_addr = stdvga_get_crtc();
665 outb(0x0c, crtc_addr);
666 u8 b2 = inb(crtc_addr + 1);
668 outb(0x0d, crtc_addr);
669 u8 b1 = inb(crtc_addr + 1);
671 outb(0x1b, crtc_addr);
672 u8 b3 = inb(crtc_addr + 1);
674 outb(0x1d, crtc_addr);
675 u8 b4 = inb(crtc_addr + 1);
677 return (b1 | (b2<<8) | ((b3 & 0x01) << 16) | ((b3 & 0x0c) << 15)
678 | ((b4 & 0x80) << 12));
682 cirrus_vesa_00h(struct bregs *regs)
685 struct vbe_info *info = (void*)(regs->di+0);
687 if (GET_FARVAR(seg, info->signature) == VBE2_SIGNATURE) {
688 SET_FARVAR(seg, info->oem_revision, 0x0100);
689 SET_FARVAR(seg, info->oem_vendor_string,
690 SEGOFF(get_global_seg(), (u32)VBE_VENDOR_STRING));
691 SET_FARVAR(seg, info->oem_product_string,
692 SEGOFF(get_global_seg(), (u32)VBE_PRODUCT_STRING));
693 SET_FARVAR(seg, info->oem_revision_string,
694 SEGOFF(get_global_seg(), (u32)VBE_REVISION_STRING));
696 SET_FARVAR(seg, info->signature, VESA_SIGNATURE);
698 SET_FARVAR(seg, info->version, 0x0200);
700 SET_FARVAR(seg, info->oem_string
701 , SEGOFF(get_global_seg(), (u32)VBE_OEM_STRING));
702 SET_FARVAR(seg, info->capabilities, 0);
703 SET_FARVAR(seg, info->total_memory, cirrus_get_memsize());
705 u16 *destmode = (void*)info->reserved;
706 SET_FARVAR(seg, info->video_mode, SEGOFF(seg, (u32)destmode));
708 for (i=0; i<ARRAY_SIZE(cirrus_vesa_modelist); i++)
709 SET_FARVAR(seg, destmode[i]
710 , GET_GLOBAL(cirrus_vesa_modelist[i].vesamode));
711 SET_FARVAR(seg, destmode[i], 0xffff);
716 static u32 cirrus_lfb_addr VAR16;
719 cirrus_vesa_01h(struct bregs *regs)
721 u16 mode = cirrus_vesamode_to_mode(regs->cx & 0x3fff);
726 struct cirrus_mode_s *table_g = cirrus_get_modeentry(mode);
727 u32 lfb = GET_GLOBAL(cirrus_lfb_addr); // XXX
728 if ((regs->cx & 0x4000) && !lfb) {
734 struct vbe_mode_info *info = (void*)(regs->di+0);
735 memset_far(seg, info, 0, sizeof(*info));
737 SET_FARVAR(seg, info->mode_attributes, lfb ? 0xbb : 0x3b);
738 SET_FARVAR(seg, info->winA_attributes, 0x07);
739 SET_FARVAR(seg, info->winB_attributes, 0);
740 SET_FARVAR(seg, info->win_granularity, 16);
741 SET_FARVAR(seg, info->win_size, 64);
742 SET_FARVAR(seg, info->winA_seg, SEG_GRAPH);
743 SET_FARVAR(seg, info->winB_seg, 0x0);
744 SET_FARVAR(seg, info->win_func_ptr.segoff, 0x0); // XXX
745 u16 linesize = cirrus_get_line_offset_entry(table_g);
746 SET_FARVAR(seg, info->bytes_per_scanline, linesize);
747 SET_FARVAR(seg, info->xres, GET_GLOBAL(table_g->width));
748 u16 height = GET_GLOBAL(table_g->height);
749 SET_FARVAR(seg, info->yres, height);
750 SET_FARVAR(seg, info->xcharsize, 8);
751 SET_FARVAR(seg, info->ycharsize, 16);
752 SET_FARVAR(seg, info->planes, 1);
753 SET_FARVAR(seg, info->bits_per_pixel, GET_GLOBAL(table_g->depth));
754 SET_FARVAR(seg, info->banks, 1);
755 SET_FARVAR(seg, info->mem_model, GET_GLOBAL(table_g->memmodel));
756 SET_FARVAR(seg, info->bank_size, 0);
758 int pages = (cirrus_get_memsize() * 64 * 1024) / (height * linesize);
759 SET_FARVAR(seg, info->pages, pages - 1);
760 SET_FARVAR(seg, info->reserved0, 0);
762 SET_FARVAR(seg, info->red_size, GET_GLOBAL(table_g->vesaredmask));
763 SET_FARVAR(seg, info->red_pos, GET_GLOBAL(table_g->vesaredpos));
764 SET_FARVAR(seg, info->green_size, GET_GLOBAL(table_g->vesagreenmask));
765 SET_FARVAR(seg, info->green_pos, GET_GLOBAL(table_g->vesagreenpos));
766 SET_FARVAR(seg, info->blue_size, GET_GLOBAL(table_g->vesabluemask));
767 SET_FARVAR(seg, info->blue_pos, GET_GLOBAL(table_g->vesabluepos));
768 SET_FARVAR(seg, info->alpha_size, GET_GLOBAL(table_g->vesareservedmask));
769 SET_FARVAR(seg, info->alpha_pos, GET_GLOBAL(table_g->vesareservedpos));
770 u8 directcolor_info = GET_GLOBAL(table_g->bitsperpixel) <= 8;
771 SET_FARVAR(seg, info->directcolor_info, directcolor_info);
773 SET_FARVAR(seg, info->phys_base, lfb);
779 cirrus_vesa_02h(struct bregs *regs)
781 if (regs->bx & 0x3e00) {
785 if ((regs->bx & 0x1ff) < 0x100) {
786 // XXX - call legacy mode switch
791 u16 mode = cirrus_vesamode_to_mode(regs->cx & 0x3fff);
796 struct cirrus_mode_s *table_g = cirrus_get_modeentry(mode);
797 cirrus_switch_mode(table_g);
799 if (!(regs->bx & 0x4000))
800 cirrus_enable_16k_granularity();
801 if (!(regs->bx & 0x8000))
802 cirrus_clear_vram(0);
803 SET_BDA(video_mode, mode);
804 SET_BDA(vbe_mode, regs->bx);
810 cirrus_vesa_03h(struct bregs *regs)
812 u16 mode = GET_BDA(vbe_mode);
814 mode = GET_BDA(video_mode);
820 // XXX - add cirrus_vesa_05h_farentry to vgaentry.S
823 cirrus_vesa_05h(struct bregs *regs)
829 if (regs->dx >= 0x100)
831 outw((regs->dx << 8) | (regs->bl + 9), VGAREG_GRDC_ADDRESS);
832 } else if (regs->bh == 1) {
834 outb(regs->bl + 9, VGAREG_GRDC_ADDRESS);
835 regs->dx = inb(VGAREG_GRDC_DATA);
846 cirrus_vesa_06h(struct bregs *regs)
853 if (regs->bl == 0x00) {
854 cirrus_set_line_offset(cirrus_get_bpp_bytes() * regs->cx);
855 } else if (regs->bl == 0x02) {
856 cirrus_set_line_offset(regs->cx);
859 u32 v = cirrus_get_line_offset();
860 regs->cx = v / cirrus_get_bpp_bytes();
862 regs->dx = (cirrus_get_memsize() * 64 * 1024) / v;
867 cirrus_vesa_07h(struct bregs *regs)
869 if (regs->bl == 0x80 || regs->bl == 0x00) {
870 u32 addr = (cirrus_get_bpp_bytes() * regs->cx
871 + cirrus_get_line_offset() * regs->dx);
872 cirrus_set_start_addr(addr / 4);
873 } else if (regs->bl == 0x01) {
874 u32 addr = cirrus_get_start_addr() * 4;
875 u32 linelength = cirrus_get_line_offset();
876 regs->dx = addr / linelength;
877 regs->cx = (addr % linelength) / cirrus_get_bpp_bytes();
887 cirrus_vesa_10h(struct bregs *regs)
889 if (regs->bl == 0x00) {
894 if (regs->bl == 0x01) {
895 SET_BDA(vbe_flag, regs->bh);
899 if (regs->bl == 0x02) {
900 regs->bh = GET_BDA(vbe_flag);
908 cirrus_vesa_not_handled(struct bregs *regs)
915 cirrus_vesa(struct bregs *regs)
918 case 0x00: cirrus_vesa_00h(regs); break;
919 case 0x01: cirrus_vesa_01h(regs); break;
920 case 0x02: cirrus_vesa_02h(regs); break;
921 case 0x03: cirrus_vesa_03h(regs); break;
922 case 0x05: cirrus_vesa_05h(regs); break;
923 case 0x06: cirrus_vesa_06h(regs); break;
924 case 0x07: cirrus_vesa_07h(regs); break;
925 case 0x10: cirrus_vesa_10h(regs); break;
926 default: cirrus_vesa_not_handled(regs); break;
931 /****************************************************************
933 ****************************************************************/
938 int ret = stdvga_init();
942 dprintf(1, "cirrus init\n");
943 if (! cirrus_check())
945 dprintf(1, "cirrus init 2\n");
948 outb(0x0f, VGAREG_SEQU_ADDRESS);
949 u8 v = inb(VGAREG_SEQU_DATA);
950 outb(((v & 0x18) << 8) | 0x0a, VGAREG_SEQU_ADDRESS);
952 outw(0x0007, VGAREG_SEQU_ADDRESS);
954 outw(0x0431, VGAREG_GRDC_ADDRESS);
955 outw(0x0031, VGAREG_GRDC_ADDRESS);