1 // QEMU Cirrus CLGD 54xx VGABIOS Extension.
3 // Copyright (C) 2009 Kevin O'Connor <kevin@koconnor.net>
4 // Copyright (c) 2004 Makoto Suzuki (suzu)
6 // This file may be distributed under the terms of the GNU LGPLv3 license.
8 #include "clext.h" // clext_init
9 #include "vgabios.h" // VBE_VENDOR_STRING
10 #include "biosvar.h" // GET_GLOBAL
11 #include "util.h" // dprintf
12 #include "bregs.h" // struct bregs
13 #include "stdvga.h" // VGAREG_SEQU_ADDRESS
14 #include "pci.h" // pci_config_readl
15 #include "pci_regs.h" // PCI_BASE_ADDRESS_0
18 /****************************************************************
20 ****************************************************************/
23 static u16 cseq_vga[] VAR16 = {0x0007,0xffff};
24 static u16 cgraph_vga[] VAR16 = {0x0009,0x000a,0x000b,0xffff};
25 static u16 ccrtc_vga[] VAR16 = {0x001a,0x001b,0x001d,0xffff};
28 static u16 cgraph_svgacolor[] VAR16 = {
29 0x0000,0x0001,0x0002,0x0003,0x0004,0x4005,0x0506,0x0f07,0xff08,
34 static u16 cseq_640x480x8[] VAR16 = {
35 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
36 0x580b,0x580c,0x580d,0x580e,
38 0x331b,0x331c,0x331d,0x331e,
41 static u16 ccrtc_640x480x8[] VAR16 = {
43 0x5f00,0x4f01,0x4f02,0x8003,0x5204,0x1e05,0x0b06,0x3e07,
45 0xea10,0xdf12,0x5013,0x4014,0xdf15,0x0b16,0xc317,0xff18,
50 static u16 cseq_640x480x16[] VAR16 = {
51 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1707,
52 0x580b,0x580c,0x580d,0x580e,
54 0x331b,0x331c,0x331d,0x331e,
57 static u16 ccrtc_640x480x16[] VAR16 = {
59 0x5f00,0x4f01,0x4f02,0x8003,0x5204,0x1e05,0x0b06,0x3e07,
61 0xea10,0xdf12,0xa013,0x4014,0xdf15,0x0b16,0xc317,0xff18,
66 static u16 cseq_640x480x24[] VAR16 = {
67 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1507,
68 0x580b,0x580c,0x580d,0x580e,
70 0x331b,0x331c,0x331d,0x331e,
73 static u16 ccrtc_640x480x24[] VAR16 = {
75 0x5f00,0x4f01,0x4f02,0x8003,0x5204,0x1e05,0x0b06,0x3e07,
77 0xea10,0xdf12,0xf013,0x4014,0xdf15,0x0b16,0xc317,0xff18,
82 static u16 cseq_800x600x8[] VAR16 = {
83 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
84 0x230b,0x230c,0x230d,0x230e,
86 0x141b,0x141c,0x141d,0x141e,
89 static u16 ccrtc_800x600x8[] VAR16 = {
90 0x2311,0x7d00,0x6301,0x6302,0x8003,0x6b04,0x1a05,0x9806,0xf007,
92 0x7d10,0x5712,0x6413,0x4014,0x5715,0x9816,0xc317,0xff18,
97 static u16 cseq_800x600x16[] VAR16 = {
98 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1707,
99 0x230b,0x230c,0x230d,0x230e,
100 0x0412,0x0013,0x2017,
101 0x141b,0x141c,0x141d,0x141e,
104 static u16 ccrtc_800x600x16[] VAR16 = {
105 0x2311,0x7d00,0x6301,0x6302,0x8003,0x6b04,0x1a05,0x9806,0xf007,
106 0x6009,0x000c,0x000d,
107 0x7d10,0x5712,0xc813,0x4014,0x5715,0x9816,0xc317,0xff18,
108 0x001a,0x221b,0x001d,
112 static u16 cseq_800x600x24[] VAR16 = {
113 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1507,
114 0x230b,0x230c,0x230d,0x230e,
115 0x0412,0x0013,0x2017,
116 0x141b,0x141c,0x141d,0x141e,
119 static u16 ccrtc_800x600x24[] VAR16 = {
120 0x2311,0x7d00,0x6301,0x6302,0x8003,0x6b04,0x1a05,0x9806,0xf007,
121 0x6009,0x000c,0x000d,
122 0x7d10,0x5712,0x2c13,0x4014,0x5715,0x9816,0xc317,0xff18,
123 0x001a,0x321b,0x001d,
127 static u16 cseq_1024x768x8[] VAR16 = {
128 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
129 0x760b,0x760c,0x760d,0x760e,
130 0x0412,0x0013,0x2017,
131 0x341b,0x341c,0x341d,0x341e,
134 static u16 ccrtc_1024x768x8[] VAR16 = {
135 0x2911,0xa300,0x7f01,0x7f02,0x8603,0x8304,0x9405,0x2406,0xf507,
136 0x6009,0x000c,0x000d,
137 0x0310,0xff12,0x8013,0x4014,0xff15,0x2416,0xc317,0xff18,
138 0x001a,0x221b,0x001d,
142 static u16 cseq_1024x768x16[] VAR16 = {
143 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1707,
144 0x760b,0x760c,0x760d,0x760e,
145 0x0412,0x0013,0x2017,
146 0x341b,0x341c,0x341d,0x341e,
149 static u16 ccrtc_1024x768x16[] VAR16 = {
150 0x2911,0xa300,0x7f01,0x7f02,0x8603,0x8304,0x9405,0x2406,0xf507,
151 0x6009,0x000c,0x000d,
152 0x0310,0xff12,0x0013,0x4014,0xff15,0x2416,0xc317,0xff18,
153 0x001a,0x321b,0x001d,
157 static u16 cseq_1024x768x24[] VAR16 = {
158 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1507,
159 0x760b,0x760c,0x760d,0x760e,
160 0x0412,0x0013,0x2017,
161 0x341b,0x341c,0x341d,0x341e,
164 static u16 ccrtc_1024x768x24[] VAR16 = {
165 0x2911,0xa300,0x7f01,0x7f02,0x8603,0x8304,0x9405,0x2406,0xf507,
166 0x6009,0x000c,0x000d,
167 0x0310,0xff12,0x8013,0x4014,0xff15,0x2416,0xc317,0xff18,
168 0x001a,0x321b,0x001d,
172 static u16 cseq_1280x1024x8[] VAR16 = {
173 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
174 0x760b,0x760c,0x760d,0x760e,
175 0x0412,0x0013,0x2017,
176 0x341b,0x341c,0x341d,0x341e,
179 static u16 ccrtc_1280x1024x8[] VAR16 = {
180 0x2911,0xc300,0x9f01,0x9f02,0x8603,0x8304,0x9405,0x2406,0xf707,
181 0x6009,0x000c,0x000d,
182 0x0310,0xff12,0xa013,0x4014,0xff15,0x2416,0xc317,0xff18,
183 0x001a,0x221b,0x001d,
187 static u16 cseq_1280x1024x16[] VAR16 = {
188 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1707,
189 0x760b,0x760c,0x760d,0x760e,
190 0x0412,0x0013,0x2017,
191 0x341b,0x341c,0x341d,0x341e,
194 static u16 ccrtc_1280x1024x16[] VAR16 = {
195 0x2911,0xc300,0x9f01,0x9f02,0x8603,0x8304,0x9405,0x2406,0xf707,
196 0x6009,0x000c,0x000d,
197 0x0310,0xff12,0x4013,0x4014,0xff15,0x2416,0xc317,0xff18,
198 0x001a,0x321b,0x001d,
203 static u16 cseq_1600x1200x8[] VAR16 = {
204 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
205 0x760b,0x760c,0x760d,0x760e,
206 0x0412,0x0013,0x2017,
207 0x341b,0x341c,0x341d,0x341e,
210 static u16 ccrtc_1600x1200x8[] VAR16 = {
211 0x2911,0xc300,0x9f01,0x9f02,0x8603,0x8304,0x9405,0x2406,0xf707,
212 0x6009,0x000c,0x000d,
213 0x0310,0xff12,0xc813,0x4014,0xff15,0x2416,0xc317,0xff18,
214 0x001a,0x221b,0x001d,
218 struct cirrus_mode_s {
220 struct vgamode_s info;
222 u16 hidden_dac; /* 0x3c6 */
223 u16 *seq; /* 0x3c4 */
224 u16 *graph; /* 0x3ce */
225 u16 *crtc; /* 0x3d4 */
228 static struct cirrus_mode_s cirrus_modes[] VAR16 = {
229 {0x5f,{MM_PACKED,640,480,8,8,16,SEG_GRAPH},0x00,
230 cseq_640x480x8,cgraph_svgacolor,ccrtc_640x480x8},
231 {0x64,{MM_DIRECT,640,480,16,8,16,SEG_GRAPH},0xe1,
232 cseq_640x480x16,cgraph_svgacolor,ccrtc_640x480x16},
233 {0x66,{MM_DIRECT,640,480,15,8,16,SEG_GRAPH},0xf0,
234 cseq_640x480x16,cgraph_svgacolor,ccrtc_640x480x16},
235 {0x71,{MM_DIRECT,640,480,24,8,16,SEG_GRAPH},0xe5,
236 cseq_640x480x24,cgraph_svgacolor,ccrtc_640x480x24},
238 {0x5c,{MM_PACKED,800,600,8,8,16,SEG_GRAPH},0x00,
239 cseq_800x600x8,cgraph_svgacolor,ccrtc_800x600x8},
240 {0x65,{MM_DIRECT,800,600,16,8,16,SEG_GRAPH},0xe1,
241 cseq_800x600x16,cgraph_svgacolor,ccrtc_800x600x16},
242 {0x67,{MM_DIRECT,800,600,15,8,16,SEG_GRAPH},0xf0,
243 cseq_800x600x16,cgraph_svgacolor,ccrtc_800x600x16},
245 {0x60,{MM_PACKED,1024,768,8,8,16,SEG_GRAPH},0x00,
246 cseq_1024x768x8,cgraph_svgacolor,ccrtc_1024x768x8},
247 {0x74,{MM_DIRECT,1024,768,16,8,16,SEG_GRAPH},0xe1,
248 cseq_1024x768x16,cgraph_svgacolor,ccrtc_1024x768x16},
249 {0x68,{MM_DIRECT,1024,768,15,8,16,SEG_GRAPH},0xf0,
250 cseq_1024x768x16,cgraph_svgacolor,ccrtc_1024x768x16},
252 {0x78,{MM_DIRECT,800,600,24,8,16,SEG_GRAPH},0xe5,
253 cseq_800x600x24,cgraph_svgacolor,ccrtc_800x600x24},
254 {0x79,{MM_DIRECT,1024,768,24,8,16,SEG_GRAPH},0xe5,
255 cseq_1024x768x24,cgraph_svgacolor,ccrtc_1024x768x24},
257 {0x6d,{MM_PACKED,1280,1024,8,8,16,SEG_GRAPH},0x00,
258 cseq_1280x1024x8,cgraph_svgacolor,ccrtc_1280x1024x8},
259 {0x69,{MM_DIRECT,1280,1024,15,8,16,SEG_GRAPH},0xf0,
260 cseq_1280x1024x16,cgraph_svgacolor,ccrtc_1280x1024x16},
261 {0x75,{MM_DIRECT,1280,1024,16,8,16,SEG_GRAPH},0xe1,
262 cseq_1280x1024x16,cgraph_svgacolor,ccrtc_1280x1024x16},
264 {0x7b,{MM_PACKED,1600,1200,8,8,16,SEG_GRAPH},0x00,
265 cseq_1600x1200x8,cgraph_svgacolor,ccrtc_1600x1200x8},
268 static struct cirrus_mode_s mode_switchback VAR16 =
269 {0xfe,{0xff},0,cseq_vga,cgraph_vga,ccrtc_vga};
273 } cirrus_vesa_modelist[] VAR16 = {
307 /****************************************************************
309 ****************************************************************/
312 is_cirrus_mode(struct vgamode_s *vmode_g)
314 return (vmode_g >= &cirrus_modes[0].info
315 && vmode_g <= &cirrus_modes[ARRAY_SIZE(cirrus_modes)-1].info);
319 clext_list_modes(u16 seg, u16 *dest, u16 *last)
322 for (i=0; i<ARRAY_SIZE(cirrus_vesa_modelist) && dest<last; i++) {
323 SET_FARVAR(seg, *dest, GET_GLOBAL(cirrus_vesa_modelist[i].vesamode));
326 stdvga_list_modes(seg, dest, last);
330 cirrus_vesamode_to_mode(u16 vesamode)
333 for (i=0; i<ARRAY_SIZE(cirrus_vesa_modelist); i++)
334 if (GET_GLOBAL(cirrus_vesa_modelist[i].vesamode) == vesamode)
335 return GET_GLOBAL(cirrus_vesa_modelist[i].mode);
339 static struct cirrus_mode_s *
340 cirrus_get_modeentry(int mode)
342 int transmode = cirrus_vesamode_to_mode(mode);
345 struct cirrus_mode_s *table_g = cirrus_modes;
346 while (table_g < &cirrus_modes[ARRAY_SIZE(cirrus_modes)]) {
347 u16 tmode = GET_GLOBAL(table_g->mode);
356 clext_find_mode(int mode)
358 struct cirrus_mode_s *table_g = cirrus_get_modeentry(mode);
360 return &table_g->info;
361 return stdvga_find_mode(mode);
365 cirrus_switch_mode_setregs(u16 *data, u16 port)
368 u16 val = GET_GLOBAL(*data);
377 cirrus_switch_mode(struct cirrus_mode_s *table)
379 // Unlock cirrus special
380 stdvga_sequ_write(0x06, 0x12);
381 cirrus_switch_mode_setregs(GET_GLOBAL(table->seq), VGAREG_SEQU_ADDRESS);
382 cirrus_switch_mode_setregs(GET_GLOBAL(table->graph), VGAREG_GRDC_ADDRESS);
383 cirrus_switch_mode_setregs(GET_GLOBAL(table->crtc), stdvga_get_crtc());
385 stdvga_pelmask_write(0x00);
386 stdvga_pelmask_read();
387 stdvga_pelmask_read();
388 stdvga_pelmask_read();
389 stdvga_pelmask_read();
390 stdvga_pelmask_write(GET_GLOBAL(table->hidden_dac));
391 stdvga_pelmask_write(0xff);
393 u8 memmodel = GET_GLOBAL(table->info.memmodel);
395 if (memmodel == MM_PLANAR)
397 else if (memmodel != MM_TEXT)
399 stdvga_attr_mask(0x10, 0x01, on);
403 cirrus_get_memsize(void)
405 // get DRAM band width
406 u8 v = stdvga_sequ_read(0x0f);
407 u8 x = (v >> 3) & 0x03;
408 if (x == 0x03 && v & 0x80)
415 clext_get_window(struct vgamode_s *vmode_g, int window)
417 return stdvga_grdc_read(window + 9);
421 clext_set_window(struct vgamode_s *vmode_g, int window, int val)
425 stdvga_grdc_write(window + 9, val);
430 clext_get_linelength(struct vgamode_s *vmode_g)
432 u16 crtc_addr = stdvga_get_crtc();
433 u8 reg13 = stdvga_crtc_read(crtc_addr, 0x13);
434 u8 reg1b = stdvga_crtc_read(crtc_addr, 0x1b);
435 return (((reg1b & 0x10) << 4) + reg13) * stdvga_bpp_factor(vmode_g) * 2;
439 clext_set_linelength(struct vgamode_s *vmode_g, int val)
441 u16 crtc_addr = stdvga_get_crtc();
442 int factor = stdvga_bpp_factor(vmode_g) * 2;
443 int new_line_offset = DIV_ROUND_UP(val, factor);
444 stdvga_crtc_write(crtc_addr, 0x13, new_line_offset);
445 stdvga_crtc_mask(crtc_addr, 0x1b, 0x10, (new_line_offset & 0x100) >> 4);
450 clext_get_displaystart(struct vgamode_s *vmode_g)
452 u16 crtc_addr = stdvga_get_crtc();
453 u8 b2 = stdvga_crtc_read(crtc_addr, 0x0c);
454 u8 b1 = stdvga_crtc_read(crtc_addr, 0x0d);
455 u8 b3 = stdvga_crtc_read(crtc_addr, 0x1b);
456 u8 b4 = stdvga_crtc_read(crtc_addr, 0x1d);
457 int val = (b1 | (b2<<8) | ((b3 & 0x01) << 16) | ((b3 & 0x0c) << 15)
458 | ((b4 & 0x80) << 12));
459 return val * stdvga_bpp_factor(vmode_g);
463 clext_set_displaystart(struct vgamode_s *vmode_g, int val)
465 u16 crtc_addr = stdvga_get_crtc();
466 val /= stdvga_bpp_factor(vmode_g);
467 stdvga_crtc_write(crtc_addr, 0x0d, val);
468 stdvga_crtc_write(crtc_addr, 0x0c, val >> 8);
469 stdvga_crtc_mask(crtc_addr, 0x1d, 0x80, (val & 0x0800) >> 4);
470 stdvga_crtc_mask(crtc_addr, 0x1b, 0x0d
471 , ((val & 0x0100) >> 8) | ((val & 0x0600) >> 7));
476 cirrus_enable_16k_granularity(void)
478 stdvga_grdc_mask(0x0b, 0x00, 0x20);
482 cirrus_clear_vram(u16 param)
484 cirrus_enable_16k_granularity();
485 u8 count = GET_GLOBAL(VBE_total_memory) / (16 * 1024);
487 for (i=0; i<count; i++) {
488 stdvga_grdc_write(0x09, i);
489 memset16_far(SEG_GRAPH, 0, param, 16 * 1024);
491 stdvga_grdc_write(0x09, 0x00);
495 clext_set_mode(struct vgamode_s *vmode_g, int flags)
497 if (!is_cirrus_mode(vmode_g)) {
498 cirrus_switch_mode(&mode_switchback);
499 dprintf(1, "cirrus mode switch regular\n");
500 return stdvga_set_mode(vmode_g, flags);
502 struct cirrus_mode_s *table_g = container_of(
503 vmode_g, struct cirrus_mode_s, info);
504 cirrus_switch_mode(table_g);
505 if (!(flags & MF_LINEARFB))
506 cirrus_enable_16k_granularity();
507 if (!(flags & MF_NOCLEARMEM))
508 cirrus_clear_vram(0);
515 stdvga_sequ_write(0x06, 0x92);
516 return stdvga_sequ_read(0x06) == 0x12;
520 /****************************************************************
522 ****************************************************************/
525 clext_101280(struct bregs *regs)
527 u8 v = stdvga_crtc_read(stdvga_get_crtc(), 0x27);
541 clext_101281(struct bregs *regs)
548 clext_101282(struct bregs *regs)
550 regs->al = stdvga_crtc_read(stdvga_get_crtc(), 0x27) & 0x03;
555 clext_101285(struct bregs *regs)
557 regs->al = GET_GLOBAL(VBE_total_memory) / (64*1024);
561 clext_10129a(struct bregs *regs)
567 extern void a0h_callback(void);
569 // fatal: not implemented yet
576 clext_1012a0(struct bregs *regs)
578 struct cirrus_mode_s *table_g = cirrus_get_modeentry(regs->al & 0x7f);
579 regs->ah = (table_g ? 1 : 0);
581 regs->di = regs->ds = regs->es = regs->bx = (u32)a0h_callback;
585 clext_1012a1(struct bregs *regs)
587 regs->bx = 0x0e00; // IBM 8512/8513, color
591 clext_1012a2(struct bregs *regs)
593 regs->al = 0x07; // HSync 31.5 - 64.0 kHz
597 clext_1012ae(struct bregs *regs)
599 regs->al = 0x01; // High Refresh 75Hz
603 clext_1012XX(struct bregs *regs)
609 clext_1012(struct bregs *regs)
612 case 0x80: clext_101280(regs); break;
613 case 0x81: clext_101281(regs); break;
614 case 0x82: clext_101282(regs); break;
615 case 0x85: clext_101285(regs); break;
616 case 0x9a: clext_10129a(regs); break;
617 case 0xa0: clext_1012a0(regs); break;
618 case 0xa1: clext_1012a1(regs); break;
619 case 0xa2: clext_1012a2(regs); break;
620 case 0xae: clext_1012ae(regs); break;
621 default: clext_1012XX(regs); break;
626 /****************************************************************
628 ****************************************************************/
633 int ret = stdvga_init();
637 dprintf(1, "cirrus init\n");
638 if (! cirrus_check())
640 dprintf(1, "cirrus init 2\n");
643 int bdf = GET_GLOBAL(VgaBDF);
644 if (CONFIG_VGA_PCI && bdf >= 0)
645 lfb_addr = (pci_config_readl(bdf, PCI_BASE_ADDRESS_0)
646 & PCI_BASE_ADDRESS_MEM_MASK);
647 SET_VGA(VBE_framebuffer, lfb_addr);
648 u16 totalmem = cirrus_get_memsize();
649 SET_VGA(VBE_total_memory, totalmem * 64 * 1024);
650 SET_VGA(VBE_win_granularity, 16);
653 stdvga_sequ_write(0x0a, stdvga_sequ_read(0x0f) & 0x18);
655 stdvga_sequ_write(0x07, 0x00);
657 stdvga_grdc_write(0x31, 0x04);
658 stdvga_grdc_write(0x31, 0x00);