vgasrc/clext.c

   1 //  QEMU Cirrus CLGD 54xx VGABIOS Extension.
   2 //
   3 // Copyright (C) 2009  Kevin O'Connor <kevin@koconnor.net>
   4 //  Copyright (c) 2004 Makoto Suzuki (suzu)
   5 //
   6 // This file may be distributed under the terms of the GNU LGPLv3 license.
   7
   8 #include "clext.h" // clext_init
   9 #include "vgabios.h" // VBE_VENDOR_STRING
  10 #include "biosvar.h" // GET_GLOBAL
  11 #include "util.h" // dprintf
  12 #include "bregs.h" // struct bregs
  13 #include "stdvga.h" // VGAREG_SEQU_ADDRESS
  14 #include "pci.h" // pci_config_readl
  15 #include "pci_regs.h" // PCI_BASE_ADDRESS_0
  16
  17
  18 /****************************************************************
  19  * tables
  20  ****************************************************************/
  21
  22 /* VGA */
  23 static u16 cseq_vga[] VAR16 = {0x0007,0xffff};
  24 static u16 cgraph_vga[] VAR16 = {0x0009,0x000a,0x000b,0xffff};
  25 static u16 ccrtc_vga[] VAR16 = {0x001a,0x001b,0x001d,0xffff};
  26
  27 /* extensions */
  28 static u16 cgraph_svgacolor[] VAR16 = {
  29     0x0000,0x0001,0x0002,0x0003,0x0004,0x4005,0x0506,0x0f07,0xff08,
  30     0x0009,0x000a,0x000b,
  31     0xffff
  32 };
  33 /* 640x480x8 */
  34 static u16 cseq_640x480x8[] VAR16 = {
  35     0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
  36     0x580b,0x580c,0x580d,0x580e,
  37     0x0412,0x0013,0x2017,
  38     0x331b,0x331c,0x331d,0x331e,
  39     0xffff
  40 };
  41 static u16 ccrtc_640x480x8[] VAR16 = {
  42     0x2c11,
  43     0x5f00,0x4f01,0x4f02,0x8003,0x5204,0x1e05,0x0b06,0x3e07,
  44     0x4009,0x000c,0x000d,
  45     0xea10,0xdf12,0x5013,0x4014,0xdf15,0x0b16,0xc317,0xff18,
  46     0x001a,0x221b,0x001d,
  47     0xffff
  48 };
  49 /* 640x480x16 */
  50 static u16 cseq_640x480x16[] VAR16 = {
  51     0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1707,
  52     0x580b,0x580c,0x580d,0x580e,
  53     0x0412,0x0013,0x2017,
  54     0x331b,0x331c,0x331d,0x331e,
  55     0xffff
  56 };
  57 static u16 ccrtc_640x480x16[] VAR16 = {
  58     0x2c11,
  59     0x5f00,0x4f01,0x4f02,0x8003,0x5204,0x1e05,0x0b06,0x3e07,
  60     0x4009,0x000c,0x000d,
  61     0xea10,0xdf12,0xa013,0x4014,0xdf15,0x0b16,0xc317,0xff18,
  62     0x001a,0x221b,0x001d,
  63     0xffff
  64 };
  65 /* 640x480x24 */
  66 static u16 cseq_640x480x24[] VAR16 = {
  67     0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1507,
  68     0x580b,0x580c,0x580d,0x580e,
  69     0x0412,0x0013,0x2017,
  70     0x331b,0x331c,0x331d,0x331e,
  71     0xffff
  72 };
  73 static u16 ccrtc_640x480x24[] VAR16 = {
  74     0x2c11,
  75     0x5f00,0x4f01,0x4f02,0x8003,0x5204,0x1e05,0x0b06,0x3e07,
  76     0x4009,0x000c,0x000d,
  77     0xea10,0xdf12,0xf013,0x4014,0xdf15,0x0b16,0xc317,0xff18,
  78     0x001a,0x221b,0x001d,
  79     0xffff
  80 };
  81 /* 800x600x8 */
  82 static u16 cseq_800x600x8[] VAR16 = {
  83     0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
  84     0x230b,0x230c,0x230d,0x230e,
  85     0x0412,0x0013,0x2017,
  86     0x141b,0x141c,0x141d,0x141e,
  87     0xffff
  88 };
  89 static u16 ccrtc_800x600x8[] VAR16 = {
  90     0x2311,0x7d00,0x6301,0x6302,0x8003,0x6b04,0x1a05,0x9806,0xf007,
  91     0x6009,0x000c,0x000d,
  92     0x7d10,0x5712,0x6413,0x4014,0x5715,0x9816,0xc317,0xff18,
  93     0x001a,0x221b,0x001d,
  94     0xffff
  95 };
  96 /* 800x600x16 */
  97 static u16 cseq_800x600x16[] VAR16 = {
  98     0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1707,
  99     0x230b,0x230c,0x230d,0x230e,
 100     0x0412,0x0013,0x2017,
 101     0x141b,0x141c,0x141d,0x141e,
 102     0xffff
 103 };
 104 static u16 ccrtc_800x600x16[] VAR16 = {
 105     0x2311,0x7d00,0x6301,0x6302,0x8003,0x6b04,0x1a05,0x9806,0xf007,
 106     0x6009,0x000c,0x000d,
 107     0x7d10,0x5712,0xc813,0x4014,0x5715,0x9816,0xc317,0xff18,
 108     0x001a,0x221b,0x001d,
 109     0xffff
 110 };
 111 /* 800x600x24 */
 112 static u16 cseq_800x600x24[] VAR16 = {
 113     0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1507,
 114     0x230b,0x230c,0x230d,0x230e,
 115     0x0412,0x0013,0x2017,
 116     0x141b,0x141c,0x141d,0x141e,
 117     0xffff
 118 };
 119 static u16 ccrtc_800x600x24[] VAR16 = {
 120     0x2311,0x7d00,0x6301,0x6302,0x8003,0x6b04,0x1a05,0x9806,0xf007,
 121     0x6009,0x000c,0x000d,
 122     0x7d10,0x5712,0x2c13,0x4014,0x5715,0x9816,0xc317,0xff18,
 123     0x001a,0x321b,0x001d,
 124     0xffff
 125 };
 126 /* 1024x768x8 */
 127 static u16 cseq_1024x768x8[] VAR16 = {
 128     0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
 129     0x760b,0x760c,0x760d,0x760e,
 130     0x0412,0x0013,0x2017,
 131     0x341b,0x341c,0x341d,0x341e,
 132     0xffff
 133 };
 134 static u16 ccrtc_1024x768x8[] VAR16 = {
 135     0x2911,0xa300,0x7f01,0x7f02,0x8603,0x8304,0x9405,0x2406,0xf507,
 136     0x6009,0x000c,0x000d,
 137     0x0310,0xff12,0x8013,0x4014,0xff15,0x2416,0xc317,0xff18,
 138     0x001a,0x221b,0x001d,
 139     0xffff
 140 };
 141 /* 1024x768x16 */
 142 static u16 cseq_1024x768x16[] VAR16 = {
 143     0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1707,
 144     0x760b,0x760c,0x760d,0x760e,
 145     0x0412,0x0013,0x2017,
 146     0x341b,0x341c,0x341d,0x341e,
 147     0xffff
 148 };
 149 static u16 ccrtc_1024x768x16[] VAR16 = {
 150     0x2911,0xa300,0x7f01,0x7f02,0x8603,0x8304,0x9405,0x2406,0xf507,
 151     0x6009,0x000c,0x000d,
 152     0x0310,0xff12,0x0013,0x4014,0xff15,0x2416,0xc317,0xff18,
 153     0x001a,0x321b,0x001d,
 154     0xffff
 155 };
 156 /* 1024x768x24 */
 157 static u16 cseq_1024x768x24[] VAR16 = {
 158     0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1507,
 159     0x760b,0x760c,0x760d,0x760e,
 160     0x0412,0x0013,0x2017,
 161     0x341b,0x341c,0x341d,0x341e,
 162     0xffff
 163 };
 164 static u16 ccrtc_1024x768x24[] VAR16 = {
 165     0x2911,0xa300,0x7f01,0x7f02,0x8603,0x8304,0x9405,0x2406,0xf507,
 166     0x6009,0x000c,0x000d,
 167     0x0310,0xff12,0x8013,0x4014,0xff15,0x2416,0xc317,0xff18,
 168     0x001a,0x321b,0x001d,
 169     0xffff
 170 };
 171 /* 1280x1024x8 */
 172 static u16 cseq_1280x1024x8[] VAR16 = {
 173     0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
 174     0x760b,0x760c,0x760d,0x760e,
 175     0x0412,0x0013,0x2017,
 176     0x341b,0x341c,0x341d,0x341e,
 177     0xffff
 178 };
 179 static u16 ccrtc_1280x1024x8[] VAR16 = {
 180     0x2911,0xc300,0x9f01,0x9f02,0x8603,0x8304,0x9405,0x2406,0xf707,
 181     0x6009,0x000c,0x000d,
 182     0x0310,0xff12,0xa013,0x4014,0xff15,0x2416,0xc317,0xff18,
 183     0x001a,0x221b,0x001d,
 184     0xffff
 185 };
 186 /* 1280x1024x16 */
 187 static u16 cseq_1280x1024x16[] VAR16 = {
 188     0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1707,
 189     0x760b,0x760c,0x760d,0x760e,
 190     0x0412,0x0013,0x2017,
 191     0x341b,0x341c,0x341d,0x341e,
 192     0xffff
 193 };
 194 static u16 ccrtc_1280x1024x16[] VAR16 = {
 195     0x2911,0xc300,0x9f01,0x9f02,0x8603,0x8304,0x9405,0x2406,0xf707,
 196     0x6009,0x000c,0x000d,
 197     0x0310,0xff12,0x4013,0x4014,0xff15,0x2416,0xc317,0xff18,
 198     0x001a,0x321b,0x001d,
 199     0xffff
 200 };
 201
 202 /* 1600x1200x8 */
 203 static u16 cseq_1600x1200x8[] VAR16 = {
 204     0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
 205     0x760b,0x760c,0x760d,0x760e,
 206     0x0412,0x0013,0x2017,
 207     0x341b,0x341c,0x341d,0x341e,
 208     0xffff
 209 };
 210 static u16 ccrtc_1600x1200x8[] VAR16 = {
 211     0x2911,0xc300,0x9f01,0x9f02,0x8603,0x8304,0x9405,0x2406,0xf707,
 212     0x6009,0x000c,0x000d,
 213     0x0310,0xff12,0xc813,0x4014,0xff15,0x2416,0xc317,0xff18,
 214     0x001a,0x221b,0x001d,
 215     0xffff
 216 };
 217
 218 struct cirrus_mode_s {
 219     u16 mode;
 220     struct vgamode_s info;
 221
 222     u16 hidden_dac; /* 0x3c6 */
 223     u16 *seq; /* 0x3c4 */
 224     u16 *graph; /* 0x3ce */
 225     u16 *crtc; /* 0x3d4 */
 226 };
 227
 228 static struct cirrus_mode_s cirrus_modes[] VAR16 = {
 229     {0x5f,{MM_PACKED,640,480,8,8,16,SEG_GRAPH},0x00,
 230      cseq_640x480x8,cgraph_svgacolor,ccrtc_640x480x8},
 231     {0x64,{MM_DIRECT,640,480,16,8,16,SEG_GRAPH},0xe1,
 232      cseq_640x480x16,cgraph_svgacolor,ccrtc_640x480x16},
 233     {0x66,{MM_DIRECT,640,480,15,8,16,SEG_GRAPH},0xf0,
 234      cseq_640x480x16,cgraph_svgacolor,ccrtc_640x480x16},
 235     {0x71,{MM_DIRECT,640,480,24,8,16,SEG_GRAPH},0xe5,
 236      cseq_640x480x24,cgraph_svgacolor,ccrtc_640x480x24},
 237
 238     {0x5c,{MM_PACKED,800,600,8,8,16,SEG_GRAPH},0x00,
 239      cseq_800x600x8,cgraph_svgacolor,ccrtc_800x600x8},
 240     {0x65,{MM_DIRECT,800,600,16,8,16,SEG_GRAPH},0xe1,
 241      cseq_800x600x16,cgraph_svgacolor,ccrtc_800x600x16},
 242     {0x67,{MM_DIRECT,800,600,15,8,16,SEG_GRAPH},0xf0,
 243      cseq_800x600x16,cgraph_svgacolor,ccrtc_800x600x16},
 244
 245     {0x60,{MM_PACKED,1024,768,8,8,16,SEG_GRAPH},0x00,
 246      cseq_1024x768x8,cgraph_svgacolor,ccrtc_1024x768x8},
 247     {0x74,{MM_DIRECT,1024,768,16,8,16,SEG_GRAPH},0xe1,
 248      cseq_1024x768x16,cgraph_svgacolor,ccrtc_1024x768x16},
 249     {0x68,{MM_DIRECT,1024,768,15,8,16,SEG_GRAPH},0xf0,
 250      cseq_1024x768x16,cgraph_svgacolor,ccrtc_1024x768x16},
 251
 252     {0x78,{MM_DIRECT,800,600,24,8,16,SEG_GRAPH},0xe5,
 253      cseq_800x600x24,cgraph_svgacolor,ccrtc_800x600x24},
 254     {0x79,{MM_DIRECT,1024,768,24,8,16,SEG_GRAPH},0xe5,
 255      cseq_1024x768x24,cgraph_svgacolor,ccrtc_1024x768x24},
 256
 257     {0x6d,{MM_PACKED,1280,1024,8,8,16,SEG_GRAPH},0x00,
 258      cseq_1280x1024x8,cgraph_svgacolor,ccrtc_1280x1024x8},
 259     {0x69,{MM_DIRECT,1280,1024,15,8,16,SEG_GRAPH},0xf0,
 260      cseq_1280x1024x16,cgraph_svgacolor,ccrtc_1280x1024x16},
 261     {0x75,{MM_DIRECT,1280,1024,16,8,16,SEG_GRAPH},0xe1,
 262      cseq_1280x1024x16,cgraph_svgacolor,ccrtc_1280x1024x16},
 263
 264     {0x7b,{MM_PACKED,1600,1200,8,8,16,SEG_GRAPH},0x00,
 265      cseq_1600x1200x8,cgraph_svgacolor,ccrtc_1600x1200x8},
 266 };
 267
 268 static struct cirrus_mode_s mode_switchback VAR16 =
 269     {0xfe,{0xff},0,cseq_vga,cgraph_vga,ccrtc_vga};
 270
 271 static struct {
 272     u16 vesamode, mode;
 273 } cirrus_vesa_modelist[] VAR16 = {
 274     // 640x480x8
 275     { 0x101, 0x5f },
 276     // 640x480x15
 277     { 0x110, 0x66 },
 278     // 640x480x16
 279     { 0x111, 0x64 },
 280     // 640x480x24
 281     { 0x112, 0x71 },
 282     // 800x600x8
 283     { 0x103, 0x5c },
 284     // 800x600x15
 285     { 0x113, 0x67 },
 286     // 800x600x16
 287     { 0x114, 0x65 },
 288     // 800x600x24
 289     { 0x115, 0x78 },
 290     // 1024x768x8
 291     { 0x105, 0x60 },
 292     // 1024x768x15
 293     { 0x116, 0x68 },
 294     // 1024x768x16
 295     { 0x117, 0x74 },
 296     // 1024x768x24
 297     { 0x118, 0x79 },
 298     // 1280x1024x8
 299     { 0x107, 0x6d },
 300     // 1280x1024x15
 301     { 0x119, 0x69 },
 302     // 1280x1024x16
 303     { 0x11a, 0x75 },
 304 };
 305
 306
 307 /****************************************************************
 308  * helper functions
 309  ****************************************************************/
 310
 311 int
 312 is_cirrus_mode(struct vgamode_s *vmode_g)
 313 {
 314     return (vmode_g >= &cirrus_modes[0].info
 315             && vmode_g <= &cirrus_modes[ARRAY_SIZE(cirrus_modes)-1].info);
 316 }
 317
 318 static u16
 319 cirrus_vesamode_to_mode(u16 vesamode)
 320 {
 321     int i;
 322     for (i=0; i<ARRAY_SIZE(cirrus_vesa_modelist); i++)
 323         if (GET_GLOBAL(cirrus_vesa_modelist[i].vesamode) == vesamode)
 324             return GET_GLOBAL(cirrus_vesa_modelist[i].mode);
 325     return 0;
 326 }
 327
 328 static struct cirrus_mode_s *
 329 cirrus_get_modeentry(int mode)
 330 {
 331     int transmode = cirrus_vesamode_to_mode(mode);
 332     if (transmode)
 333         mode = transmode;
 334     struct cirrus_mode_s *table_g = cirrus_modes;
 335     while (table_g < &cirrus_modes[ARRAY_SIZE(cirrus_modes)]) {
 336         u16 tmode = GET_GLOBAL(table_g->mode);
 337         if (tmode == mode)
 338             return table_g;
 339         table_g++;
 340     }
 341     return NULL;
 342 }
 343
 344 struct vgamode_s *
 345 clext_find_mode(int mode)
 346 {
 347     struct cirrus_mode_s *table_g = cirrus_get_modeentry(mode);
 348     if (table_g)
 349         return &table_g->info;
 350     return stdvga_find_mode(mode);
 351 }
 352
 353 static void
 354 cirrus_switch_mode_setregs(u16 *data, u16 port)
 355 {
 356     for (;;) {
 357         u16 val = GET_GLOBAL(*data);
 358         if (val == 0xffff)
 359             return;
 360         outw(val, port);
 361         data++;
 362     }
 363 }
 364
 365 static void
 366 cirrus_switch_mode(struct cirrus_mode_s *table)
 367 {
 368     // Unlock cirrus special
 369     stdvga_sequ_write(0x06, 0x12);
 370     cirrus_switch_mode_setregs(GET_GLOBAL(table->seq), VGAREG_SEQU_ADDRESS);
 371     cirrus_switch_mode_setregs(GET_GLOBAL(table->graph), VGAREG_GRDC_ADDRESS);
 372     cirrus_switch_mode_setregs(GET_GLOBAL(table->crtc), stdvga_get_crtc());
 373
 374     stdvga_pelmask_write(0x00);
 375     stdvga_pelmask_read();
 376     stdvga_pelmask_read();
 377     stdvga_pelmask_read();
 378     stdvga_pelmask_read();
 379     stdvga_pelmask_write(GET_GLOBAL(table->hidden_dac));
 380     stdvga_pelmask_write(0xff);
 381
 382     u8 memmodel = GET_GLOBAL(table->info.memmodel);
 383     u8 on = 0;
 384     if (memmodel == MM_PLANAR)
 385         on = 0x41;
 386     else if (memmodel != MM_TEXT)
 387         on = 0x01;
 388     stdvga_attr_mask(0x10, 0x01, on);
 389 }
 390
 391 static u8
 392 cirrus_get_memsize(void)
 393 {
 394     // get DRAM band width
 395     u8 v = stdvga_sequ_read(0x0f);
 396     u8 x = (v >> 3) & 0x03;
 397     if (x == 0x03 && v & 0x80)
 398         // 4MB
 399         return 0x40;
 400     return 0x04 << x;
 401 }
 402
 403 static void
 404 cirrus_enable_16k_granularity(void)
 405 {
 406     stdvga_grdc_mask(0x0b, 0x00, 0x20);
 407 }
 408
 409 static void
 410 cirrus_clear_vram(u16 param)
 411 {
 412     cirrus_enable_16k_granularity();
 413     u8 count = GET_GLOBAL(VBE_total_memory) / (16 * 1024);
 414     u8 i;
 415     for (i=0; i<count; i++) {
 416         stdvga_grdc_write(0x09, i);
 417         memset16_far(SEG_GRAPH, 0, param, 16 * 1024);
 418     }
 419     stdvga_grdc_write(0x09, 0x00);
 420 }
 421
 422 int
 423 clext_set_mode(struct vgamode_s *vmode_g, int flags)
 424 {
 425     if (!is_cirrus_mode(vmode_g)) {
 426         cirrus_switch_mode(&mode_switchback);
 427         dprintf(1, "cirrus mode switch regular\n");
 428         return stdvga_set_mode(vmode_g, flags);
 429     }
 430     struct cirrus_mode_s *table_g = container_of(
 431         vmode_g, struct cirrus_mode_s, info);
 432     cirrus_switch_mode(table_g);
 433     if (!(flags & MF_LINEARFB))
 434         cirrus_enable_16k_granularity();
 435     if (!(flags & MF_NOCLEARMEM))
 436         cirrus_clear_vram(0);
 437     return 0;
 438 }
 439
 440 static int
 441 cirrus_check(void)
 442 {
 443     stdvga_sequ_write(0x06, 0x92);
 444     return stdvga_sequ_read(0x06) == 0x12;
 445 }
 446
 447
 448 /****************************************************************
 449  * extbios
 450  ****************************************************************/
 451
 452 static void
 453 clext_101280(struct bregs *regs)
 454 {
 455     u8 v = stdvga_crtc_read(stdvga_get_crtc(), 0x27);
 456     if (v == 0xa0)
 457         // 5430
 458         regs->ax = 0x0032;
 459     else if (v == 0xb8)
 460         // 5446
 461         regs->ax = 0x0039;
 462     else
 463         regs->ax = 0x00ff;
 464     regs->bx = 0x00;
 465     return;
 466 }
 467
 468 static void
 469 clext_101281(struct bregs *regs)
 470 {
 471     // XXX
 472     regs->ax = 0x0100;
 473 }
 474
 475 static void
 476 clext_101282(struct bregs *regs)
 477 {
 478     regs->al = stdvga_crtc_read(stdvga_get_crtc(), 0x27) & 0x03;
 479     regs->ah = 0xAF;
 480 }
 481
 482 static void
 483 clext_101285(struct bregs *regs)
 484 {
 485     regs->al = GET_GLOBAL(VBE_total_memory) / (64*1024);
 486 }
 487
 488 static void
 489 clext_10129a(struct bregs *regs)
 490 {
 491     regs->ax = 0x4060;
 492     regs->cx = 0x1132;
 493 }
 494
 495 extern void a0h_callback(void);
 496 ASM16(
 497     // fatal: not implemented yet
 498     "a0h_callback:"
 499     "cli\n"
 500     "hlt\n"
 501     "retf");
 502
 503 static void
 504 clext_1012a0(struct bregs *regs)
 505 {
 506     struct cirrus_mode_s *table_g = cirrus_get_modeentry(regs->al & 0x7f);
 507     regs->ah = (table_g ? 1 : 0);
 508     regs->si = 0xffff;
 509     regs->di = regs->ds = regs->es = regs->bx = (u32)a0h_callback;
 510 }
 511
 512 static void
 513 clext_1012a1(struct bregs *regs)
 514 {
 515     regs->bx = 0x0e00; // IBM 8512/8513, color
 516 }
 517
 518 static void
 519 clext_1012a2(struct bregs *regs)
 520 {
 521     regs->al = 0x07; // HSync 31.5 - 64.0 kHz
 522 }
 523
 524 static void
 525 clext_1012ae(struct bregs *regs)
 526 {
 527     regs->al = 0x01; // High Refresh 75Hz
 528 }
 529
 530 static void
 531 clext_1012XX(struct bregs *regs)
 532 {
 533     debug_stub(regs);
 534 }
 535
 536 void
 537 clext_1012(struct bregs *regs)
 538 {
 539     switch (regs->bl) {
 540     case 0x80: clext_101280(regs); break;
 541     case 0x81: clext_101281(regs); break;
 542     case 0x82: clext_101282(regs); break;
 543     case 0x85: clext_101285(regs); break;
 544     case 0x9a: clext_10129a(regs); break;
 545     case 0xa0: clext_1012a0(regs); break;
 546     case 0xa1: clext_1012a1(regs); break;
 547     case 0xa2: clext_1012a2(regs); break;
 548     case 0xae: clext_1012ae(regs); break;
 549     default:   clext_1012XX(regs); break;
 550     }
 551 }
 552
 553
 554 /****************************************************************
 555  * vesa calls
 556  ****************************************************************/
 557
 558 void
 559 clext_list_modes(u16 seg, u16 *dest, u16 *last)
 560 {
 561     int i;
 562     for (i=0; i<ARRAY_SIZE(cirrus_vesa_modelist) && dest<last; i++) {
 563         SET_FARVAR(seg, *dest, GET_GLOBAL(cirrus_vesa_modelist[i].vesamode));
 564         dest++;
 565     }
 566     stdvga_list_modes(seg, dest, last);
 567 }
 568
 569 static u8
 570 cirrus_get_bpp_bytes(void)
 571 {
 572     u8 v = stdvga_sequ_read(0x07) & 0x0e;
 573     if (v == 0x06)
 574         v &= 0x02;
 575     v >>= 1;
 576     if (v != 0x04)
 577         v++;
 578     return v;
 579 }
 580
 581 static void
 582 cirrus_set_line_offset(u16 new_line_offset)
 583 {
 584     new_line_offset /= 8;
 585     u16 crtc_addr = stdvga_get_crtc();
 586     stdvga_crtc_write(crtc_addr, 0x13, new_line_offset);
 587     stdvga_crtc_mask(crtc_addr, 0x1b, 0x10, (new_line_offset & 0x100) >> 4);
 588 }
 589
 590 static u16
 591 cirrus_get_line_offset(void)
 592 {
 593     u16 crtc_addr = stdvga_get_crtc();
 594     u8 reg13 = stdvga_crtc_read(crtc_addr, 0x13);
 595     u8 reg1b = stdvga_crtc_read(crtc_addr, 0x1b);
 596     return (((reg1b & 0x10) << 4) + reg13) * 8;
 597 }
 598
 599 static void
 600 cirrus_set_start_addr(u32 addr)
 601 {
 602     u16 crtc_addr = stdvga_get_crtc();
 603     stdvga_crtc_write(crtc_addr, 0x0d, addr);
 604     stdvga_crtc_write(crtc_addr, 0x0c, addr >> 8);
 605     stdvga_crtc_mask(crtc_addr, 0x1d, 0x80, (addr & 0x0800) >> 4);
 606     stdvga_crtc_mask(crtc_addr, 0x1b, 0x0d
 607                      , ((addr & 0x0100) >> 8) | ((addr & 0x0600) >> 7));
 608 }
 609
 610 static u32
 611 cirrus_get_start_addr(void)
 612 {
 613     u16 crtc_addr = stdvga_get_crtc();
 614     u8 b2 = stdvga_crtc_read(crtc_addr, 0x0c);
 615     u8 b1 = stdvga_crtc_read(crtc_addr, 0x0d);
 616     u8 b3 = stdvga_crtc_read(crtc_addr, 0x1b);
 617     u8 b4 = stdvga_crtc_read(crtc_addr, 0x1d);
 618     return (b1 | (b2<<8) | ((b3 & 0x01) << 16) | ((b3 & 0x0c) << 15)
 619             | ((b4 & 0x80) << 12));
 620 }
 621
 622 static void
 623 cirrus_vesa_05h(struct bregs *regs)
 624 {
 625     if (regs->bl > 1)
 626         goto fail;
 627     if (regs->bh == 0) {
 628         // set mempage
 629         if (regs->dx >= 0x100)
 630             goto fail;
 631         stdvga_grdc_write(regs->bl + 9, regs->dx);
 632     } else if (regs->bh == 1) {
 633         // get mempage
 634         regs->dx = stdvga_grdc_read(regs->bl + 9);
 635     } else
 636         goto fail;
 637
 638     regs->ax = 0x004f;
 639     return;
 640 fail:
 641     regs->ax = 0x014f;
 642 }
 643
 644 static void
 645 cirrus_vesa_06h(struct bregs *regs)
 646 {
 647     if (regs->bl > 2) {
 648         regs->ax = 0x0100;
 649         return;
 650     }
 651
 652     if (regs->bl == 0x00) {
 653         cirrus_set_line_offset(cirrus_get_bpp_bytes() * regs->cx);
 654     } else if (regs->bl == 0x02) {
 655         cirrus_set_line_offset(regs->cx);
 656     }
 657
 658     u32 v = cirrus_get_line_offset();
 659     regs->cx = v / cirrus_get_bpp_bytes();
 660     regs->bx = v;
 661     regs->dx = GET_GLOBAL(VBE_total_memory) / v;
 662     regs->ax = 0x004f;
 663 }
 664
 665 static void
 666 cirrus_vesa_07h(struct bregs *regs)
 667 {
 668     if (regs->bl == 0x80 || regs->bl == 0x00) {
 669         u32 addr = (cirrus_get_bpp_bytes() * regs->cx
 670                     + cirrus_get_line_offset() * regs->dx);
 671         cirrus_set_start_addr(addr / 4);
 672     } else if (regs->bl == 0x01) {
 673         u32 addr = cirrus_get_start_addr() * 4;
 674         u32 linelength = cirrus_get_line_offset();
 675         regs->dx = addr / linelength;
 676         regs->cx = (addr % linelength) / cirrus_get_bpp_bytes();
 677     } else {
 678         regs->ax = 0x0100;
 679         return;
 680     }
 681
 682     regs->ax = 0x004f;
 683 }
 684
 685 static void
 686 cirrus_vesa_10h(struct bregs *regs)
 687 {
 688     if (regs->bl == 0x00) {
 689         regs->bx = 0x0f30;
 690         regs->ax = 0x004f;
 691         return;
 692     }
 693     if (regs->bl == 0x01) {
 694         SET_BDA(vbe_flag, regs->bh);
 695         regs->ax = 0x004f;
 696         return;
 697     }
 698     if (regs->bl == 0x02) {
 699         regs->bh = GET_BDA(vbe_flag);
 700         regs->ax = 0x004f;
 701         return;
 702     }
 703     regs->ax = 0x014f;
 704 }
 705
 706 static void
 707 cirrus_vesa_not_handled(struct bregs *regs)
 708 {
 709     debug_stub(regs);
 710     regs->ax = 0x014f;
 711 }
 712
 713 void
 714 cirrus_vesa(struct bregs *regs)
 715 {
 716     switch (regs->al) {
 717     case 0x05: cirrus_vesa_05h(regs); break;
 718     case 0x06: cirrus_vesa_06h(regs); break;
 719     case 0x07: cirrus_vesa_07h(regs); break;
 720     case 0x10: cirrus_vesa_10h(regs); break;
 721     default:   cirrus_vesa_not_handled(regs); break;
 722     }
 723 }
 724
 725
 726 /****************************************************************
 727  * init
 728  ****************************************************************/
 729
 730 int
 731 clext_init(void)
 732 {
 733     int ret = stdvga_init();
 734     if (ret)
 735         return ret;
 736
 737     dprintf(1, "cirrus init\n");
 738     if (! cirrus_check())
 739         return -1;
 740     dprintf(1, "cirrus init 2\n");
 741
 742     u32 lfb_addr = 0;
 743     int bdf = GET_GLOBAL(VgaBDF);
 744     if (CONFIG_VGA_PCI && bdf >= 0)
 745         lfb_addr = (pci_config_readl(bdf, PCI_BASE_ADDRESS_0)
 746                     & PCI_BASE_ADDRESS_MEM_MASK);
 747     SET_VGA(VBE_framebuffer, lfb_addr);
 748     u16 totalmem = cirrus_get_memsize();
 749     SET_VGA(VBE_total_memory, totalmem * 64 * 1024);
 750     SET_VGA(VBE_win_granularity, 16);
 751
 752     // memory setup
 753     stdvga_sequ_write(0x0a, stdvga_sequ_read(0x0f) & 0x18);
 754     // set vga mode
 755     stdvga_sequ_write(0x07, 0x00);
 756     // reset bitblt
 757     stdvga_grdc_write(0x31, 0x04);
 758     stdvga_grdc_write(0x31, 0x00);
 759
 760     return 0;
 761 }