1 #include "vgabios.h" // struct vbe_modeinfo
2 #include "vbe.h" // VBE_MODE_VESA_DEFINED
3 #include "bochsvga.h" // bochsvga_set_mode
4 #include "util.h" // dprintf
5 #include "config.h" // CONFIG_*
6 #include "biosvar.h" // SET_BDA
7 #include "stdvga.h" // VGAREG_SEQU_ADDRESS
8 #include "pci.h" // pci_config_readl
9 #include "pci_regs.h" // PCI_BASE_ADDRESS_0
11 static struct bochsvga_mode
14 struct vgamode_s info;
15 } bochsvga_modes[] VAR16 = {
17 { 0x100, { MM_PACKED, 640, 400, 8, 8, 16, SEG_GRAPH } },
18 { 0x101, { MM_PACKED, 640, 480, 8, 8, 16, SEG_GRAPH } },
19 { 0x102, { MM_PLANAR, 800, 600, 4, 8, 16, SEG_GRAPH } },
20 { 0x103, { MM_PACKED, 800, 600, 8, 8, 16, SEG_GRAPH } },
21 { 0x104, { MM_PLANAR, 1024, 768, 4, 8, 16, SEG_GRAPH } },
22 { 0x105, { MM_PACKED, 1024, 768, 8, 8, 16, SEG_GRAPH } },
23 { 0x106, { MM_PLANAR, 1280, 1024, 4, 8, 16, SEG_GRAPH } },
24 { 0x107, { MM_PACKED, 1280, 1024, 8, 8, 16, SEG_GRAPH } },
25 { 0x10D, { MM_DIRECT, 320, 200, 15, 8, 16, SEG_GRAPH } },
26 { 0x10E, { MM_DIRECT, 320, 200, 16, 8, 16, SEG_GRAPH } },
27 { 0x10F, { MM_DIRECT, 320, 200, 24, 8, 16, SEG_GRAPH } },
28 { 0x110, { MM_DIRECT, 640, 480, 15, 8, 16, SEG_GRAPH } },
29 { 0x111, { MM_DIRECT, 640, 480, 16, 8, 16, SEG_GRAPH } },
30 { 0x112, { MM_DIRECT, 640, 480, 24, 8, 16, SEG_GRAPH } },
31 { 0x113, { MM_DIRECT, 800, 600, 15, 8, 16, SEG_GRAPH } },
32 { 0x114, { MM_DIRECT, 800, 600, 16, 8, 16, SEG_GRAPH } },
33 { 0x115, { MM_DIRECT, 800, 600, 24, 8, 16, SEG_GRAPH } },
34 { 0x116, { MM_DIRECT, 1024, 768, 15, 8, 16, SEG_GRAPH } },
35 { 0x117, { MM_DIRECT, 1024, 768, 16, 8, 16, SEG_GRAPH } },
36 { 0x118, { MM_DIRECT, 1024, 768, 24, 8, 16, SEG_GRAPH } },
37 { 0x119, { MM_DIRECT, 1280, 1024, 15, 8, 16, SEG_GRAPH } },
38 { 0x11A, { MM_DIRECT, 1280, 1024, 16, 8, 16, SEG_GRAPH } },
39 { 0x11B, { MM_DIRECT, 1280, 1024, 24, 8, 16, SEG_GRAPH } },
40 { 0x11C, { MM_PACKED, 1600, 1200, 8, 8, 16, SEG_GRAPH } },
41 { 0x11D, { MM_DIRECT, 1600, 1200, 15, 8, 16, SEG_GRAPH } },
42 { 0x11E, { MM_DIRECT, 1600, 1200, 16, 8, 16, SEG_GRAPH } },
43 { 0x11F, { MM_DIRECT, 1600, 1200, 24, 8, 16, SEG_GRAPH } },
45 { 0x140, { MM_DIRECT, 320, 200, 32, 8, 16, SEG_GRAPH } },
46 { 0x141, { MM_DIRECT, 640, 400, 32, 8, 16, SEG_GRAPH } },
47 { 0x142, { MM_DIRECT, 640, 480, 32, 8, 16, SEG_GRAPH } },
48 { 0x143, { MM_DIRECT, 800, 600, 32, 8, 16, SEG_GRAPH } },
49 { 0x144, { MM_DIRECT, 1024, 768, 32, 8, 16, SEG_GRAPH } },
50 { 0x145, { MM_DIRECT, 1280, 1024, 32, 8, 16, SEG_GRAPH } },
51 { 0x146, { MM_PACKED, 320, 200, 8, 8, 16, SEG_GRAPH } },
52 { 0x147, { MM_DIRECT, 1600, 1200, 32, 8, 16, SEG_GRAPH } },
53 { 0x148, { MM_PACKED, 1152, 864, 8, 8, 16, SEG_GRAPH } },
54 { 0x149, { MM_DIRECT, 1152, 864, 15, 8, 16, SEG_GRAPH } },
55 { 0x14a, { MM_DIRECT, 1152, 864, 16, 8, 16, SEG_GRAPH } },
56 { 0x14b, { MM_DIRECT, 1152, 864, 24, 8, 16, SEG_GRAPH } },
57 { 0x14c, { MM_DIRECT, 1152, 864, 32, 8, 16, SEG_GRAPH } },
58 { 0x178, { MM_DIRECT, 1280, 800, 16, 8, 16, SEG_GRAPH } },
59 { 0x179, { MM_DIRECT, 1280, 800, 24, 8, 16, SEG_GRAPH } },
60 { 0x17a, { MM_DIRECT, 1280, 800, 32, 8, 16, SEG_GRAPH } },
61 { 0x17b, { MM_DIRECT, 1280, 960, 16, 8, 16, SEG_GRAPH } },
62 { 0x17c, { MM_DIRECT, 1280, 960, 24, 8, 16, SEG_GRAPH } },
63 { 0x17d, { MM_DIRECT, 1280, 960, 32, 8, 16, SEG_GRAPH } },
64 { 0x17e, { MM_DIRECT, 1440, 900, 16, 8, 16, SEG_GRAPH } },
65 { 0x17f, { MM_DIRECT, 1440, 900, 24, 8, 16, SEG_GRAPH } },
66 { 0x180, { MM_DIRECT, 1440, 900, 32, 8, 16, SEG_GRAPH } },
67 { 0x181, { MM_DIRECT, 1400, 1050, 16, 8, 16, SEG_GRAPH } },
68 { 0x182, { MM_DIRECT, 1400, 1050, 24, 8, 16, SEG_GRAPH } },
69 { 0x183, { MM_DIRECT, 1400, 1050, 32, 8, 16, SEG_GRAPH } },
70 { 0x184, { MM_DIRECT, 1680, 1050, 16, 8, 16, SEG_GRAPH } },
71 { 0x185, { MM_DIRECT, 1680, 1050, 24, 8, 16, SEG_GRAPH } },
72 { 0x186, { MM_DIRECT, 1680, 1050, 32, 8, 16, SEG_GRAPH } },
73 { 0x187, { MM_DIRECT, 1920, 1200, 16, 8, 16, SEG_GRAPH } },
74 { 0x188, { MM_DIRECT, 1920, 1200, 24, 8, 16, SEG_GRAPH } },
75 { 0x189, { MM_DIRECT, 1920, 1200, 32, 8, 16, SEG_GRAPH } },
76 { 0x18a, { MM_DIRECT, 2560, 1600, 16, 8, 16, SEG_GRAPH } },
77 { 0x18b, { MM_DIRECT, 2560, 1600, 24, 8, 16, SEG_GRAPH } },
78 { 0x18c, { MM_DIRECT, 2560, 1600, 32, 8, 16, SEG_GRAPH } },
81 static u16 dispi_get_max_xres(void)
86 en = dispi_read(VBE_DISPI_INDEX_ENABLE);
88 dispi_write(VBE_DISPI_INDEX_ENABLE, en | VBE_DISPI_GETCAPS);
89 xres = dispi_read(VBE_DISPI_INDEX_XRES);
90 dispi_write(VBE_DISPI_INDEX_ENABLE, en);
95 static u16 dispi_get_max_bpp(void)
100 en = dispi_read(VBE_DISPI_INDEX_ENABLE);
102 dispi_write(VBE_DISPI_INDEX_ENABLE, en | VBE_DISPI_GETCAPS);
103 bpp = dispi_read(VBE_DISPI_INDEX_BPP);
104 dispi_write(VBE_DISPI_INDEX_ENABLE, en);
109 /* Called only during POST */
113 int ret = stdvga_init();
118 dispi_write(VBE_DISPI_INDEX_ID, VBE_DISPI_ID0);
119 if (dispi_read(VBE_DISPI_INDEX_ID) != VBE_DISPI_ID0) {
120 dprintf(1, "No VBE DISPI interface detected\n");
124 dispi_write(VBE_DISPI_INDEX_ID, VBE_DISPI_ID5);
126 u32 lfb_addr = VBE_DISPI_LFB_PHYSICAL_ADDRESS;
127 int bdf = GET_GLOBAL(VgaBDF);
128 if (CONFIG_VGA_PCI && bdf >= 0)
129 lfb_addr = (pci_config_readl(bdf, PCI_BASE_ADDRESS_0)
130 & PCI_BASE_ADDRESS_MEM_MASK);
132 SET_VGA(VBE_framebuffer, lfb_addr);
133 u16 totalmem = dispi_read(VBE_DISPI_INDEX_VIDEO_MEMORY_64K);
134 SET_VGA(VBE_total_memory, totalmem * 64 * 1024);
135 SET_VGA(VBE_capabilities, VBE_CAPABILITY_8BIT_DAC);
137 dprintf(1, "VBE DISPI detected. lfb_addr=%x\n", lfb_addr);
142 static int mode_valid(struct vgamode_s *vmode_g)
144 u16 max_xres = dispi_get_max_xres();
145 u16 max_bpp = dispi_get_max_bpp();
146 u32 max_mem = GET_GLOBAL(VBE_total_memory);
148 u16 width = GET_GLOBAL(vmode_g->width);
149 u16 height = GET_GLOBAL(vmode_g->height);
150 u8 depth = GET_GLOBAL(vmode_g->depth);
151 u32 mem = width * height * DIV_ROUND_UP(depth, 8);
153 return width <= max_xres && depth <= max_bpp && mem <= max_mem;
156 struct vgamode_s *bochsvga_find_mode(int mode)
158 struct bochsvga_mode *m = bochsvga_modes;
159 for (; m < &bochsvga_modes[ARRAY_SIZE(bochsvga_modes)]; m++)
160 if (GET_GLOBAL(m->mode) == mode) {
161 if (! mode_valid(&m->info))
165 return stdvga_find_mode(mode);
169 bochsvga_list_modes(u16 seg, u16 *dest, u16 *last)
171 struct bochsvga_mode *m = bochsvga_modes;
172 for (; m < &bochsvga_modes[ARRAY_SIZE(bochsvga_modes)] && dest<last; m++) {
173 if (!mode_valid(&m->info))
176 dprintf(1, "VBE found mode %x valid.\n", GET_GLOBAL(m->mode));
177 SET_FARVAR(seg, *dest, GET_GLOBAL(m->mode));
181 stdvga_list_modes(seg, dest, last);
185 bochsvga_hires_enable(int enable)
189 VBE_DISPI_LFB_ENABLED |
190 VBE_DISPI_NOCLEARMEM : 0;
192 dispi_write(VBE_DISPI_INDEX_ENABLE, flags);
196 bochsvga_clear_scr(void)
200 en = dispi_read(VBE_DISPI_INDEX_ENABLE);
201 en &= ~VBE_DISPI_NOCLEARMEM;
202 dispi_write(VBE_DISPI_INDEX_ENABLE, en);
206 bochsvga_set_mode(int mode, int flags)
208 if (!(mode & VBE_MODE_VESA_DEFINED)) {
209 dprintf(1, "set VGA mode %x\n", mode);
211 SET_BDA(vbe_mode, 0);
212 bochsvga_hires_enable(0);
213 return stdvga_set_mode(mode, flags);
216 struct vgamode_s *vmode_g = bochsvga_find_mode(mode);
218 dprintf(1, "VBE mode %x not found\n", mode);
219 return VBE_RETURN_STATUS_FAILED;
221 bochsvga_hires_enable(1);
223 u8 depth = GET_GLOBAL(vmode_g->depth);
225 stdvga_set_mode(0x6a, 0);
227 // XXX load_dac_palette(3);
230 dispi_write(VBE_DISPI_INDEX_BPP, depth);
231 u16 width = GET_GLOBAL(vmode_g->width);
232 u16 height = GET_GLOBAL(vmode_g->height);
233 dispi_write(VBE_DISPI_INDEX_XRES, width);
234 dispi_write(VBE_DISPI_INDEX_YRES, height);
235 dispi_write(VBE_DISPI_INDEX_BANK, 0);
237 /* VGA compat setup */
238 //XXX: This probably needs some reverse engineering
239 u16 crtc_addr = VGAREG_VGA_CRTC_ADDRESS;
240 stdvga_crtc_write(crtc_addr, 0x11, 0x00);
241 stdvga_crtc_write(crtc_addr, 0x01, width / 8 - 1);
242 dispi_write(VBE_DISPI_INDEX_VIRT_WIDTH, width);
243 stdvga_crtc_write(crtc_addr, 0x12, height - 1);
245 if ((height - 1) & 0x0100)
247 if ((height - 1) & 0x0200)
249 stdvga_crtc_mask(crtc_addr, 0x07, 0x42, v);
251 stdvga_crtc_write(crtc_addr, 0x09, 0x00);
252 stdvga_crtc_mask(crtc_addr, 0x17, 0x00, 0x03);
253 stdvga_attr_mask(0x10, 0x00, 0x01);
254 stdvga_grdc_write(0x06, 0x05);
255 stdvga_sequ_write(0x02, 0x0f);
257 stdvga_crtc_mask(crtc_addr, 0x14, 0x00, 0x40);
258 stdvga_attr_mask(0x10, 0x00, 0x40);
259 stdvga_sequ_mask(0x04, 0x00, 0x08);
260 stdvga_grdc_mask(0x05, 0x20, 0x40);
263 SET_BDA(vbe_mode, mode | flags);
265 if (flags & MF_LINEARFB) {
266 /* Linear frame buffer */
269 if (!(mode & MF_NOCLEARMEM)) {
270 bochsvga_clear_scr();