1 #include "vgabios.h" // struct vbe_modeinfo
2 #include "vbe.h" // VBE_MODE_VESA_DEFINED
3 #include "bochsvga.h" // bochsvga_set_mode
4 #include "util.h" // dprintf
5 #include "config.h" // CONFIG_*
6 #include "biosvar.h" // SET_BDA
7 #include "stdvga.h" // VGAREG_SEQU_ADDRESS
9 static struct bochsvga_mode
12 struct vgamode_s info;
13 } bochsvga_modes[] VAR16 = {
15 { 0x100, { MM_PACKED, 640, 400, 8 } },
16 { 0x101, { MM_PACKED, 640, 480, 8 } },
17 { 0x102, { MM_PLANAR, 800, 600, 4 } },
18 { 0x103, { MM_PACKED, 800, 600, 8 } },
19 { 0x104, { MM_PLANAR, 1024, 768, 4 } },
20 { 0x105, { MM_PACKED, 1024, 768, 8 } },
21 { 0x106, { MM_PLANAR, 1280, 1024, 4 } },
22 { 0x107, { MM_PACKED, 1280, 1024, 8 } },
23 { 0x10D, { MM_DIRECT, 320, 200, 15 } },
24 { 0x10E, { MM_DIRECT, 320, 200, 16 } },
25 { 0x10F, { MM_DIRECT, 320, 200, 24 } },
26 { 0x110, { MM_DIRECT, 640, 480, 15 } },
27 { 0x111, { MM_DIRECT, 640, 480, 16 } },
28 { 0x112, { MM_DIRECT, 640, 480, 24 } },
29 { 0x113, { MM_DIRECT, 800, 600, 15 } },
30 { 0x114, { MM_DIRECT, 800, 600, 16 } },
31 { 0x115, { MM_DIRECT, 800, 600, 24 } },
32 { 0x116, { MM_DIRECT, 1024, 768, 15 } },
33 { 0x117, { MM_DIRECT, 1024, 768, 16 } },
34 { 0x118, { MM_DIRECT, 1024, 768, 24 } },
35 { 0x119, { MM_DIRECT, 1280, 1024, 15 } },
36 { 0x11A, { MM_DIRECT, 1280, 1024, 16 } },
37 { 0x11B, { MM_DIRECT, 1280, 1024, 24 } },
38 { 0x11C, { MM_PACKED, 1600, 1200, 8 } },
39 { 0x11D, { MM_DIRECT, 1600, 1200, 15 } },
40 { 0x11E, { MM_DIRECT, 1600, 1200, 16 } },
41 { 0x11F, { MM_DIRECT, 1600, 1200, 24 } },
43 { 0x140, { MM_DIRECT, 320, 200, 32 } },
44 { 0x141, { MM_DIRECT, 640, 400, 32 } },
45 { 0x142, { MM_DIRECT, 640, 480, 32 } },
46 { 0x143, { MM_DIRECT, 800, 600, 32 } },
47 { 0x144, { MM_DIRECT, 1024, 768, 32 } },
48 { 0x145, { MM_DIRECT, 1280, 1024, 32 } },
49 { 0x146, { MM_PACKED, 320, 200, 8 } },
50 { 0x147, { MM_DIRECT, 1600, 1200, 32 } },
51 { 0x148, { MM_PACKED, 1152, 864, 8 } },
52 { 0x149, { MM_DIRECT, 1152, 864, 15 } },
53 { 0x14a, { MM_DIRECT, 1152, 864, 16 } },
54 { 0x14b, { MM_DIRECT, 1152, 864, 24 } },
55 { 0x14c, { MM_DIRECT, 1152, 864, 32 } },
56 { 0x178, { MM_DIRECT, 1280, 800, 16 } },
57 { 0x179, { MM_DIRECT, 1280, 800, 24 } },
58 { 0x17a, { MM_DIRECT, 1280, 800, 32 } },
59 { 0x17b, { MM_DIRECT, 1280, 960, 16 } },
60 { 0x17c, { MM_DIRECT, 1280, 960, 24 } },
61 { 0x17d, { MM_DIRECT, 1280, 960, 32 } },
62 { 0x17e, { MM_DIRECT, 1440, 900, 16 } },
63 { 0x17f, { MM_DIRECT, 1440, 900, 24 } },
64 { 0x180, { MM_DIRECT, 1440, 900, 32 } },
65 { 0x181, { MM_DIRECT, 1400, 1050, 16 } },
66 { 0x182, { MM_DIRECT, 1400, 1050, 24 } },
67 { 0x183, { MM_DIRECT, 1400, 1050, 32 } },
68 { 0x184, { MM_DIRECT, 1680, 1050, 16 } },
69 { 0x185, { MM_DIRECT, 1680, 1050, 24 } },
70 { 0x186, { MM_DIRECT, 1680, 1050, 32 } },
71 { 0x187, { MM_DIRECT, 1920, 1200, 16 } },
72 { 0x188, { MM_DIRECT, 1920, 1200, 24 } },
73 { 0x189, { MM_DIRECT, 1920, 1200, 32 } },
74 { 0x18a, { MM_DIRECT, 2560, 1600, 16 } },
75 { 0x18b, { MM_DIRECT, 2560, 1600, 24 } },
76 { 0x18c, { MM_DIRECT, 2560, 1600, 32 } },
79 static inline u32 pci_config_readl(u16 bdf, u16 addr)
90 : "=a"(status), "=c"(val)
91 : "a"(0xb10a), "b"(bdf), "D"(addr)
100 static u16 dispi_get_max_xres(void)
105 en = dispi_read(VBE_DISPI_INDEX_ENABLE);
107 dispi_write(VBE_DISPI_INDEX_ENABLE, en | VBE_DISPI_GETCAPS);
108 xres = dispi_read(VBE_DISPI_INDEX_XRES);
109 dispi_write(VBE_DISPI_INDEX_ENABLE, en);
114 static u16 dispi_get_max_bpp(void)
119 en = dispi_read(VBE_DISPI_INDEX_ENABLE);
121 dispi_write(VBE_DISPI_INDEX_ENABLE, en | VBE_DISPI_GETCAPS);
122 bpp = dispi_read(VBE_DISPI_INDEX_BPP);
123 dispi_write(VBE_DISPI_INDEX_ENABLE, en);
128 /* Called only during POST */
132 int ret = stdvga_init();
137 dispi_write(VBE_DISPI_INDEX_ID, VBE_DISPI_ID0);
138 if (dispi_read(VBE_DISPI_INDEX_ID) != VBE_DISPI_ID0) {
139 dprintf(1, "No VBE DISPI interface detected\n");
143 SET_VGA(VBE_enabled, 1);
144 dispi_write(VBE_DISPI_INDEX_ID, VBE_DISPI_ID5);
148 lfb_addr = pci_config_readl(GET_GLOBAL(VgaBDF), 0x10) & ~0xf;
150 lfb_addr = VBE_DISPI_LFB_PHYSICAL_ADDRESS;
152 SET_VGA(VBE_framebuffer, lfb_addr);
153 u16 totalmem = dispi_read(VBE_DISPI_INDEX_VIDEO_MEMORY_64K);
154 SET_VGA(VBE_total_memory, totalmem * 64 * 1024);
155 SET_VGA(VBE_capabilities, VBE_CAPABILITY_8BIT_DAC);
157 dprintf(1, "VBE DISPI detected. lfb_addr=%x\n", lfb_addr);
162 static int mode_valid(struct vgamode_s *vmode_g)
164 u16 max_xres = dispi_get_max_xres();
165 u16 max_bpp = dispi_get_max_bpp();
166 u32 max_mem = GET_GLOBAL(VBE_total_memory);
168 u16 width = GET_GLOBAL(vmode_g->width);
169 u16 height = GET_GLOBAL(vmode_g->height);
170 u8 depth = GET_GLOBAL(vmode_g->depth);
171 u32 mem = width * height * DIV_ROUND_UP(depth, 8);
173 return width <= max_xres && depth <= max_bpp && mem <= max_mem;
176 struct vgamode_s *bochsvga_find_mode(int mode)
178 struct bochsvga_mode *m = bochsvga_modes;
179 for (; m < &bochsvga_modes[ARRAY_SIZE(bochsvga_modes)]; m++)
180 if (GET_GLOBAL(m->mode) == mode) {
181 if (! mode_valid(&m->info))
185 return stdvga_find_mode(mode);
189 bochsvga_list_modes(u16 seg, u16 *dest, u16 *last)
191 struct bochsvga_mode *m = bochsvga_modes;
192 for (; m < &bochsvga_modes[ARRAY_SIZE(bochsvga_modes)] && dest<last; m++) {
193 if (!mode_valid(&m->info))
196 dprintf(1, "VBE found mode %x valid.\n", GET_GLOBAL(m->mode));
197 SET_FARVAR(seg, *dest, GET_GLOBAL(m->mode));
201 stdvga_list_modes(seg, dest, last);
205 bochsvga_hires_enable(int enable)
209 VBE_DISPI_LFB_ENABLED |
210 VBE_DISPI_NOCLEARMEM : 0;
212 dispi_write(VBE_DISPI_INDEX_ENABLE, flags);
216 bochsvga_clear_scr(void)
220 en = dispi_read(VBE_DISPI_INDEX_ENABLE);
221 en &= ~VBE_DISPI_NOCLEARMEM;
222 dispi_write(VBE_DISPI_INDEX_ENABLE, en);
226 bochsvga_set_mode(int mode, int flags)
228 if (!(mode & VBE_MODE_VESA_DEFINED)) {
229 dprintf(1, "set VGA mode %x\n", mode);
231 SET_BDA(vbe_mode, 0);
232 bochsvga_hires_enable(0);
233 return stdvga_set_mode(mode, flags);
236 struct vgamode_s *vmode_g = bochsvga_find_mode(mode);
238 dprintf(1, "VBE mode %x not found\n", mode);
239 return VBE_RETURN_STATUS_FAILED;
241 bochsvga_hires_enable(1);
243 u8 depth = GET_GLOBAL(vmode_g->depth);
245 stdvga_set_mode(0x6a, 0);
247 // XXX load_dac_palette(3);
250 dispi_write(VBE_DISPI_INDEX_BPP, depth);
251 u16 width = GET_GLOBAL(vmode_g->width);
252 u16 height = GET_GLOBAL(vmode_g->height);
253 dispi_write(VBE_DISPI_INDEX_XRES, width);
254 dispi_write(VBE_DISPI_INDEX_YRES, height);
255 dispi_write(VBE_DISPI_INDEX_BANK, 0);
257 /* VGA compat setup */
258 //XXX: This probably needs some reverse engineering
260 outw(0x0011, VGAREG_VGA_CRTC_ADDRESS);
261 outw(((width * 4 - 1) << 8) | 0x1, VGAREG_VGA_CRTC_ADDRESS);
262 dispi_write(VBE_DISPI_INDEX_VIRT_WIDTH, width);
263 outw(((height - 1) << 8) | 0x12, VGAREG_VGA_CRTC_ADDRESS);
264 outw(((height - 1) & 0xff00) | 0x7, VGAREG_VGA_CRTC_ADDRESS);
265 v = inb(VGAREG_VGA_CRTC_DATA) & 0xbd;
270 outb(v, VGAREG_VGA_CRTC_DATA);
272 outw(0x9, VGAREG_VGA_CRTC_ADDRESS);
273 outb(0x17, VGAREG_VGA_CRTC_ADDRESS);
274 outb(inb(VGAREG_VGA_CRTC_DATA) | 0x3, VGAREG_VGA_CRTC_DATA);
275 v = inb(VGAREG_ACTL_RESET);
276 outw(0x10, VGAREG_ACTL_ADDRESS);
277 v = inb(VGAREG_ACTL_READ_DATA) | 0x1;
278 outb(v, VGAREG_ACTL_ADDRESS);
279 outb(0x20, VGAREG_ACTL_ADDRESS);
280 outw(0x0506, VGAREG_GRDC_ADDRESS);
281 outw(0x0f02, VGAREG_SEQU_ADDRESS);
283 outb(0x14, VGAREG_VGA_CRTC_ADDRESS);
284 outb(inb(VGAREG_VGA_CRTC_DATA) | 0x40, VGAREG_VGA_CRTC_DATA);
285 v = inb(VGAREG_ACTL_RESET);
286 outw(0x10, VGAREG_ACTL_ADDRESS);
287 v = inb(VGAREG_ACTL_READ_DATA) | 0x40;
288 outb(v, VGAREG_ACTL_ADDRESS);
289 outb(0x20, VGAREG_ACTL_ADDRESS);
290 outb(0x04, VGAREG_SEQU_ADDRESS);
291 v = inb(VGAREG_SEQU_DATA) | 0x08;
292 outb(v, VGAREG_SEQU_DATA);
293 outb(0x05, VGAREG_GRDC_ADDRESS);
294 v = inb(VGAREG_GRDC_DATA) & 0x9f;
295 outb(v | 0x40, VGAREG_GRDC_DATA);
298 SET_BDA(vbe_mode, mode | flags);
300 if (flags & MF_LINEARFB) {
301 /* Linear frame buffer */
304 if (!(mode & MF_NOCLEARMEM)) {
305 bochsvga_clear_scr();