1 // Bochs VGA interface to extended "VBE" modes
3 // Copyright (C) 2012 Kevin O'Connor <kevin@koconnor.net>
4 // Copyright (C) 2011 Julian Pidancet <julian.pidancet@citrix.com>
5 // Copyright (C) 2002 Jeroen Janssen
7 // This file may be distributed under the terms of the GNU LGPLv3 license.
9 #include "vgabios.h" // struct vbe_modeinfo
10 #include "vbe.h" // VBE_CAPABILITY_8BIT_DAC
11 #include "bochsvga.h" // bochsvga_set_mode
12 #include "util.h" // dprintf
13 #include "config.h" // CONFIG_*
14 #include "biosvar.h" // GET_GLOBAL
15 #include "stdvga.h" // VGAREG_SEQU_ADDRESS
16 #include "pci.h" // pci_config_readl
17 #include "pci_regs.h" // PCI_BASE_ADDRESS_0
19 static struct bochsvga_mode
22 struct vgamode_s info;
23 } bochsvga_modes[] VAR16 = {
25 { 0x100, { MM_PACKED, 640, 400, 8, 8, 16, SEG_GRAPH } },
26 { 0x101, { MM_PACKED, 640, 480, 8, 8, 16, SEG_GRAPH } },
27 { 0x102, { MM_PLANAR, 800, 600, 4, 8, 16, SEG_GRAPH } },
28 { 0x103, { MM_PACKED, 800, 600, 8, 8, 16, SEG_GRAPH } },
29 { 0x104, { MM_PLANAR, 1024, 768, 4, 8, 16, SEG_GRAPH } },
30 { 0x105, { MM_PACKED, 1024, 768, 8, 8, 16, SEG_GRAPH } },
31 { 0x106, { MM_PLANAR, 1280, 1024, 4, 8, 16, SEG_GRAPH } },
32 { 0x107, { MM_PACKED, 1280, 1024, 8, 8, 16, SEG_GRAPH } },
33 { 0x10D, { MM_DIRECT, 320, 200, 15, 8, 16, SEG_GRAPH } },
34 { 0x10E, { MM_DIRECT, 320, 200, 16, 8, 16, SEG_GRAPH } },
35 { 0x10F, { MM_DIRECT, 320, 200, 24, 8, 16, SEG_GRAPH } },
36 { 0x110, { MM_DIRECT, 640, 480, 15, 8, 16, SEG_GRAPH } },
37 { 0x111, { MM_DIRECT, 640, 480, 16, 8, 16, SEG_GRAPH } },
38 { 0x112, { MM_DIRECT, 640, 480, 24, 8, 16, SEG_GRAPH } },
39 { 0x113, { MM_DIRECT, 800, 600, 15, 8, 16, SEG_GRAPH } },
40 { 0x114, { MM_DIRECT, 800, 600, 16, 8, 16, SEG_GRAPH } },
41 { 0x115, { MM_DIRECT, 800, 600, 24, 8, 16, SEG_GRAPH } },
42 { 0x116, { MM_DIRECT, 1024, 768, 15, 8, 16, SEG_GRAPH } },
43 { 0x117, { MM_DIRECT, 1024, 768, 16, 8, 16, SEG_GRAPH } },
44 { 0x118, { MM_DIRECT, 1024, 768, 24, 8, 16, SEG_GRAPH } },
45 { 0x119, { MM_DIRECT, 1280, 1024, 15, 8, 16, SEG_GRAPH } },
46 { 0x11A, { MM_DIRECT, 1280, 1024, 16, 8, 16, SEG_GRAPH } },
47 { 0x11B, { MM_DIRECT, 1280, 1024, 24, 8, 16, SEG_GRAPH } },
48 { 0x11C, { MM_PACKED, 1600, 1200, 8, 8, 16, SEG_GRAPH } },
49 { 0x11D, { MM_DIRECT, 1600, 1200, 15, 8, 16, SEG_GRAPH } },
50 { 0x11E, { MM_DIRECT, 1600, 1200, 16, 8, 16, SEG_GRAPH } },
51 { 0x11F, { MM_DIRECT, 1600, 1200, 24, 8, 16, SEG_GRAPH } },
53 { 0x140, { MM_DIRECT, 320, 200, 32, 8, 16, SEG_GRAPH } },
54 { 0x141, { MM_DIRECT, 640, 400, 32, 8, 16, SEG_GRAPH } },
55 { 0x142, { MM_DIRECT, 640, 480, 32, 8, 16, SEG_GRAPH } },
56 { 0x143, { MM_DIRECT, 800, 600, 32, 8, 16, SEG_GRAPH } },
57 { 0x144, { MM_DIRECT, 1024, 768, 32, 8, 16, SEG_GRAPH } },
58 { 0x145, { MM_DIRECT, 1280, 1024, 32, 8, 16, SEG_GRAPH } },
59 { 0x146, { MM_PACKED, 320, 200, 8, 8, 16, SEG_GRAPH } },
60 { 0x147, { MM_DIRECT, 1600, 1200, 32, 8, 16, SEG_GRAPH } },
61 { 0x148, { MM_PACKED, 1152, 864, 8, 8, 16, SEG_GRAPH } },
62 { 0x149, { MM_DIRECT, 1152, 864, 15, 8, 16, SEG_GRAPH } },
63 { 0x14a, { MM_DIRECT, 1152, 864, 16, 8, 16, SEG_GRAPH } },
64 { 0x14b, { MM_DIRECT, 1152, 864, 24, 8, 16, SEG_GRAPH } },
65 { 0x14c, { MM_DIRECT, 1152, 864, 32, 8, 16, SEG_GRAPH } },
66 { 0x178, { MM_DIRECT, 1280, 800, 16, 8, 16, SEG_GRAPH } },
67 { 0x179, { MM_DIRECT, 1280, 800, 24, 8, 16, SEG_GRAPH } },
68 { 0x17a, { MM_DIRECT, 1280, 800, 32, 8, 16, SEG_GRAPH } },
69 { 0x17b, { MM_DIRECT, 1280, 960, 16, 8, 16, SEG_GRAPH } },
70 { 0x17c, { MM_DIRECT, 1280, 960, 24, 8, 16, SEG_GRAPH } },
71 { 0x17d, { MM_DIRECT, 1280, 960, 32, 8, 16, SEG_GRAPH } },
72 { 0x17e, { MM_DIRECT, 1440, 900, 16, 8, 16, SEG_GRAPH } },
73 { 0x17f, { MM_DIRECT, 1440, 900, 24, 8, 16, SEG_GRAPH } },
74 { 0x180, { MM_DIRECT, 1440, 900, 32, 8, 16, SEG_GRAPH } },
75 { 0x181, { MM_DIRECT, 1400, 1050, 16, 8, 16, SEG_GRAPH } },
76 { 0x182, { MM_DIRECT, 1400, 1050, 24, 8, 16, SEG_GRAPH } },
77 { 0x183, { MM_DIRECT, 1400, 1050, 32, 8, 16, SEG_GRAPH } },
78 { 0x184, { MM_DIRECT, 1680, 1050, 16, 8, 16, SEG_GRAPH } },
79 { 0x185, { MM_DIRECT, 1680, 1050, 24, 8, 16, SEG_GRAPH } },
80 { 0x186, { MM_DIRECT, 1680, 1050, 32, 8, 16, SEG_GRAPH } },
81 { 0x187, { MM_DIRECT, 1920, 1200, 16, 8, 16, SEG_GRAPH } },
82 { 0x188, { MM_DIRECT, 1920, 1200, 24, 8, 16, SEG_GRAPH } },
83 { 0x189, { MM_DIRECT, 1920, 1200, 32, 8, 16, SEG_GRAPH } },
84 { 0x18a, { MM_DIRECT, 2560, 1600, 16, 8, 16, SEG_GRAPH } },
85 { 0x18b, { MM_DIRECT, 2560, 1600, 24, 8, 16, SEG_GRAPH } },
86 { 0x18c, { MM_DIRECT, 2560, 1600, 32, 8, 16, SEG_GRAPH } },
89 static int is_bochsvga_mode(struct vgamode_s *vmode_g)
91 return (vmode_g >= &bochsvga_modes[0].info
92 && vmode_g <= &bochsvga_modes[ARRAY_SIZE(bochsvga_modes)-1].info);
95 static u16 dispi_get_max_xres(void)
100 en = dispi_read(VBE_DISPI_INDEX_ENABLE);
102 dispi_write(VBE_DISPI_INDEX_ENABLE, en | VBE_DISPI_GETCAPS);
103 xres = dispi_read(VBE_DISPI_INDEX_XRES);
104 dispi_write(VBE_DISPI_INDEX_ENABLE, en);
109 static u16 dispi_get_max_bpp(void)
114 en = dispi_read(VBE_DISPI_INDEX_ENABLE);
116 dispi_write(VBE_DISPI_INDEX_ENABLE, en | VBE_DISPI_GETCAPS);
117 bpp = dispi_read(VBE_DISPI_INDEX_BPP);
118 dispi_write(VBE_DISPI_INDEX_ENABLE, en);
123 /* Called only during POST */
127 int ret = stdvga_init();
132 dispi_write(VBE_DISPI_INDEX_ID, VBE_DISPI_ID0);
133 if (dispi_read(VBE_DISPI_INDEX_ID) != VBE_DISPI_ID0) {
134 dprintf(1, "No VBE DISPI interface detected\n");
138 dispi_write(VBE_DISPI_INDEX_ID, VBE_DISPI_ID5);
140 u32 lfb_addr = VBE_DISPI_LFB_PHYSICAL_ADDRESS;
141 int bdf = GET_GLOBAL(VgaBDF);
142 if (CONFIG_VGA_PCI && bdf >= 0)
143 lfb_addr = (pci_config_readl(bdf, PCI_BASE_ADDRESS_0)
144 & PCI_BASE_ADDRESS_MEM_MASK);
146 SET_VGA(VBE_framebuffer, lfb_addr);
147 u16 totalmem = dispi_read(VBE_DISPI_INDEX_VIDEO_MEMORY_64K);
148 SET_VGA(VBE_total_memory, totalmem * 64 * 1024);
149 SET_VGA(VBE_capabilities, VBE_CAPABILITY_8BIT_DAC);
151 dprintf(1, "VBE DISPI detected. lfb_addr=%x\n", lfb_addr);
156 static int mode_valid(struct vgamode_s *vmode_g)
158 u16 max_xres = dispi_get_max_xres();
159 u16 max_bpp = dispi_get_max_bpp();
160 u32 max_mem = GET_GLOBAL(VBE_total_memory);
162 u16 width = GET_GLOBAL(vmode_g->width);
163 u16 height = GET_GLOBAL(vmode_g->height);
164 u8 depth = GET_GLOBAL(vmode_g->depth);
165 u32 mem = width * height * DIV_ROUND_UP(depth, 8);
167 return width <= max_xres && depth <= max_bpp && mem <= max_mem;
170 struct vgamode_s *bochsvga_find_mode(int mode)
172 struct bochsvga_mode *m = bochsvga_modes;
173 for (; m < &bochsvga_modes[ARRAY_SIZE(bochsvga_modes)]; m++)
174 if (GET_GLOBAL(m->mode) == mode) {
175 if (! mode_valid(&m->info))
179 return stdvga_find_mode(mode);
183 bochsvga_list_modes(u16 seg, u16 *dest, u16 *last)
185 struct bochsvga_mode *m = bochsvga_modes;
186 for (; m < &bochsvga_modes[ARRAY_SIZE(bochsvga_modes)] && dest<last; m++) {
187 if (!mode_valid(&m->info))
190 dprintf(1, "VBE found mode %x valid.\n", GET_GLOBAL(m->mode));
191 SET_FARVAR(seg, *dest, GET_GLOBAL(m->mode));
195 stdvga_list_modes(seg, dest, last);
199 bochsvga_hires_enable(int enable)
203 VBE_DISPI_LFB_ENABLED |
204 VBE_DISPI_NOCLEARMEM : 0;
206 dispi_write(VBE_DISPI_INDEX_ENABLE, flags);
210 bochsvga_get_window(struct vgamode_s *vmode_g, int window)
214 return dispi_read(VBE_DISPI_INDEX_BANK);
218 bochsvga_set_window(struct vgamode_s *vmode_g, int window, int val)
222 dispi_write(VBE_DISPI_INDEX_BANK, val);
223 if (dispi_read(VBE_DISPI_INDEX_BANK) != val)
229 bochsvga_get_linelength(struct vgamode_s *vmode_g)
231 return dispi_read(VBE_DISPI_INDEX_VIRT_WIDTH) * vga_bpp(vmode_g) / 8;
235 bochsvga_set_linelength(struct vgamode_s *vmode_g, int val)
237 stdvga_set_linelength(vmode_g, val);
238 int pixels = (val * 8) / vga_bpp(vmode_g);
239 dispi_write(VBE_DISPI_INDEX_VIRT_WIDTH, pixels);
244 bochsvga_get_displaystart(struct vgamode_s *vmode_g)
246 int bpp = vga_bpp(vmode_g);
247 int linelength = dispi_read(VBE_DISPI_INDEX_VIRT_WIDTH) * bpp / 8;
248 int x = dispi_read(VBE_DISPI_INDEX_X_OFFSET);
249 int y = dispi_read(VBE_DISPI_INDEX_Y_OFFSET);
250 return x * bpp / 8 + linelength * y;
254 bochsvga_set_displaystart(struct vgamode_s *vmode_g, int val)
256 stdvga_set_displaystart(vmode_g, val);
257 int bpp = vga_bpp(vmode_g);
258 int linelength = dispi_read(VBE_DISPI_INDEX_VIRT_WIDTH) * bpp / 8;
259 dispi_write(VBE_DISPI_INDEX_X_OFFSET, (val % linelength) * 8 / bpp);
260 dispi_write(VBE_DISPI_INDEX_Y_OFFSET, val / linelength);
265 bochsvga_clear_scr(void)
269 en = dispi_read(VBE_DISPI_INDEX_ENABLE);
270 en &= ~VBE_DISPI_NOCLEARMEM;
271 dispi_write(VBE_DISPI_INDEX_ENABLE, en);
275 bochsvga_set_mode(struct vgamode_s *vmode_g, int flags)
277 if (! is_bochsvga_mode(vmode_g)) {
278 bochsvga_hires_enable(0);
279 return stdvga_set_mode(vmode_g, flags);
282 bochsvga_hires_enable(1);
284 u8 depth = GET_GLOBAL(vmode_g->depth);
286 stdvga_set_mode(stdvga_find_mode(0x6a), 0);
288 // XXX load_dac_palette(3);
291 dispi_write(VBE_DISPI_INDEX_BPP, depth);
292 u16 width = GET_GLOBAL(vmode_g->width);
293 u16 height = GET_GLOBAL(vmode_g->height);
294 dispi_write(VBE_DISPI_INDEX_XRES, width);
295 dispi_write(VBE_DISPI_INDEX_YRES, height);
296 dispi_write(VBE_DISPI_INDEX_BANK, 0);
298 /* VGA compat setup */
299 //XXX: This probably needs some reverse engineering
300 u16 crtc_addr = VGAREG_VGA_CRTC_ADDRESS;
301 stdvga_crtc_write(crtc_addr, 0x11, 0x00);
302 stdvga_crtc_write(crtc_addr, 0x01, width / 8 - 1);
303 dispi_write(VBE_DISPI_INDEX_VIRT_WIDTH, width);
304 stdvga_crtc_write(crtc_addr, 0x12, height - 1);
306 if ((height - 1) & 0x0100)
308 if ((height - 1) & 0x0200)
310 stdvga_crtc_mask(crtc_addr, 0x07, 0x42, v);
312 stdvga_crtc_write(crtc_addr, 0x09, 0x00);
313 stdvga_crtc_mask(crtc_addr, 0x17, 0x00, 0x03);
314 stdvga_attr_mask(0x10, 0x00, 0x01);
315 stdvga_grdc_write(0x06, 0x05);
316 stdvga_sequ_write(0x02, 0x0f);
318 stdvga_crtc_mask(crtc_addr, 0x14, 0x00, 0x40);
319 stdvga_attr_mask(0x10, 0x00, 0x40);
320 stdvga_sequ_mask(0x04, 0x00, 0x08);
321 stdvga_grdc_mask(0x05, 0x20, 0x40);
324 if (flags & MF_LINEARFB) {
325 /* Linear frame buffer */
328 if (!(flags & MF_NOCLEARMEM)) {
329 bochsvga_clear_scr();