4 #include "usb.h" // struct usb_pipe
8 int uhci_init(struct usb_s *cntl);
9 int uhci_control(u32 endp, int dir, const void *cmd, int cmdsize
10 , void *data, int datasize);
11 struct usb_pipe *uhci_alloc_intr_pipe(u32 endp, int period);
12 int uhci_poll_intr(struct usb_pipe *pipe, void *data);
15 /****************************************************************
16 * uhci structs and flags
17 ****************************************************************/
19 /* USB port status and control registers */
22 #define USBPORTSC_CCS 0x0001 /* Current Connect Status
23 * ("device present") */
24 #define USBPORTSC_CSC 0x0002 /* Connect Status Change */
25 #define USBPORTSC_PE 0x0004 /* Port Enable */
26 #define USBPORTSC_PEC 0x0008 /* Port Enable Change */
27 #define USBPORTSC_DPLUS 0x0010 /* D+ high (line status) */
28 #define USBPORTSC_DMINUS 0x0020 /* D- high (line status) */
29 #define USBPORTSC_RD 0x0040 /* Resume Detect */
30 #define USBPORTSC_RES1 0x0080 /* reserved, always 1 */
31 #define USBPORTSC_LSDA 0x0100 /* Low Speed Device Attached */
32 #define USBPORTSC_PR 0x0200 /* Port Reset */
34 /* Legacy support register */
35 #define USBLEGSUP 0xc0
36 #define USBLEGSUP_RWC 0x8f00 /* the R/WC bits */
38 /* Command register */
40 #define USBCMD_RS 0x0001 /* Run/Stop */
41 #define USBCMD_HCRESET 0x0002 /* Host reset */
42 #define USBCMD_GRESET 0x0004 /* Global reset */
43 #define USBCMD_EGSM 0x0008 /* Global Suspend Mode */
44 #define USBCMD_FGR 0x0010 /* Force Global Resume */
45 #define USBCMD_SWDBG 0x0020 /* SW Debug mode */
46 #define USBCMD_CF 0x0040 /* Config Flag (sw only) */
47 #define USBCMD_MAXP 0x0080 /* Max Packet (0 = 32, 1 = 64) */
51 #define USBSTS_USBINT 0x0001 /* Interrupt due to IOC */
52 #define USBSTS_ERROR 0x0002 /* Interrupt due to error */
53 #define USBSTS_RD 0x0004 /* Resume Detect */
54 #define USBSTS_HSE 0x0008 /* Host System Error: PCI problems */
55 #define USBSTS_HCPE 0x0010 /* Host Controller Process Error:
56 * the schedule is buggy */
57 #define USBSTS_HCH 0x0020 /* HC Halted */
59 /* Interrupt enable register */
61 #define USBINTR_TIMEOUT 0x0001 /* Timeout/CRC error enable */
62 #define USBINTR_RESUME 0x0002 /* Resume interrupt enable */
63 #define USBINTR_IOC 0x0004 /* Interrupt On Complete enable */
64 #define USBINTR_SP 0x0008 /* Short packet interrupt enable */
67 #define USBFLBASEADD 8
69 #define USBSOF_DEFAULT 64 /* Frame length is exactly 1 ms */
71 struct uhci_framelist {
75 #define TD_CTRL_SPD (1 << 29) /* Short Packet Detect */
76 #define TD_CTRL_C_ERR_MASK (3 << 27) /* Error Counter bits */
77 #define TD_CTRL_C_ERR_SHIFT 27
78 #define TD_CTRL_LS (1 << 26) /* Low Speed Device */
79 #define TD_CTRL_IOS (1 << 25) /* Isochronous Select */
80 #define TD_CTRL_IOC (1 << 24) /* Interrupt on Complete */
81 #define TD_CTRL_ACTIVE (1 << 23) /* TD Active */
82 #define TD_CTRL_STALLED (1 << 22) /* TD Stalled */
83 #define TD_CTRL_DBUFERR (1 << 21) /* Data Buffer Error */
84 #define TD_CTRL_BABBLE (1 << 20) /* Babble Detected */
85 #define TD_CTRL_NAK (1 << 19) /* NAK Received */
86 #define TD_CTRL_CRCTIMEO (1 << 18) /* CRC/Time Out Error */
87 #define TD_CTRL_BITSTUFF (1 << 17) /* Bit Stuff Error */
88 #define TD_CTRL_ACTLEN_MASK 0x7FF /* actual length, encoded as n - 1 */
90 #define TD_CTRL_ANY_ERROR (TD_CTRL_STALLED | TD_CTRL_DBUFERR | \
91 TD_CTRL_BABBLE | TD_CTRL_CRCTIME | \
93 #define uhci_maxerr(err) ((err) << TD_CTRL_C_ERR_SHIFT)
95 #define TD_TOKEN_DEVADDR_SHIFT 8
96 #define TD_TOKEN_TOGGLE_SHIFT 19
97 #define TD_TOKEN_TOGGLE (1 << 19)
98 #define TD_TOKEN_EXPLEN_SHIFT 21
99 #define TD_TOKEN_EXPLEN_MASK 0x7FF /* expected length, encoded as n-1 */
100 #define TD_TOKEN_PID_MASK 0xFF
102 #define uhci_explen(len) ((((len) - 1) & TD_TOKEN_EXPLEN_MASK) << \
103 TD_TOKEN_EXPLEN_SHIFT)
105 #define uhci_expected_length(token) ((((token) >> TD_TOKEN_EXPLEN_SHIFT) + \
106 1) & TD_TOKEN_EXPLEN_MASK)
123 struct uhci_td *next_td;
124 struct usb_pipe pipe;
127 #define UHCI_PTR_BITS 0x000F
128 #define UHCI_PTR_TERM 0x0001
129 #define UHCI_PTR_QH 0x0002
130 #define UHCI_PTR_DEPTH 0x0004
131 #define UHCI_PTR_BREADTH 0x0000