1 // Code for handling OHCI USB controllers.
3 // Copyright (C) 2009 Kevin O'Connor <kevin@koconnor.net>
5 // This file may be distributed under the terms of the GNU LGPLv3 license.
7 #include "util.h" // dprintf
8 #include "pci.h" // pci_bdf_to_bus
9 #include "config.h" // CONFIG_*
10 #include "usb-ohci.h" // struct ohci_hcca
11 #include "pci_regs.h" // PCI_BASE_ADDRESS_0
12 #include "usb.h" // struct usb_s
13 #include "farptr.h" // GET_FLATPTR
18 start_ohci(struct usb_s *cntl, struct ohci_hcca *hcca)
20 u32 oldfminterval = readl(&cntl->ohci.regs->fminterval);
21 u32 oldrwc = readl(&cntl->ohci.regs->control) & OHCI_CTRL_RWC;
23 // XXX - check if already running?
26 writel(&cntl->ohci.regs->control, OHCI_USB_RESET | oldrwc);
27 readl(&cntl->ohci.regs->control); // flush writes
28 msleep(USB_TIME_DRSTR);
30 // Do software init (min 10us, max 2ms)
31 u64 end = calc_future_tsc_usec(10);
32 writel(&cntl->ohci.regs->cmdstatus, OHCI_HCR);
34 u32 status = readl(&cntl->ohci.regs->cmdstatus);
35 if (! status & OHCI_HCR)
37 if (check_time(end)) {
44 writel(&cntl->ohci.regs->ed_controlhead, (u32)cntl->ohci.control_ed);
45 writel(&cntl->ohci.regs->ed_bulkhead, 0);
46 writel(&cntl->ohci.regs->hcca, (u32)hcca);
49 u32 fi = oldfminterval & 0x3fff;
50 writel(&cntl->ohci.regs->fminterval
51 , (((oldfminterval & FIT) ^ FIT)
52 | fi | (((6 * (fi - 210)) / 7) << 16)));
53 writel(&cntl->ohci.regs->periodicstart, ((9 * fi) / 10) & 0x3fff);
54 readl(&cntl->ohci.regs->control); // flush writes
56 // XXX - verify that fminterval was setup correctly.
58 // Go into operational state
59 writel(&cntl->ohci.regs->control
60 , (OHCI_CTRL_CBSR | OHCI_CTRL_CLE | OHCI_CTRL_PLE
61 | OHCI_USB_OPER | oldrwc));
62 readl(&cntl->ohci.regs->control); // flush writes
68 stop_ohci(struct usb_s *cntl)
70 u32 oldrwc = readl(&cntl->ohci.regs->control) & OHCI_CTRL_RWC;
71 writel(&cntl->ohci.regs->control, oldrwc);
72 readl(&cntl->ohci.regs->control); // flush writes
75 // Find any devices connected to the root hub.
77 check_ohci_ports(struct usb_s *cntl)
79 // Turn on power for all devices on roothub.
80 u32 rha = readl(&cntl->ohci.regs->roothub_a);
81 rha &= ~(RH_A_PSM | RH_A_OCPM);
82 writel(&cntl->ohci.regs->roothub_status, RH_HS_LPSC);
83 writel(&cntl->ohci.regs->roothub_b, RH_B_PPCM);
84 msleep((rha >> 24) * 2);
86 // Count and reset connected devices
87 int ports = rha & RH_A_NDP;
90 for (i=0; i<ports; i++)
91 if (readl(&cntl->ohci.regs->roothub_portstatus[i]) & RH_PS_CCS) {
92 writel(&cntl->ohci.regs->roothub_portstatus[i], RH_PS_PRS);
96 // No devices connected
99 // XXX - should poll instead of using timer.
100 msleep(USB_TIME_DRSTR + USB_TIME_RSTRCY);
103 for (i=0; i<ports; i++) {
104 u32 sts = readl(&cntl->ohci.regs->roothub_portstatus[i]);
105 if ((sts & (RH_PS_CCS|RH_PS_PES)) == (RH_PS_CCS|RH_PS_PES)) {
106 int count = configure_usb_device(cntl, !!(sts & RH_PS_LSDA));
109 writel(&cntl->ohci.regs->roothub_portstatus[i]
110 , RH_PS_CCS|RH_PS_LSDA);
120 // Turn off power to all ports
121 writel(&cntl->ohci.regs->roothub_status, RH_HS_LPS);
126 ohci_init(void *data)
128 if (! CONFIG_USB_OHCI)
130 struct usb_s *cntl = data;
132 // XXX - don't call pci_config_XXX from a thread
133 cntl->type = USB_TYPE_OHCI;
134 u32 baseaddr = pci_config_readl(cntl->bdf, PCI_BASE_ADDRESS_0);
135 cntl->ohci.regs = (void*)(baseaddr & PCI_BASE_ADDRESS_MEM_MASK);
137 dprintf(3, "OHCI init on dev %02x:%02x.%x (regs=%p)\n"
138 , pci_bdf_to_bus(cntl->bdf), pci_bdf_to_dev(cntl->bdf)
139 , pci_bdf_to_fn(cntl->bdf), cntl->ohci.regs);
141 // Enable bus mastering and memory access.
142 pci_config_maskw(cntl->bdf, PCI_COMMAND
143 , 0, PCI_COMMAND_MASTER|PCI_COMMAND_MEMORY);
145 // XXX - check for and disable SMM control?
147 // Disable interrupts
148 writel(&cntl->ohci.regs->intrdisable, ~0);
149 writel(&cntl->ohci.regs->intrstatus, ~0);
152 struct ohci_hcca *hcca = memalign_high(256, sizeof(*hcca));
153 struct ohci_ed *intr_ed = malloc_high(sizeof(*intr_ed));
154 struct ohci_ed *control_ed = malloc_high(sizeof(*control_ed));
155 if (!hcca || !intr_ed || !control_ed) {
159 memset(hcca, 0, sizeof(*hcca));
160 memset(intr_ed, 0, sizeof(*intr_ed));
161 intr_ed->hwINFO = ED_SKIP;
163 for (i=0; i<ARRAY_SIZE(hcca->int_table); i++)
164 hcca->int_table[i] = (u32)intr_ed;
165 memset(control_ed, 0, sizeof(*control_ed));
166 control_ed->hwINFO = ED_SKIP;
167 cntl->ohci.control_ed = control_ed;
169 int ret = start_ohci(cntl, hcca);
173 int count = check_ohci_ports(cntl);
187 wait_ed(struct ohci_ed *ed)
189 // XXX - 500ms just a guess
190 u64 end = calc_future_tsc(500);
192 if (ed->hwHeadP == ed->hwTailP)
194 if (check_time(end)) {
203 ohci_control(u32 endp, int dir, const void *cmd, int cmdsize
204 , void *data, int datasize)
206 if (! CONFIG_USB_OHCI)
209 dprintf(5, "ohci_control %x\n", endp);
210 struct usb_s *cntl = endp2cntl(endp);
211 int maxpacket = endp2maxsize(endp);
212 int lowspeed = endp2speed(endp);
213 int devaddr = endp2devaddr(endp) | (endp2ep(endp) << 7);
215 // Setup transfer descriptors
216 struct ohci_td *tds = malloc_tmphigh(sizeof(*tds) * 3);
217 tds[0].hwINFO = TD_DP_SETUP | TD_T_DATA0 | TD_CC;
218 tds[0].hwCBP = (u32)cmd;
219 tds[0].hwNextTD = (u32)&tds[1];
220 tds[0].hwBE = (u32)cmd + cmdsize - 1;
221 tds[1].hwINFO = (dir ? TD_DP_IN : TD_DP_OUT) | TD_T_DATA1 | TD_CC;
222 tds[1].hwCBP = datasize ? (u32)data : 0;
223 tds[1].hwNextTD = (u32)&tds[2];
224 tds[1].hwBE = (u32)data + datasize - 1;
225 tds[2].hwINFO = (dir ? TD_DP_OUT : TD_DP_IN) | TD_T_DATA1 | TD_CC;
227 tds[2].hwNextTD = (u32)&tds[3];
231 struct ohci_ed *ed = cntl->ohci.control_ed;
232 ed->hwINFO = ED_SKIP;
234 ed->hwHeadP = (u32)&tds[0];
235 ed->hwTailP = (u32)&tds[3];
237 ed->hwINFO = devaddr | (maxpacket << 16) | (lowspeed ? ED_LOWSPEED : 0);
238 writel(&cntl->ohci.regs->cmdstatus, OHCI_CLF);
240 int ret = wait_ed(ed);
241 ed->hwINFO = ED_SKIP;
243 usleep(1); // XXX - in case controller still accessing tds
250 struct usb_pipe pipe;
257 ohci_alloc_intr_pipe(u32 endp, int frameexp)
259 if (! CONFIG_USB_OHCI)
262 dprintf(7, "ohci_alloc_intr_pipe %x %d\n", endp, frameexp);
265 struct usb_s *cntl = endp2cntl(endp);
266 int maxpacket = endp2maxsize(endp);
267 int lowspeed = endp2speed(endp);
268 int devaddr = endp2devaddr(endp) | (endp2ep(endp) << 7);
269 // Determine number of entries needed for 2 timer ticks.
270 int ms = 1<<frameexp;
271 int count = DIV_ROUND_UP(PIT_TICK_INTERVAL * 1000 * 2, PIT_TICK_RATE * ms);
272 struct ohci_pipe *pipe = malloc_low(sizeof(*pipe));
273 struct ohci_td *tds = malloc_low(sizeof(*tds) * count);
274 void *data = malloc_low(maxpacket * count);
275 if (!pipe || !tds || !data)
278 struct ohci_ed *ed = &pipe->ed;
279 ed->hwHeadP = (u32)&tds[0];
280 ed->hwTailP = (u32)&tds[count-1];
281 ed->hwINFO = devaddr | (maxpacket << 16) | (lowspeed ? ED_LOWSPEED : 0);
284 for (i=0; i<count-1; i++) {
285 tds[i].hwINFO = TD_DP_IN | TD_T_TOGGLE | TD_CC;
286 tds[i].hwCBP = (u32)data + maxpacket * i;
287 tds[i].hwNextTD = (u32)&tds[i+1];
288 tds[i].hwBE = tds[i].hwCBP + maxpacket - 1;
291 // Add to interrupt schedule.
293 struct ohci_hcca *hcca = (void*)cntl->ohci.regs->hcca;
295 // Add to existing interrupt entry.
296 struct ohci_ed *intr_ed = (void*)hcca->int_table[0];
297 ed->hwNextED = intr_ed->hwNextED;
298 intr_ed->hwNextED = (u32)ed;
300 int startpos = 1<<(frameexp-1);
301 ed->hwNextED = hcca->int_table[startpos];
302 for (i=startpos; i<ARRAY_SIZE(hcca->int_table); i+=ms)
303 hcca->int_table[i] = (u32)ed;
309 pipe->pipe.endp = endp;
320 ohci_poll_intr(struct usb_pipe *pipe, void *data)
323 if (! CONFIG_USB_OHCI)
326 struct ohci_pipe *p = container_of(pipe, struct ohci_pipe, pipe);
327 struct ohci_td *tds = GET_FLATPTR(p->tds);
328 struct ohci_td *head = (void*)GET_FLATPTR(p->ed.hwHeadP);
329 struct ohci_td *tail = (void*)GET_FLATPTR(p->ed.hwTailP);
330 int count = GET_FLATPTR(p->count);
331 int pos = (tail - tds + 1) % count;
332 struct ohci_td *next = &tds[pos];
336 // XXX - check for errors.
339 u32 endp = GET_FLATPTR(p->pipe.endp);
340 int maxpacket = endp2maxsize(endp);
341 void *pipedata = GET_FLATPTR(p->data);
342 void *intrdata = pipedata + maxpacket * pos;
343 memcpy_far(GET_SEG(SS), data
344 , FLATPTR_TO_SEG(intrdata), (void*)FLATPTR_TO_OFFSET(intrdata)
348 SET_FLATPTR(tail->hwINFO, TD_DP_IN | TD_T_TOGGLE | TD_CC);
349 intrdata = pipedata + maxpacket * (tail-tds);
350 SET_FLATPTR(tail->hwCBP, (u32)intrdata);
351 SET_FLATPTR(tail->hwNextTD, (u32)next);
352 SET_FLATPTR(tail->hwBE, (u32)intrdata + maxpacket - 1);
354 SET_FLATPTR(p->ed.hwTailP, (u32)next);