1 // Code for handling OHCI USB controllers.
3 // Copyright (C) 2009 Kevin O'Connor <kevin@koconnor.net>
5 // This file may be distributed under the terms of the GNU LGPLv3 license.
7 #include "util.h" // dprintf
8 #include "pci.h" // pci_bdf_to_bus
9 #include "config.h" // CONFIG_*
10 #include "usb-ohci.h" // struct ohci_hcca
11 #include "pci_regs.h" // PCI_BASE_ADDRESS_0
12 #include "usb.h" // struct usb_s
13 #include "farptr.h" // GET_FLATPTR
14 #include "usb-hub.h" // struct usbhub_s
19 /****************************************************************
21 ****************************************************************/
24 init_ohci_port(void *data)
26 struct usbhub_s *hub = data;
27 u32 port = hub->port; // XXX - find better way to pass port
29 u32 sts = readl(&hub->cntl->ohci.regs->roothub_portstatus[port]);
30 if (!(sts & RH_PS_CCS))
34 // XXX - need to wait for USB_TIME_ATTDB if just powered up?
37 mutex_lock(&hub->cntl->resetlock);
38 writel(&hub->cntl->ohci.regs->roothub_portstatus[port], RH_PS_PRS);
39 u64 end = calc_future_tsc(USB_TIME_DRSTR * 2);
41 sts = readl(&hub->cntl->ohci.regs->roothub_portstatus[port]);
42 if (!(sts & RH_PS_PRS))
43 // XXX - need to ensure USB_TIME_DRSTR time in reset?
45 if (check_time(end)) {
53 if ((sts & (RH_PS_CCS|RH_PS_PES)) != (RH_PS_CCS|RH_PS_PES))
54 // Device no longer present
57 // Set address of port
58 struct usb_pipe *pipe = usb_set_address(hub->cntl, !!(sts & RH_PS_LSDA));
61 mutex_unlock(&hub->cntl->resetlock);
63 // Configure the device
64 int count = configure_usb_device(pipe);
68 writel(&hub->cntl->ohci.regs->roothub_portstatus[port]
69 , RH_PS_CCS|RH_PS_LSDA);
70 hub->devcount += count;
77 writel(&hub->cntl->ohci.regs->roothub_portstatus[port]
78 , RH_PS_CCS|RH_PS_LSDA);
79 mutex_unlock(&hub->cntl->resetlock);
83 // Find any devices connected to the root hub.
85 check_ohci_ports(struct usb_s *cntl)
88 // Turn on power for all devices on roothub.
89 u32 rha = readl(&cntl->ohci.regs->roothub_a);
90 rha &= ~(RH_A_PSM | RH_A_OCPM);
91 writel(&cntl->ohci.regs->roothub_status, RH_HS_LPSC);
92 writel(&cntl->ohci.regs->roothub_b, RH_B_PPCM);
93 msleep((rha >> 24) * 2);
94 // XXX - need to sleep for USB_TIME_SIGATT if just powered up?
96 // Lanuch a thread per port.
98 memset(&hub, 0, sizeof(hub));
100 int ports = rha & RH_A_NDP;
103 for (i=0; i<ports; i++) {
105 run_thread(init_ohci_port, &hub);
108 // Wait for threads to complete.
116 /****************************************************************
118 ****************************************************************/
121 start_ohci(struct usb_s *cntl, struct ohci_hcca *hcca)
123 u32 oldfminterval = readl(&cntl->ohci.regs->fminterval);
124 u32 oldrwc = readl(&cntl->ohci.regs->control) & OHCI_CTRL_RWC;
126 // XXX - check if already running?
129 writel(&cntl->ohci.regs->control, OHCI_USB_RESET | oldrwc);
130 readl(&cntl->ohci.regs->control); // flush writes
131 msleep(USB_TIME_DRSTR);
133 // Do software init (min 10us, max 2ms)
134 u64 end = calc_future_tsc_usec(10);
135 writel(&cntl->ohci.regs->cmdstatus, OHCI_HCR);
137 u32 status = readl(&cntl->ohci.regs->cmdstatus);
138 if (! status & OHCI_HCR)
140 if (check_time(end)) {
147 writel(&cntl->ohci.regs->ed_controlhead, 0);
148 writel(&cntl->ohci.regs->ed_bulkhead, 0);
149 writel(&cntl->ohci.regs->hcca, (u32)hcca);
152 u32 fi = oldfminterval & 0x3fff;
153 writel(&cntl->ohci.regs->fminterval
154 , (((oldfminterval & FIT) ^ FIT)
155 | fi | (((6 * (fi - 210)) / 7) << 16)));
156 writel(&cntl->ohci.regs->periodicstart, ((9 * fi) / 10) & 0x3fff);
157 readl(&cntl->ohci.regs->control); // flush writes
159 // XXX - verify that fminterval was setup correctly.
161 // Go into operational state
162 writel(&cntl->ohci.regs->control
163 , (OHCI_CTRL_CBSR | OHCI_CTRL_CLE | OHCI_CTRL_PLE
164 | OHCI_USB_OPER | oldrwc));
165 readl(&cntl->ohci.regs->control); // flush writes
171 stop_ohci(struct usb_s *cntl)
173 u32 oldrwc = readl(&cntl->ohci.regs->control) & OHCI_CTRL_RWC;
174 writel(&cntl->ohci.regs->control, oldrwc);
175 readl(&cntl->ohci.regs->control); // flush writes
179 ohci_init(void *data)
181 if (! CONFIG_USB_OHCI)
183 struct usb_s *cntl = data;
185 // XXX - don't call pci_config_XXX from a thread
186 cntl->type = USB_TYPE_OHCI;
187 u32 baseaddr = pci_config_readl(cntl->bdf, PCI_BASE_ADDRESS_0);
188 cntl->ohci.regs = (void*)(baseaddr & PCI_BASE_ADDRESS_MEM_MASK);
190 dprintf(3, "OHCI init on dev %02x:%02x.%x (regs=%p)\n"
191 , pci_bdf_to_bus(cntl->bdf), pci_bdf_to_dev(cntl->bdf)
192 , pci_bdf_to_fn(cntl->bdf), cntl->ohci.regs);
194 // Enable bus mastering and memory access.
195 pci_config_maskw(cntl->bdf, PCI_COMMAND
196 , 0, PCI_COMMAND_MASTER|PCI_COMMAND_MEMORY);
198 // XXX - check for and disable SMM control?
200 // Disable interrupts
201 writel(&cntl->ohci.regs->intrdisable, ~0);
202 writel(&cntl->ohci.regs->intrstatus, ~0);
205 struct ohci_hcca *hcca = memalign_high(256, sizeof(*hcca));
206 struct ohci_ed *intr_ed = malloc_high(sizeof(*intr_ed));
207 if (!hcca || !intr_ed) {
211 memset(hcca, 0, sizeof(*hcca));
212 memset(intr_ed, 0, sizeof(*intr_ed));
213 intr_ed->hwINFO = ED_SKIP;
215 for (i=0; i<ARRAY_SIZE(hcca->int_table); i++)
216 hcca->int_table[i] = (u32)intr_ed;
218 int ret = start_ohci(cntl, hcca);
222 int count = check_ohci_ports(cntl);
223 free_pipe(cntl->defaultpipe);
236 /****************************************************************
237 * End point communication
238 ****************************************************************/
241 wait_ed(struct ohci_ed *ed)
243 // XXX - 500ms just a guess
244 u64 end = calc_future_tsc(500);
246 if (ed->hwHeadP == ed->hwTailP)
248 if (check_time(end)) {
256 // Wait for next USB frame to start - for ensuring safe memory release.
258 ohci_waittick(struct usb_s *cntl)
261 struct ohci_hcca *hcca = (void*)cntl->ohci.regs->hcca;
262 u32 startframe = hcca->frame_no;
263 u64 end = calc_future_tsc(1000 * 5);
265 if (hcca->frame_no != startframe)
267 if (check_time(end)) {
276 signal_freelist(struct usb_s *cntl)
278 u32 v = readl(&cntl->ohci.regs->control);
279 if (v & OHCI_CTRL_CLE) {
280 writel(&cntl->ohci.regs->control, v & ~(OHCI_CTRL_CLE|OHCI_CTRL_BLE));
282 writel(&cntl->ohci.regs->ed_controlcurrent, 0);
283 writel(&cntl->ohci.regs->ed_bulkcurrent, 0);
284 writel(&cntl->ohci.regs->control, v);
292 struct usb_pipe pipe;
299 ohci_free_pipe(struct usb_pipe *p)
301 if (! CONFIG_USB_OHCI)
303 struct ohci_pipe *pipe = container_of(p, struct ohci_pipe, pipe);
304 u32 endp = pipe->pipe.endp;
305 dprintf(7, "ohci_free_pipe %x\n", endp);
306 struct usb_s *cntl = endp2cntl(endp);
308 u32 *pos = &cntl->ohci.regs->ed_controlhead;
310 struct ohci_ed *next = (void*)*pos;
312 // Not found?! Exit without freeing.
313 warn_internalerror();
316 if (next == &pipe->ed) {
317 *pos = next->hwNextED;
318 signal_freelist(cntl);
322 pos = &next->hwNextED;
327 ohci_alloc_control_pipe(u32 endp)
329 if (! CONFIG_USB_OHCI)
331 struct usb_s *cntl = endp2cntl(endp);
332 dprintf(7, "ohci_alloc_control_pipe %x\n", endp);
334 // Allocate a queue head.
335 struct ohci_pipe *pipe = malloc_tmphigh(sizeof(*pipe));
340 memset(pipe, 0, sizeof(*pipe));
341 pipe->ed.hwINFO = ED_SKIP;
342 pipe->pipe.endp = endp;
344 // Add queue head to controller list.
345 pipe->ed.hwNextED = cntl->ohci.regs->ed_controlhead;
347 cntl->ohci.regs->ed_controlhead = (u32)&pipe->ed;
352 ohci_control(struct usb_pipe *p, int dir, const void *cmd, int cmdsize
353 , void *data, int datasize)
355 if (! CONFIG_USB_OHCI)
357 if (datasize > 4096) {
358 // XXX - should support larger sizes.
362 struct ohci_pipe *pipe = container_of(p, struct ohci_pipe, pipe);
363 u32 endp = pipe->pipe.endp;
364 dprintf(5, "ohci_control %x\n", endp);
365 struct usb_s *cntl = endp2cntl(endp);
366 int maxpacket = endp2maxsize(endp);
367 int lowspeed = endp2speed(endp);
368 int devaddr = endp2devaddr(endp) | (endp2ep(endp) << 7);
370 // Setup transfer descriptors
371 struct ohci_td *tds = malloc_tmphigh(sizeof(*tds) * 3);
372 tds[0].hwINFO = TD_DP_SETUP | TD_T_DATA0 | TD_CC;
373 tds[0].hwCBP = (u32)cmd;
374 tds[0].hwNextTD = (u32)&tds[1];
375 tds[0].hwBE = (u32)cmd + cmdsize - 1;
376 tds[1].hwINFO = (dir ? TD_DP_IN : TD_DP_OUT) | TD_T_DATA1 | TD_CC;
377 tds[1].hwCBP = datasize ? (u32)data : 0;
378 tds[1].hwNextTD = (u32)&tds[2];
379 tds[1].hwBE = (u32)data + datasize - 1;
380 tds[2].hwINFO = (dir ? TD_DP_OUT : TD_DP_IN) | TD_T_DATA1 | TD_CC;
382 tds[2].hwNextTD = (u32)&tds[3];
386 pipe->ed.hwINFO = ED_SKIP;
388 pipe->ed.hwHeadP = (u32)&tds[0];
389 pipe->ed.hwTailP = (u32)&tds[3];
391 pipe->ed.hwINFO = devaddr | (maxpacket << 16) | (lowspeed ? ED_LOWSPEED : 0);
392 writel(&cntl->ohci.regs->cmdstatus, OHCI_CLF);
394 int ret = wait_ed(&pipe->ed);
395 pipe->ed.hwINFO = ED_SKIP;
403 ohci_alloc_intr_pipe(u32 endp, int frameexp)
405 if (! CONFIG_USB_OHCI)
408 dprintf(7, "ohci_alloc_intr_pipe %x %d\n", endp, frameexp);
411 struct usb_s *cntl = endp2cntl(endp);
412 int maxpacket = endp2maxsize(endp);
413 int lowspeed = endp2speed(endp);
414 int devaddr = endp2devaddr(endp) | (endp2ep(endp) << 7);
415 // Determine number of entries needed for 2 timer ticks.
416 int ms = 1<<frameexp;
417 int count = DIV_ROUND_UP(PIT_TICK_INTERVAL * 1000 * 2, PIT_TICK_RATE * ms);
418 struct ohci_pipe *pipe = malloc_low(sizeof(*pipe));
419 struct ohci_td *tds = malloc_low(sizeof(*tds) * count);
420 void *data = malloc_low(maxpacket * count);
421 if (!pipe || !tds || !data)
424 struct ohci_ed *ed = &pipe->ed;
425 ed->hwHeadP = (u32)&tds[0];
426 ed->hwTailP = (u32)&tds[count-1];
427 ed->hwINFO = devaddr | (maxpacket << 16) | (lowspeed ? ED_LOWSPEED : 0);
430 for (i=0; i<count-1; i++) {
431 tds[i].hwINFO = TD_DP_IN | TD_T_TOGGLE | TD_CC;
432 tds[i].hwCBP = (u32)data + maxpacket * i;
433 tds[i].hwNextTD = (u32)&tds[i+1];
434 tds[i].hwBE = tds[i].hwCBP + maxpacket - 1;
437 // Add to interrupt schedule.
439 struct ohci_hcca *hcca = (void*)cntl->ohci.regs->hcca;
441 // Add to existing interrupt entry.
442 struct ohci_ed *intr_ed = (void*)hcca->int_table[0];
443 ed->hwNextED = intr_ed->hwNextED;
444 intr_ed->hwNextED = (u32)ed;
446 int startpos = 1<<(frameexp-1);
447 ed->hwNextED = hcca->int_table[startpos];
448 for (i=startpos; i<ARRAY_SIZE(hcca->int_table); i+=ms)
449 hcca->int_table[i] = (u32)ed;
455 pipe->pipe.endp = endp;
466 ohci_poll_intr(struct usb_pipe *p, void *data)
469 if (! CONFIG_USB_OHCI)
472 struct ohci_pipe *pipe = container_of(p, struct ohci_pipe, pipe);
473 struct ohci_td *tds = GET_FLATPTR(pipe->tds);
474 struct ohci_td *head = (void*)GET_FLATPTR(pipe->ed.hwHeadP);
475 struct ohci_td *tail = (void*)GET_FLATPTR(pipe->ed.hwTailP);
476 int count = GET_FLATPTR(pipe->count);
477 int pos = (tail - tds + 1) % count;
478 struct ohci_td *next = &tds[pos];
482 // XXX - check for errors.
485 u32 endp = GET_FLATPTR(pipe->pipe.endp);
486 int maxpacket = endp2maxsize(endp);
487 void *pipedata = GET_FLATPTR(pipe->data);
488 void *intrdata = pipedata + maxpacket * pos;
489 memcpy_far(GET_SEG(SS), data
490 , FLATPTR_TO_SEG(intrdata), (void*)FLATPTR_TO_OFFSET(intrdata)
494 SET_FLATPTR(tail->hwINFO, TD_DP_IN | TD_T_TOGGLE | TD_CC);
495 intrdata = pipedata + maxpacket * (tail-tds);
496 SET_FLATPTR(tail->hwCBP, (u32)intrdata);
497 SET_FLATPTR(tail->hwNextTD, (u32)next);
498 SET_FLATPTR(tail->hwBE, (u32)intrdata + maxpacket - 1);
500 SET_FLATPTR(pipe->ed.hwTailP, (u32)next);