1 // Code for handling OHCI USB controllers.
3 // Copyright (C) 2009 Kevin O'Connor <kevin@koconnor.net>
5 // This file may be distributed under the terms of the GNU LGPLv3 license.
7 #include "util.h" // dprintf
8 #include "pci.h" // pci_bdf_to_bus
9 #include "config.h" // CONFIG_*
10 #include "usb-ohci.h" // struct ohci_hcca
11 #include "pci_regs.h" // PCI_BASE_ADDRESS_0
12 #include "usb.h" // struct usb_s
13 #include "farptr.h" // GET_FLATPTR
18 start_ohci(struct usb_s *cntl, struct ohci_hcca *hcca)
20 u32 oldfminterval = readl(&cntl->ohci.regs->fminterval);
21 u32 oldrwc = readl(&cntl->ohci.regs->control) & OHCI_CTRL_RWC;
23 // XXX - check if already running?
26 writel(&cntl->ohci.regs->control, OHCI_USB_RESET | oldrwc);
27 readl(&cntl->ohci.regs->control); // flush writes
28 msleep(USB_TIME_DRSTR);
30 // Do software init (min 10us, max 2ms)
31 u64 end = calc_future_tsc_usec(10);
32 writel(&cntl->ohci.regs->cmdstatus, OHCI_HCR);
34 u32 status = readl(&cntl->ohci.regs->cmdstatus);
35 if (! status & OHCI_HCR)
37 if (check_time(end)) {
44 writel(&cntl->ohci.regs->ed_controlhead, (u32)cntl->ohci.control_ed);
45 writel(&cntl->ohci.regs->ed_bulkhead, 0);
46 writel(&cntl->ohci.regs->hcca, (u32)hcca);
49 u32 fi = oldfminterval & 0x3fff;
50 writel(&cntl->ohci.regs->fminterval
51 , (((oldfminterval & FIT) ^ FIT)
52 | fi | (((6 * (fi - 210)) / 7) << 16)));
53 writel(&cntl->ohci.regs->periodicstart, ((9 * fi) / 10) & 0x3fff);
54 readl(&cntl->ohci.regs->control); // flush writes
56 // XXX - verify that fminterval was setup correctly.
58 // Go into operational state
59 writel(&cntl->ohci.regs->control
60 , (OHCI_CTRL_CBSR | OHCI_CTRL_CLE | OHCI_CTRL_PLE
61 | OHCI_USB_OPER | oldrwc));
62 readl(&cntl->ohci.regs->control); // flush writes
68 stop_ohci(struct usb_s *cntl)
70 u32 oldrwc = readl(&cntl->ohci.regs->control) & OHCI_CTRL_RWC;
71 writel(&cntl->ohci.regs->control, oldrwc);
72 readl(&cntl->ohci.regs->control); // flush writes
75 // Find any devices connected to the root hub.
77 check_ohci_ports(struct usb_s *cntl)
79 // Turn on power for all devices on roothub.
80 u32 rha = readl(&cntl->ohci.regs->roothub_a);
81 rha &= ~(RH_A_PSM | RH_A_OCPM);
82 writel(&cntl->ohci.regs->roothub_status, RH_HS_LPSC);
83 writel(&cntl->ohci.regs->roothub_b, RH_B_PPCM);
84 msleep((rha >> 24) * 2);
85 // XXX - need to sleep for USB_TIME_SIGATT if just powered up?
87 // Count and reset connected devices
88 int ports = rha & RH_A_NDP;
91 for (i=0; i<ports; i++) {
92 u32 sts = readl(&cntl->ohci.regs->roothub_portstatus[i]);
93 if (!(sts & RH_PS_CCS))
95 // XXX - need to wait for USB_TIME_ATTDB if just powered up?
96 writel(&cntl->ohci.regs->roothub_portstatus[i], RH_PS_PRS);
97 u64 end = calc_future_tsc(USB_TIME_DRSTR * 2);
99 sts = readl(&cntl->ohci.regs->roothub_portstatus[i]);
100 if (!(sts & RH_PS_PRS))
101 // XXX - need to ensure USB_TIME_DRSTR time in reset?
103 if (check_time(end)) {
111 if ((sts & (RH_PS_CCS|RH_PS_PES)) != (RH_PS_CCS|RH_PS_PES))
112 // Device no longer present
115 msleep(USB_TIME_RSTRCY);
117 // XXX - should try to parallelize configuration.
118 int count = configure_usb_device(cntl, !!(sts & RH_PS_LSDA));
121 writel(&cntl->ohci.regs->roothub_portstatus[i]
122 , RH_PS_CCS|RH_PS_LSDA);
126 // No devices connected
131 // Turn off power to all ports
132 writel(&cntl->ohci.regs->roothub_status, RH_HS_LPS);
137 ohci_init(void *data)
139 if (! CONFIG_USB_OHCI)
141 struct usb_s *cntl = data;
143 // XXX - don't call pci_config_XXX from a thread
144 cntl->type = USB_TYPE_OHCI;
145 u32 baseaddr = pci_config_readl(cntl->bdf, PCI_BASE_ADDRESS_0);
146 cntl->ohci.regs = (void*)(baseaddr & PCI_BASE_ADDRESS_MEM_MASK);
148 dprintf(3, "OHCI init on dev %02x:%02x.%x (regs=%p)\n"
149 , pci_bdf_to_bus(cntl->bdf), pci_bdf_to_dev(cntl->bdf)
150 , pci_bdf_to_fn(cntl->bdf), cntl->ohci.regs);
152 // Enable bus mastering and memory access.
153 pci_config_maskw(cntl->bdf, PCI_COMMAND
154 , 0, PCI_COMMAND_MASTER|PCI_COMMAND_MEMORY);
156 // XXX - check for and disable SMM control?
158 // Disable interrupts
159 writel(&cntl->ohci.regs->intrdisable, ~0);
160 writel(&cntl->ohci.regs->intrstatus, ~0);
163 struct ohci_hcca *hcca = memalign_high(256, sizeof(*hcca));
164 struct ohci_ed *intr_ed = malloc_high(sizeof(*intr_ed));
165 struct ohci_ed *control_ed = malloc_high(sizeof(*control_ed));
166 if (!hcca || !intr_ed || !control_ed) {
170 memset(hcca, 0, sizeof(*hcca));
171 memset(intr_ed, 0, sizeof(*intr_ed));
172 intr_ed->hwINFO = ED_SKIP;
174 for (i=0; i<ARRAY_SIZE(hcca->int_table); i++)
175 hcca->int_table[i] = (u32)intr_ed;
176 memset(control_ed, 0, sizeof(*control_ed));
177 control_ed->hwINFO = ED_SKIP;
178 cntl->ohci.control_ed = control_ed;
180 int ret = start_ohci(cntl, hcca);
184 int count = check_ohci_ports(cntl);
198 wait_ed(struct ohci_ed *ed)
200 // XXX - 500ms just a guess
201 u64 end = calc_future_tsc(500);
203 if (ed->hwHeadP == ed->hwTailP)
205 if (check_time(end)) {
214 ohci_control(u32 endp, int dir, const void *cmd, int cmdsize
215 , void *data, int datasize)
217 if (! CONFIG_USB_OHCI)
220 dprintf(5, "ohci_control %x\n", endp);
221 struct usb_s *cntl = endp2cntl(endp);
222 int maxpacket = endp2maxsize(endp);
223 int lowspeed = endp2speed(endp);
224 int devaddr = endp2devaddr(endp) | (endp2ep(endp) << 7);
226 // Setup transfer descriptors
227 struct ohci_td *tds = malloc_tmphigh(sizeof(*tds) * 3);
228 tds[0].hwINFO = TD_DP_SETUP | TD_T_DATA0 | TD_CC;
229 tds[0].hwCBP = (u32)cmd;
230 tds[0].hwNextTD = (u32)&tds[1];
231 tds[0].hwBE = (u32)cmd + cmdsize - 1;
232 tds[1].hwINFO = (dir ? TD_DP_IN : TD_DP_OUT) | TD_T_DATA1 | TD_CC;
233 tds[1].hwCBP = datasize ? (u32)data : 0;
234 tds[1].hwNextTD = (u32)&tds[2];
235 tds[1].hwBE = (u32)data + datasize - 1;
236 tds[2].hwINFO = (dir ? TD_DP_OUT : TD_DP_IN) | TD_T_DATA1 | TD_CC;
238 tds[2].hwNextTD = (u32)&tds[3];
242 struct ohci_ed *ed = cntl->ohci.control_ed;
243 ed->hwINFO = ED_SKIP;
245 ed->hwHeadP = (u32)&tds[0];
246 ed->hwTailP = (u32)&tds[3];
248 ed->hwINFO = devaddr | (maxpacket << 16) | (lowspeed ? ED_LOWSPEED : 0);
249 writel(&cntl->ohci.regs->cmdstatus, OHCI_CLF);
251 int ret = wait_ed(ed);
252 ed->hwINFO = ED_SKIP;
254 usleep(1); // XXX - in case controller still accessing tds
261 struct usb_pipe pipe;
268 ohci_alloc_intr_pipe(u32 endp, int frameexp)
270 if (! CONFIG_USB_OHCI)
273 dprintf(7, "ohci_alloc_intr_pipe %x %d\n", endp, frameexp);
276 struct usb_s *cntl = endp2cntl(endp);
277 int maxpacket = endp2maxsize(endp);
278 int lowspeed = endp2speed(endp);
279 int devaddr = endp2devaddr(endp) | (endp2ep(endp) << 7);
280 // Determine number of entries needed for 2 timer ticks.
281 int ms = 1<<frameexp;
282 int count = DIV_ROUND_UP(PIT_TICK_INTERVAL * 1000 * 2, PIT_TICK_RATE * ms);
283 struct ohci_pipe *pipe = malloc_low(sizeof(*pipe));
284 struct ohci_td *tds = malloc_low(sizeof(*tds) * count);
285 void *data = malloc_low(maxpacket * count);
286 if (!pipe || !tds || !data)
289 struct ohci_ed *ed = &pipe->ed;
290 ed->hwHeadP = (u32)&tds[0];
291 ed->hwTailP = (u32)&tds[count-1];
292 ed->hwINFO = devaddr | (maxpacket << 16) | (lowspeed ? ED_LOWSPEED : 0);
295 for (i=0; i<count-1; i++) {
296 tds[i].hwINFO = TD_DP_IN | TD_T_TOGGLE | TD_CC;
297 tds[i].hwCBP = (u32)data + maxpacket * i;
298 tds[i].hwNextTD = (u32)&tds[i+1];
299 tds[i].hwBE = tds[i].hwCBP + maxpacket - 1;
302 // Add to interrupt schedule.
304 struct ohci_hcca *hcca = (void*)cntl->ohci.regs->hcca;
306 // Add to existing interrupt entry.
307 struct ohci_ed *intr_ed = (void*)hcca->int_table[0];
308 ed->hwNextED = intr_ed->hwNextED;
309 intr_ed->hwNextED = (u32)ed;
311 int startpos = 1<<(frameexp-1);
312 ed->hwNextED = hcca->int_table[startpos];
313 for (i=startpos; i<ARRAY_SIZE(hcca->int_table); i+=ms)
314 hcca->int_table[i] = (u32)ed;
320 pipe->pipe.endp = endp;
331 ohci_poll_intr(struct usb_pipe *pipe, void *data)
334 if (! CONFIG_USB_OHCI)
337 struct ohci_pipe *p = container_of(pipe, struct ohci_pipe, pipe);
338 struct ohci_td *tds = GET_FLATPTR(p->tds);
339 struct ohci_td *head = (void*)GET_FLATPTR(p->ed.hwHeadP);
340 struct ohci_td *tail = (void*)GET_FLATPTR(p->ed.hwTailP);
341 int count = GET_FLATPTR(p->count);
342 int pos = (tail - tds + 1) % count;
343 struct ohci_td *next = &tds[pos];
347 // XXX - check for errors.
350 u32 endp = GET_FLATPTR(p->pipe.endp);
351 int maxpacket = endp2maxsize(endp);
352 void *pipedata = GET_FLATPTR(p->data);
353 void *intrdata = pipedata + maxpacket * pos;
354 memcpy_far(GET_SEG(SS), data
355 , FLATPTR_TO_SEG(intrdata), (void*)FLATPTR_TO_OFFSET(intrdata)
359 SET_FLATPTR(tail->hwINFO, TD_DP_IN | TD_T_TOGGLE | TD_CC);
360 intrdata = pipedata + maxpacket * (tail-tds);
361 SET_FLATPTR(tail->hwCBP, (u32)intrdata);
362 SET_FLATPTR(tail->hwNextTD, (u32)next);
363 SET_FLATPTR(tail->hwBE, (u32)intrdata + maxpacket - 1);
365 SET_FLATPTR(p->ed.hwTailP, (u32)next);