1 // Code for handling OHCI USB controllers.
3 // Copyright (C) 2009 Kevin O'Connor <kevin@koconnor.net>
5 // This file may be distributed under the terms of the GNU LGPLv3 license.
7 #include "util.h" // dprintf
8 #include "pci.h" // pci_bdf_to_bus
9 #include "config.h" // CONFIG_*
10 #include "usb-ohci.h" // struct ohci_hcca
11 #include "pci_regs.h" // PCI_BASE_ADDRESS_0
12 #include "usb.h" // struct usb_s
13 #include "farptr.h" // GET_FLATPTR
14 #include "usb-hub.h" // struct usbhub_s
20 struct ohci_regs *regs;
24 /****************************************************************
26 ****************************************************************/
29 init_ohci_port(void *data)
31 struct usbhub_s *hub = data;
32 u32 port = hub->port; // XXX - find better way to pass port
33 struct usb_ohci_s *cntl = container_of(hub->cntl, struct usb_ohci_s, usb);
35 u32 sts = readl(&cntl->regs->roothub_portstatus[port]);
36 if (!(sts & RH_PS_CCS))
40 // XXX - need to wait for USB_TIME_ATTDB if just powered up?
43 mutex_lock(&cntl->usb.resetlock);
44 writel(&cntl->regs->roothub_portstatus[port], RH_PS_PRS);
45 u64 end = calc_future_tsc(USB_TIME_DRSTR * 2);
47 sts = readl(&cntl->regs->roothub_portstatus[port]);
48 if (!(sts & RH_PS_PRS))
49 // XXX - need to ensure USB_TIME_DRSTR time in reset?
51 if (check_time(end)) {
59 if ((sts & (RH_PS_CCS|RH_PS_PES)) != (RH_PS_CCS|RH_PS_PES))
60 // Device no longer present
63 // Set address of port
64 struct usb_pipe *pipe = usb_set_address(&cntl->usb, !!(sts & RH_PS_LSDA));
67 mutex_unlock(&cntl->usb.resetlock);
69 // Configure the device
70 int count = configure_usb_device(pipe);
74 writel(&cntl->regs->roothub_portstatus[port], RH_PS_CCS|RH_PS_LSDA);
75 hub->devcount += count;
82 writel(&cntl->regs->roothub_portstatus[port], RH_PS_CCS|RH_PS_LSDA);
83 mutex_unlock(&cntl->usb.resetlock);
87 // Find any devices connected to the root hub.
89 check_ohci_ports(struct usb_ohci_s *cntl)
92 // Turn on power for all devices on roothub.
93 u32 rha = readl(&cntl->regs->roothub_a);
94 rha &= ~(RH_A_PSM | RH_A_OCPM);
95 writel(&cntl->regs->roothub_status, RH_HS_LPSC);
96 writel(&cntl->regs->roothub_b, RH_B_PPCM);
97 msleep((rha >> 24) * 2);
98 // XXX - need to sleep for USB_TIME_SIGATT if just powered up?
100 // Lanuch a thread per port.
102 memset(&hub, 0, sizeof(hub));
103 hub.cntl = &cntl->usb;
104 int ports = rha & RH_A_NDP;
107 for (i=0; i<ports; i++) {
109 run_thread(init_ohci_port, &hub);
112 // Wait for threads to complete.
120 /****************************************************************
122 ****************************************************************/
125 start_ohci(struct usb_ohci_s *cntl, struct ohci_hcca *hcca)
127 u32 oldfminterval = readl(&cntl->regs->fminterval);
128 u32 oldrwc = readl(&cntl->regs->control) & OHCI_CTRL_RWC;
130 // XXX - check if already running?
133 writel(&cntl->regs->control, OHCI_USB_RESET | oldrwc);
134 readl(&cntl->regs->control); // flush writes
135 msleep(USB_TIME_DRSTR);
137 // Do software init (min 10us, max 2ms)
138 u64 end = calc_future_tsc_usec(10);
139 writel(&cntl->regs->cmdstatus, OHCI_HCR);
141 u32 status = readl(&cntl->regs->cmdstatus);
142 if (! status & OHCI_HCR)
144 if (check_time(end)) {
151 writel(&cntl->regs->ed_controlhead, 0);
152 writel(&cntl->regs->ed_bulkhead, 0);
153 writel(&cntl->regs->hcca, (u32)hcca);
156 u32 fi = oldfminterval & 0x3fff;
157 writel(&cntl->regs->fminterval
158 , (((oldfminterval & FIT) ^ FIT)
159 | fi | (((6 * (fi - 210)) / 7) << 16)));
160 writel(&cntl->regs->periodicstart, ((9 * fi) / 10) & 0x3fff);
161 readl(&cntl->regs->control); // flush writes
163 // XXX - verify that fminterval was setup correctly.
165 // Go into operational state
166 writel(&cntl->regs->control
167 , (OHCI_CTRL_CBSR | OHCI_CTRL_CLE | OHCI_CTRL_PLE
168 | OHCI_USB_OPER | oldrwc));
169 readl(&cntl->regs->control); // flush writes
175 stop_ohci(struct usb_ohci_s *cntl)
177 u32 oldrwc = readl(&cntl->regs->control) & OHCI_CTRL_RWC;
178 writel(&cntl->regs->control, oldrwc);
179 readl(&cntl->regs->control); // flush writes
183 configure_ohci(void *data)
185 struct usb_ohci_s *cntl = data;
188 struct ohci_hcca *hcca = memalign_high(256, sizeof(*hcca));
189 struct ohci_ed *intr_ed = malloc_high(sizeof(*intr_ed));
190 if (!hcca || !intr_ed) {
194 memset(hcca, 0, sizeof(*hcca));
195 memset(intr_ed, 0, sizeof(*intr_ed));
196 intr_ed->hwINFO = ED_SKIP;
198 for (i=0; i<ARRAY_SIZE(hcca->int_table); i++)
199 hcca->int_table[i] = (u32)intr_ed;
201 int ret = start_ohci(cntl, hcca);
205 int count = check_ohci_ports(cntl);
206 free_pipe(cntl->usb.defaultpipe);
219 ohci_init(u16 bdf, int busid)
221 if (! CONFIG_USB_OHCI)
223 struct usb_ohci_s *cntl = malloc_tmphigh(sizeof(*cntl));
224 memset(cntl, 0, sizeof(*cntl));
225 cntl->usb.busid = busid;
226 cntl->usb.type = USB_TYPE_OHCI;
228 u32 baseaddr = pci_config_readl(bdf, PCI_BASE_ADDRESS_0);
229 cntl->regs = (void*)(baseaddr & PCI_BASE_ADDRESS_MEM_MASK);
231 dprintf(3, "OHCI init on dev %02x:%02x.%x (regs=%p)\n"
232 , pci_bdf_to_bus(bdf), pci_bdf_to_dev(bdf)
233 , pci_bdf_to_fn(bdf), cntl->regs);
235 // Enable bus mastering and memory access.
236 pci_config_maskw(bdf, PCI_COMMAND
237 , 0, PCI_COMMAND_MASTER|PCI_COMMAND_MEMORY);
239 // XXX - check for and disable SMM control?
241 // Disable interrupts
242 writel(&cntl->regs->intrdisable, ~0);
243 writel(&cntl->regs->intrstatus, ~0);
245 run_thread(configure_ohci, cntl);
249 /****************************************************************
250 * End point communication
251 ****************************************************************/
254 wait_ed(struct ohci_ed *ed)
256 // XXX - 500ms just a guess
257 u64 end = calc_future_tsc(500);
259 if (ed->hwHeadP == ed->hwTailP)
261 if (check_time(end)) {
269 // Wait for next USB frame to start - for ensuring safe memory release.
271 ohci_waittick(struct usb_ohci_s *cntl)
274 struct ohci_hcca *hcca = (void*)cntl->regs->hcca;
275 u32 startframe = hcca->frame_no;
276 u64 end = calc_future_tsc(1000 * 5);
278 if (hcca->frame_no != startframe)
280 if (check_time(end)) {
289 signal_freelist(struct usb_ohci_s *cntl)
291 u32 v = readl(&cntl->regs->control);
292 if (v & OHCI_CTRL_CLE) {
293 writel(&cntl->regs->control, v & ~(OHCI_CTRL_CLE|OHCI_CTRL_BLE));
295 writel(&cntl->regs->ed_controlcurrent, 0);
296 writel(&cntl->regs->ed_bulkcurrent, 0);
297 writel(&cntl->regs->control, v);
305 struct usb_pipe pipe;
312 ohci_free_pipe(struct usb_pipe *p)
314 if (! CONFIG_USB_OHCI)
316 dprintf(7, "ohci_free_pipe %p\n", p);
317 struct ohci_pipe *pipe = container_of(p, struct ohci_pipe, pipe);
318 struct usb_ohci_s *cntl = container_of(
319 pipe->pipe.cntl, struct usb_ohci_s, usb);
321 u32 *pos = &cntl->regs->ed_controlhead;
323 struct ohci_ed *next = (void*)*pos;
325 // Not found?! Exit without freeing.
326 warn_internalerror();
329 if (next == &pipe->ed) {
330 *pos = next->hwNextED;
331 signal_freelist(cntl);
335 pos = &next->hwNextED;
340 ohci_alloc_control_pipe(struct usb_pipe *dummy)
342 if (! CONFIG_USB_OHCI)
344 struct usb_ohci_s *cntl = container_of(
345 dummy->cntl, struct usb_ohci_s, usb);
346 dprintf(7, "ohci_alloc_control_pipe %p\n", &cntl->usb);
348 // Allocate a queue head.
349 struct ohci_pipe *pipe = malloc_tmphigh(sizeof(*pipe));
354 memset(pipe, 0, sizeof(*pipe));
355 memcpy(&pipe->pipe, dummy, sizeof(pipe->pipe));
356 pipe->ed.hwINFO = ED_SKIP;
358 // Add queue head to controller list.
359 pipe->ed.hwNextED = cntl->regs->ed_controlhead;
361 cntl->regs->ed_controlhead = (u32)&pipe->ed;
366 ohci_control(struct usb_pipe *p, int dir, const void *cmd, int cmdsize
367 , void *data, int datasize)
369 if (! CONFIG_USB_OHCI)
371 dprintf(5, "ohci_control %p\n", p);
372 if (datasize > 4096) {
373 // XXX - should support larger sizes.
377 struct ohci_pipe *pipe = container_of(p, struct ohci_pipe, pipe);
378 struct usb_ohci_s *cntl = container_of(
379 pipe->pipe.cntl, struct usb_ohci_s, usb);
380 int maxpacket = pipe->pipe.maxpacket;
381 int lowspeed = pipe->pipe.lowspeed;
382 int devaddr = pipe->pipe.devaddr | (pipe->pipe.ep << 7);
384 // Setup transfer descriptors
385 struct ohci_td *tds = malloc_tmphigh(sizeof(*tds) * 3);
390 struct ohci_td *td = tds;
391 td->hwINFO = TD_DP_SETUP | TD_T_DATA0 | TD_CC;
392 td->hwCBP = (u32)cmd;
393 td->hwNextTD = (u32)&td[1];
394 td->hwBE = (u32)cmd + cmdsize - 1;
397 td->hwINFO = (dir ? TD_DP_IN : TD_DP_OUT) | TD_T_DATA1 | TD_CC;
398 td->hwCBP = (u32)data;
399 td->hwNextTD = (u32)&td[1];
400 td->hwBE = (u32)data + datasize - 1;
403 td->hwINFO = (dir ? TD_DP_OUT : TD_DP_IN) | TD_T_DATA1 | TD_CC;
405 td->hwNextTD = (u32)&td[1];
410 pipe->ed.hwINFO = ED_SKIP;
412 pipe->ed.hwHeadP = (u32)tds;
413 pipe->ed.hwTailP = (u32)td;
415 pipe->ed.hwINFO = devaddr | (maxpacket << 16) | (lowspeed ? ED_LOWSPEED : 0);
416 writel(&cntl->regs->cmdstatus, OHCI_CLF);
418 int ret = wait_ed(&pipe->ed);
419 pipe->ed.hwINFO = ED_SKIP;
427 ohci_alloc_intr_pipe(struct usb_pipe *dummy, int frameexp)
429 if (! CONFIG_USB_OHCI)
431 struct usb_ohci_s *cntl = container_of(
432 dummy->cntl, struct usb_ohci_s, usb);
433 dprintf(7, "ohci_alloc_intr_pipe %p %d\n", &cntl->usb, frameexp);
437 int maxpacket = dummy->maxpacket;
438 int lowspeed = dummy->lowspeed;
439 int devaddr = dummy->devaddr | (dummy->ep << 7);
440 // Determine number of entries needed for 2 timer ticks.
441 int ms = 1<<frameexp;
442 int count = DIV_ROUND_UP(PIT_TICK_INTERVAL * 1000 * 2, PIT_TICK_RATE * ms)+1;
443 struct ohci_pipe *pipe = malloc_low(sizeof(*pipe));
444 struct ohci_td *tds = malloc_low(sizeof(*tds) * count);
445 void *data = malloc_low(maxpacket * count);
446 if (!pipe || !tds || !data)
448 memset(pipe, 0, sizeof(*pipe));
449 memcpy(&pipe->pipe, dummy, sizeof(pipe->pipe));
454 struct ohci_ed *ed = &pipe->ed;
455 ed->hwHeadP = (u32)&tds[0];
456 ed->hwTailP = (u32)&tds[count-1];
457 ed->hwINFO = devaddr | (maxpacket << 16) | (lowspeed ? ED_LOWSPEED : 0);
460 for (i=0; i<count-1; i++) {
461 tds[i].hwINFO = TD_DP_IN | TD_T_TOGGLE | TD_CC;
462 tds[i].hwCBP = (u32)data + maxpacket * i;
463 tds[i].hwNextTD = (u32)&tds[i+1];
464 tds[i].hwBE = tds[i].hwCBP + maxpacket - 1;
467 // Add to interrupt schedule.
469 struct ohci_hcca *hcca = (void*)cntl->regs->hcca;
471 // Add to existing interrupt entry.
472 struct ohci_ed *intr_ed = (void*)hcca->int_table[0];
473 ed->hwNextED = intr_ed->hwNextED;
474 intr_ed->hwNextED = (u32)ed;
476 int startpos = 1<<(frameexp-1);
477 ed->hwNextED = hcca->int_table[startpos];
478 for (i=startpos; i<ARRAY_SIZE(hcca->int_table); i+=ms)
479 hcca->int_table[i] = (u32)ed;
492 ohci_poll_intr(struct usb_pipe *p, void *data)
495 if (! CONFIG_USB_OHCI)
498 struct ohci_pipe *pipe = container_of(p, struct ohci_pipe, pipe);
499 struct ohci_td *tds = GET_FLATPTR(pipe->tds);
500 struct ohci_td *head = (void*)GET_FLATPTR(pipe->ed.hwHeadP);
501 struct ohci_td *tail = (void*)GET_FLATPTR(pipe->ed.hwTailP);
502 int count = GET_FLATPTR(pipe->count);
503 int pos = (tail - tds + 1) % count;
504 struct ohci_td *next = &tds[pos];
508 // XXX - check for errors.
511 int maxpacket = GET_FLATPTR(pipe->pipe.maxpacket);
512 void *pipedata = GET_FLATPTR(pipe->data);
513 void *intrdata = pipedata + maxpacket * pos;
514 memcpy_far(GET_SEG(SS), data
515 , FLATPTR_TO_SEG(intrdata), (void*)FLATPTR_TO_OFFSET(intrdata)
519 SET_FLATPTR(tail->hwINFO, TD_DP_IN | TD_T_TOGGLE | TD_CC);
520 intrdata = pipedata + maxpacket * (tail-tds);
521 SET_FLATPTR(tail->hwCBP, (u32)intrdata);
522 SET_FLATPTR(tail->hwNextTD, (u32)next);
523 SET_FLATPTR(tail->hwBE, (u32)intrdata + maxpacket - 1);
525 SET_FLATPTR(pipe->ed.hwTailP, (u32)next);