1 // 16bit system callbacks
3 // Copyright (C) 2008 Kevin O'Connor <kevin@koconnor.net>
4 // Copyright (C) 2002 MandrakeSoft S.A.
6 // This file may be distributed under the terms of the GNU GPLv3 license.
8 #include "util.h" // irq_restore
9 #include "biosvar.h" // CONFIG_BIOS_TABLE
10 #include "ioport.h" // inb
11 #include "cmos.h" // inb_cmos
14 #define E820_RESERVED 2
17 #define E820_UNUSABLE 5
19 // Use PS2 System Control port A to set A20 enable
23 // get current setting first
24 u8 newval, oldval = inb(PORT_A20);
26 newval = oldval | 0x02;
28 newval = oldval & ~0x02;
29 outb(newval, PORT_A20);
31 return (newval & 0x02) != 0;
35 handle_152400(struct bregs *regs)
42 handle_152401(struct bregs *regs)
49 handle_152402(struct bregs *regs)
51 regs->al = !!(inb(PORT_A20) & 0x20);
56 handle_152403(struct bregs *regs)
63 handle_1524XX(struct bregs *regs)
65 handle_ret(regs, RET_EUNSUPPORTED);
69 handle_1524(struct bregs *regs)
72 case 0x00: handle_152400(regs); break;
73 case 0x01: handle_152401(regs); break;
74 case 0x02: handle_152402(regs); break;
75 case 0x03: handle_152403(regs); break;
76 default: handle_1524XX(regs); break;
80 // removable media eject
82 handle_1552(struct bregs *regs)
87 // Sleep for n microseconds. currently using the
88 // refresh request port 0x61 bit4, toggling every 15usec
93 u8 kbd = inb(PORT_PS2_CTRLB);
95 if ((inb(PORT_PS2_CTRLB) ^ kbd) & KBD_REFRESH)
99 // Wait for CX:DX microseconds. currently using the
100 // refresh request port 0x61 bit4, toggling every 15usec
102 handle_1586(struct bregs *regs)
105 usleep((regs->cx << 16) | regs->dx);
110 handle_1587(struct bregs *regs)
112 // +++ should probably have descriptor checks
113 // +++ should have exception handlers
115 u8 prev_a20_enable = set_a20(1); // enable A20 line
117 // 128K max of transfer on 386+ ???
118 // source == destination ???
120 // ES:SI points to descriptor table
121 // offset use initially comments
122 // ==============================================
123 // 00..07 Unused zeros Null descriptor
124 // 08..0f GDT zeros filled in by BIOS
125 // 10..17 source ssssssss source of data
126 // 18..1f dest dddddddd destination of data
127 // 20..27 CS zeros filled in by BIOS
128 // 28..2f SS zeros filled in by BIOS
135 // check for access rights of source & dest here
137 // Initialize GDT descriptor
139 u16 base15_00 = (regs->es << 4) + si;
140 u16 base23_16 = regs->es >> 12;
141 if (base15_00 < (regs->es<<4))
143 SET_VAR(ES, *(u16*)(si+0x08+0), 47); // limit 15:00 = 6 * 8bytes/descriptor
144 SET_VAR(ES, *(u16*)(si+0x08+2), base15_00);// base 15:00
145 SET_VAR(ES, *(u8 *)(si+0x08+4), base23_16);// base 23:16
146 SET_VAR(ES, *(u8 *)(si+0x08+5), 0x93); // access
147 SET_VAR(ES, *(u16*)(si+0x08+6), 0x0000); // base 31:24/reserved/limit 19:16
149 // Initialize CS descriptor
150 SET_VAR(ES, *(u16*)(si+0x20+0), 0xffff);// limit 15:00 = normal 64K limit
151 SET_VAR(ES, *(u16*)(si+0x20+2), 0x0000);// base 15:00
152 SET_VAR(ES, *(u8 *)(si+0x20+4), 0x000f);// base 23:16
153 SET_VAR(ES, *(u8 *)(si+0x20+5), 0x9b); // access
154 SET_VAR(ES, *(u16*)(si+0x20+6), 0x0000);// base 31:24/reserved/limit 19:16
156 // Initialize SS descriptor
157 u16 ss = GET_SEG(SS);
159 base23_16 = ss >> 12;
160 SET_VAR(ES, *(u16*)(si+0x28+0), 0xffff); // limit 15:00 = normal 64K limit
161 SET_VAR(ES, *(u16*)(si+0x28+2), base15_00);// base 15:00
162 SET_VAR(ES, *(u8 *)(si+0x28+4), base23_16);// base 23:16
163 SET_VAR(ES, *(u8 *)(si+0x28+5), 0x93); // access
164 SET_VAR(ES, *(u16*)(si+0x28+6), 0x0000); // base 31:24/reserved/limit 19:16
167 // Load new descriptor tables
169 "lidt %%cs:pmode_IDT_info\n"
172 "movl %%cr0, %%eax\n"
174 "movl %%eax, %%cr0\n"
176 // far jump to flush CPU queue after transition to protected mode
177 "ljmpw $0x0020, $1f\n"
180 // GDT points to valid descriptor table, now load DS, ES
181 "movw $0x10, %%ax\n" // 010 000 = 2nd descriptor in table, TI=GDT, RPL=00
183 "movw $0x18, %%ax\n" // 011 000 = 3rd descriptor in table, TI=GDT, RPL=00
186 // move CX words from DS:SI to ES:DI
192 // reset PG bit in CR0 ???
193 "movl %%cr0, %%eax\n"
195 "movl %%eax, %%cr0\n"
197 // far jump to flush CPU queue after transition to real mode
198 "ljmpw $0xf000, $2f\n"
201 // restore IDT to normal real-mode defaults
202 "lidt %%cs:rmode_IDT_info\n"
204 // Restore %ds (from %ss)
207 : : "c" (regs->cx), "r" (si + 8)
208 : "eax", "di", "si"); // XXX - also clobbers %es
210 set_a20(prev_a20_enable);
215 // Get the amount of extended memory (above 1M)
217 handle_1588(struct bregs *regs)
219 regs->al = inb_cmos(CMOS_MEM_EXTMEM_LOW);
220 regs->ah = inb_cmos(CMOS_MEM_EXTMEM_HIGH);
221 // According to Ralf Brown's interrupt the limit should be 15M,
222 // but real machines mostly return max. 63M.
223 if (regs->ax > 0xffc0)
228 // Device busy interrupt. Called by Int 16h when no key available
230 handle_1590(struct bregs *regs)
234 // Interrupt complete. Called by Int 16h when key becomes available
236 handle_1591(struct bregs *regs)
240 // keyboard intercept
242 handle_154f(struct bregs *regs)
248 handle_15c0(struct bregs *regs)
251 regs->bx = (u16)&BIOS_CONFIG_TABLE;
256 handle_15c1(struct bregs *regs)
258 regs->es = GET_BDA(ebda_seg);
263 handle_15e801(struct bregs *regs)
265 // my real system sets ax and bx to 0
266 // this is confirmed by Ralph Brown list
267 // but syslinux v1.48 is known to behave
268 // strangely if ax is set to 0
269 // regs.u.r16.ax = 0;
270 // regs.u.r16.bx = 0;
272 // Get the amount of extended memory (above 1M)
273 regs->cl = inb_cmos(CMOS_MEM_EXTMEM_LOW);
274 regs->ch = inb_cmos(CMOS_MEM_EXTMEM_HIGH);
277 if (regs->cx > 0x3c00)
280 // Get the amount of extended memory above 16M in 64k blocs
281 regs->dl = inb_cmos(CMOS_MEM_EXTMEM2_LOW);
282 regs->dh = inb_cmos(CMOS_MEM_EXTMEM2_HIGH);
284 // Set configured memory equal to extended memory
291 #define ACPI_DATA_SIZE 0x00010000L
294 set_e820_range(u16 DI, u32 start, u32 end, u16 type)
296 SET_VAR(ES, *(u16*)(DI+0), start);
297 SET_VAR(ES, *(u16*)(DI+2), start >> 16);
298 SET_VAR(ES, *(u16*)(DI+4), 0x00);
299 SET_VAR(ES, *(u16*)(DI+6), 0x00);
302 SET_VAR(ES, *(u16*)(DI+8), end);
303 SET_VAR(ES, *(u16*)(DI+10), end >> 16);
304 SET_VAR(ES, *(u16*)(DI+12), 0x0000);
305 SET_VAR(ES, *(u16*)(DI+14), 0x0000);
307 SET_VAR(ES, *(u16*)(DI+16), type);
308 SET_VAR(ES, *(u16*)(DI+18), 0x0);
311 // XXX - should create e820 memory map in post and just copy it here.
313 handle_15e820(struct bregs *regs)
315 if (regs->edx != 0x534D4150) {
316 handle_ret(regs, RET_EUNSUPPORTED);
320 u32 extended_memory_size = inb_cmos(CMOS_MEM_EXTMEM2_HIGH);
321 extended_memory_size <<= 8;
322 extended_memory_size |= inb_cmos(CMOS_MEM_EXTMEM2_LOW);
323 extended_memory_size *= 64;
324 // greater than EFF00000???
325 if (extended_memory_size > 0x3bc000)
326 // everything after this is reserved memory until we get to 0x100000000
327 extended_memory_size = 0x3bc000;
328 extended_memory_size *= 1024;
329 extended_memory_size += (16L * 1024 * 1024);
331 if (extended_memory_size <= (16L * 1024 * 1024)) {
332 extended_memory_size = inb_cmos(CMOS_MEM_EXTMEM_HIGH);
333 extended_memory_size <<= 8;
334 extended_memory_size |= inb_cmos(CMOS_MEM_EXTMEM_LOW);
335 extended_memory_size *= 1024;
340 set_e820_range(regs->di, 0x0000000L, 0x0009fc00L, E820_RAM);
342 regs->eax = 0x534D4150;
347 set_e820_range(regs->di, 0x0009fc00L, 0x000a0000L, E820_RESERVED);
349 regs->eax = 0x534D4150;
354 set_e820_range(regs->di, 0x000e8000L, 0x00100000L, E820_RESERVED);
356 regs->eax = 0x534D4150;
361 set_e820_range(regs->di, 0x00100000L,
362 extended_memory_size - ACPI_DATA_SIZE, E820_RAM);
364 regs->eax = 0x534D4150;
369 set_e820_range(regs->di,
370 extended_memory_size - ACPI_DATA_SIZE,
371 extended_memory_size, E820_ACPI); // ACPI RAM
373 regs->eax = 0x534D4150;
378 /* 256KB BIOS area at the end of 4 GB */
379 set_e820_range(regs->di, 0xfffc0000L, 0x00000000L, E820_RESERVED);
381 regs->eax = 0x534D4150;
385 default: /* AX=E820, DX=534D4150, BX unrecognized */
386 handle_ret(regs, RET_EUNSUPPORTED);
391 handle_15e8XX(struct bregs *regs)
393 handle_ret(regs, RET_EUNSUPPORTED);
397 handle_15e8(struct bregs *regs)
400 case 0x01: handle_15e801(regs); break;
401 case 0x20: handle_15e820(regs); break;
402 default: handle_15e8XX(regs); break;
407 handle_15XX(struct bregs *regs)
409 handle_ret(regs, RET_EUNSUPPORTED);
412 // INT 15h System Services Entry Point
414 handle_15(struct bregs *regs)
418 case 0x24: handle_1524(regs); break;
419 case 0x4f: handle_154f(regs); break;
420 case 0x52: handle_1552(regs); break;
421 case 0x53: handle_1553(regs); break;
422 case 0x83: handle_1583(regs); break;
423 case 0x86: handle_1586(regs); break;
424 case 0x87: handle_1587(regs); break;
425 case 0x88: handle_1588(regs); break;
426 case 0x90: handle_1590(regs); break;
427 case 0x91: handle_1591(regs); break;
428 case 0xc0: handle_15c0(regs); break;
429 case 0xc1: handle_15c1(regs); break;
430 case 0xc2: handle_15c2(regs); break;
431 case 0xe8: handle_15e8(regs); break;
432 default: handle_15XX(regs); break;
437 // INT 12h Memory Size Service Entry Point
439 handle_12(struct bregs *regs)
442 regs->ax = GET_BDA(mem_size_kb);
446 // INT 11h Equipment List Service Entry Point
448 handle_11(struct bregs *regs)
451 regs->ax = GET_BDA(equipment_list_flags);
455 // INT 05h Print Screen Service Entry Point
457 handle_05(struct bregs *regs)
462 // INT 10h Video Support Service Entry Point
464 handle_10(struct bregs *regs)
467 // dont do anything, since the VGA BIOS handles int10h requests
471 handle_nmi(struct bregs *regs)
477 // INT 75 - IRQ13 - MATH COPROCESSOR EXCEPTION
479 handle_75(struct bregs *regs)
484 outb(0, PORT_MATH_CLEAR);
489 memset(&br, 0, sizeof(br));
490 call16_int(0x02, &br);