1 // Support for enabling/disabling BIOS ram shadowing.
3 // Copyright (C) 2008,2009 Kevin O'Connor <kevin@koconnor.net>
4 // Copyright (C) 2006 Fabrice Bellard
6 // This file may be distributed under the terms of the GNU LGPLv3 license.
8 #include "util.h" // memcpy
9 #include "pci.h" // pci_config_writeb
10 #include "config.h" // CONFIG_*
11 #include "pci_ids.h" // PCI_VENDOR_ID_INTEL
12 #include "dev-i440fx.h"
14 // Test if 'addr' is in the range from 'start'..'start+size'
15 #define IN_RANGE(addr, start, size) ({ \
16 u32 __addr = (addr); \
17 u32 __start = (start); \
18 u32 __size = (size); \
19 (__addr - __start < __size); \
22 // On the emulators, the bios at 0xf0000 is also at 0xffff0000
23 #define BIOS_SRC_ADDR 0xffff0000
25 // Enable shadowing and copy bios.
27 __make_bios_writable_intel(u16 bdf, u32 pam0)
29 // Make ram from 0xc0000-0xf0000 writable
33 u32 pam = pam0 + 1 + i;
34 int reg = pci_config_readb(bdf, pam);
35 if ((reg & 0x11) != 0x11) {
36 // Need to copy optionroms to work around qemu implementation
37 void *mem = (void*)(BUILD_ROM_START + i * 32*1024);
38 memcpy((void*)BUILD_BIOS_TMP_ADDR, mem, 32*1024);
39 pci_config_writeb(bdf, pam, 0x33);
40 memcpy(mem, (void*)BUILD_BIOS_TMP_ADDR, 32*1024);
43 pci_config_writeb(bdf, pam, 0x33);
47 memset((void*)BUILD_BIOS_TMP_ADDR, 0, 32*1024);
49 // Make ram from 0xf0000-0x100000 writable
50 int reg = pci_config_readb(bdf, pam0);
51 pci_config_writeb(bdf, pam0, 0x30);
53 // Ram already present.
57 memcpy((void*)BUILD_BIOS_ADDR, (void*)BIOS_SRC_ADDR, BUILD_BIOS_SIZE);
61 make_bios_writable_intel(u16 bdf, u32 pam0)
63 int reg = pci_config_readb(bdf, pam0);
65 // QEMU doesn't fully implement the piix shadow capabilities -
66 // if ram isn't backing the bios segment when shadowing is
67 // disabled, the code itself wont be in memory. So, run the
68 // code from the high-memory flash location.
69 u32 pos = (u32)__make_bios_writable_intel - BUILD_BIOS_ADDR +
71 void (*func)(u16 bdf, u32 pam0) = (void*)pos;
75 // Ram already present - just enable writes
76 __make_bios_writable_intel(bdf, pam0);
80 make_bios_readonly_intel(u16 bdf, u32 pam0)
82 // Flush any pending writes before locking memory.
85 // Write protect roms from 0xc0000-0xf0000
88 u32 mem = BUILD_ROM_START + i * 32*1024;
89 u32 pam = pam0 + 1 + i;
90 if (RomEnd <= mem + 16*1024) {
92 pci_config_writeb(bdf, pam, 0x31);
95 pci_config_writeb(bdf, pam, 0x11);
98 // Write protect 0xf0000-0x100000
99 pci_config_writeb(bdf, pam0, 0x10);
102 static const struct pci_device_id dram_controller_make_writable_tbl[] = {
103 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441,
104 i440fx_bios_make_writable),
108 // Make the 0xc0000-0x100000 area read/writable.
110 make_bios_writable(void)
115 dprintf(3, "enabling shadow ram\n");
117 // at this point, staticlly alloacted variable can't written.
118 // so stack should be used.
120 // Locate chip controlling ram shadowing.
121 int bdf = pci_find_init_device(dram_controller_make_writable_tbl, NULL);
123 dprintf(1, "Unable to unlock ram - bridge not found\n");
127 static const struct pci_device_id dram_controller_make_readonly_tbl[] = {
128 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441,
129 i440fx_bios_make_readonly),
133 // Make the BIOS code segment area (0xf0000) read-only.
135 make_bios_readonly(void)
140 dprintf(3, "locking shadow ram\n");
141 int bdf = pci_find_init_device(dram_controller_make_readonly_tbl, NULL);
143 dprintf(1, "Unable to lock ram - bridge not found\n");