1 // Initialize PCI devices (on emulators)
3 // Copyright (C) 2008 Kevin O'Connor <kevin@koconnor.net>
4 // Copyright (C) 2006 Fabrice Bellard
6 // This file may be distributed under the terms of the GNU GPLv3 license.
8 #include "util.h" // dprintf
9 #include "pci.h" // pci_config_readl
10 #include "biosvar.h" // GET_EBDA
11 #include "pci_ids.h" // PCI_VENDOR_ID_INTEL
12 #include "pci_regs.h" // PCI_COMMAND
14 #define PCI_ADDRESS_SPACE_MEM 0x00
15 #define PCI_ADDRESS_SPACE_IO 0x01
16 #define PCI_ADDRESS_SPACE_MEM_PREFETCH 0x08
18 #define PCI_ROM_SLOT 6
19 #define PCI_NUM_REGIONS 7
21 static u32 pci_bios_io_addr;
22 static u32 pci_bios_mem_addr;
23 static u32 pci_bios_bigmem_addr;
24 /* host irqs corresponding to PCI irqs A-D */
25 static u8 pci_irqs[4] = { 11, 9, 11, 9 };
27 static void pci_set_io_region_addr(u16 bdf, int region_num, u32 addr)
32 if ( region_num == PCI_ROM_SLOT ) {
35 ofs = 0x10 + region_num * 4;
38 old_addr = pci_config_readl(bdf, ofs);
40 pci_config_writel(bdf, ofs, addr);
41 dprintf(1, "region %d: 0x%08x\n", region_num, addr);
43 /* enable memory mappings */
44 cmd = pci_config_readw(bdf, PCI_COMMAND);
45 if ( region_num == PCI_ROM_SLOT )
47 else if (old_addr & PCI_ADDRESS_SPACE_IO)
51 pci_config_writew(bdf, PCI_COMMAND, cmd);
54 /* return the global irq number corresponding to a given device irq
55 pin. We could also use the bus number to have a more precise
57 static int pci_slot_get_pirq(u16 bdf, int irq_num)
59 int slot_addend = pci_bdf_to_dev(bdf) - 1;
60 return (irq_num + slot_addend) & 3;
63 static void pci_bios_init_bridges(u16 bdf)
65 u16 vendor_id = pci_config_readw(bdf, PCI_VENDOR_ID);
66 u16 device_id = pci_config_readw(bdf, PCI_DEVICE_ID);
68 if (vendor_id == PCI_VENDOR_ID_INTEL
69 && (device_id == PCI_DEVICE_ID_INTEL_82371SB_0
70 || device_id == PCI_DEVICE_ID_INTEL_82371AB_0)) {
74 /* PIIX3/PIIX4 PCI to ISA bridge */
78 for(i = 0; i < 4; i++) {
80 /* set to trigger level */
81 elcr[irq >> 3] |= (1 << (irq & 7));
82 /* activate irq remapping in PIIX */
83 pci_config_writeb(bdf, 0x60 + i, irq);
87 dprintf(1, "PIIX3/PIIX4 init: elcr=%02x %02x\n",
92 static void pci_bios_init_device(u16 bdf)
96 int i, pin, pic_irq, vendor_id, device_id;
98 class = pci_config_readw(bdf, PCI_CLASS_DEVICE);
99 vendor_id = pci_config_readw(bdf, PCI_VENDOR_ID);
100 device_id = pci_config_readw(bdf, PCI_DEVICE_ID);
101 dprintf(1, "PCI: bus=%d devfn=0x%02x: vendor_id=0x%04x device_id=0x%04x\n"
102 , pci_bdf_to_bus(bdf), pci_bdf_to_devfn(bdf), vendor_id, device_id);
105 if (vendor_id == PCI_VENDOR_ID_INTEL
106 && (device_id == PCI_DEVICE_ID_INTEL_82371SB_1
107 || device_id == PCI_DEVICE_ID_INTEL_82371AB)) {
108 /* PIIX3/PIIX4 IDE */
109 pci_config_writew(bdf, 0x40, 0x8000); // enable IDE0
110 pci_config_writew(bdf, 0x42, 0x8000); // enable IDE1
113 /* IDE: we map it as in ISA mode */
114 pci_set_io_region_addr(bdf, 0, 0x1f0);
115 pci_set_io_region_addr(bdf, 1, 0x3f4);
116 pci_set_io_region_addr(bdf, 2, 0x170);
117 pci_set_io_region_addr(bdf, 3, 0x374);
121 if (vendor_id != 0x1234)
123 /* VGA: map frame buffer to default Bochs VBE address */
124 pci_set_io_region_addr(bdf, 0, 0xE0000000);
128 if (vendor_id == PCI_VENDOR_ID_IBM) {
130 if (device_id == 0x0046 || device_id == 0xFFFF) {
132 pci_set_io_region_addr(bdf, 0, 0x80800000 + 0x00040000);
137 if (vendor_id == PCI_VENDOR_ID_APPLE &&
138 (device_id == 0x0017 || device_id == 0x0022)) {
140 pci_set_io_region_addr(bdf, 0, 0x80800000);
145 /* default memory mappings */
146 for(i = 0; i < PCI_NUM_REGIONS; i++) {
150 if (i == PCI_ROM_SLOT)
154 pci_config_writel(bdf, ofs, 0xffffffff);
155 val = pci_config_readl(bdf, ofs);
157 size = (~(val & ~0xf)) + 1;
158 if (val & PCI_ADDRESS_SPACE_IO)
159 paddr = &pci_bios_io_addr;
160 else if (size >= 0x04000000)
161 paddr = &pci_bios_bigmem_addr;
163 paddr = &pci_bios_mem_addr;
164 *paddr = ALIGN(*paddr, size);
165 pci_set_io_region_addr(bdf, i, *paddr);
172 /* map the interrupt */
173 pin = pci_config_readb(bdf, PCI_INTERRUPT_PIN);
175 pin = pci_slot_get_pirq(bdf, pin - 1);
176 pic_irq = pci_irqs[pin];
177 pci_config_writeb(bdf, PCI_INTERRUPT_LINE, pic_irq);
180 if (vendor_id == PCI_VENDOR_ID_INTEL
181 && device_id == PCI_DEVICE_ID_INTEL_82371AB_3) {
182 /* PIIX4 Power Management device (for ACPI) */
183 pci_config_writel(bdf, 0x40, PORT_ACPI_PM_BASE | 1);
184 pci_config_writeb(bdf, 0x80, 0x01); /* enable PM io space */
185 pci_config_writel(bdf, 0x90, PORT_SMB_BASE | 1);
186 pci_config_writeb(bdf, 0xd2, 0x09); /* enable SMBus io space */
194 // Already done by coreboot.
197 pci_bios_io_addr = 0xc000;
198 pci_bios_mem_addr = 0xf0000000;
199 pci_bios_bigmem_addr = GET_EBDA(ram_size);
200 if (pci_bios_bigmem_addr < 0x90000000)
201 pci_bios_bigmem_addr = 0x90000000;
204 foreachpci(bdf, max) {
205 pci_bios_init_bridges(bdf);
207 foreachpci(bdf, max) {
208 pci_bios_init_device(bdf);