1 // Initialize PCI devices (on emulators)
3 // Copyright (C) 2008 Kevin O'Connor <kevin@koconnor.net>
4 // Copyright (C) 2006 Fabrice Bellard
6 // This file may be distributed under the terms of the GNU LGPLv3 license.
8 #include "util.h" // dprintf
9 #include "pci.h" // pci_config_readl
10 #include "biosvar.h" // GET_EBDA
11 #include "pci_ids.h" // PCI_VENDOR_ID_INTEL
12 #include "pci_regs.h" // PCI_COMMAND
14 #define PCI_ROM_SLOT 6
15 #define PCI_NUM_REGIONS 7
17 static u32 pci_bios_io_addr;
18 static u32 pci_bios_mem_addr;
19 static u32 pci_bios_bigmem_addr;
20 /* host irqs corresponding to PCI irqs A-D */
21 static u8 pci_irqs[4] = {
25 static void pci_set_io_region_addr(u16 bdf, int region_num, u32 addr)
29 if (region_num == PCI_ROM_SLOT) {
30 ofs = PCI_ROM_ADDRESS;
32 ofs = PCI_BASE_ADDRESS_0 + region_num * 4;
35 old_addr = pci_config_readl(bdf, ofs);
37 pci_config_writel(bdf, ofs, addr);
38 dprintf(1, "region %d: 0x%08x\n", region_num, addr);
41 /* return the global irq number corresponding to a given device irq
42 pin. We could also use the bus number to have a more precise
44 static int pci_slot_get_pirq(u16 bdf, int irq_num)
46 int slot_addend = pci_bdf_to_dev(bdf) - 1;
47 return (irq_num + slot_addend) & 3;
50 static void pci_bios_init_bridges(u16 bdf)
52 u16 vendor_id = pci_config_readw(bdf, PCI_VENDOR_ID);
53 u16 device_id = pci_config_readw(bdf, PCI_DEVICE_ID);
55 if (vendor_id == PCI_VENDOR_ID_INTEL
56 && (device_id == PCI_DEVICE_ID_INTEL_82371SB_0
57 || device_id == PCI_DEVICE_ID_INTEL_82371AB_0)) {
61 /* PIIX3/PIIX4 PCI to ISA bridge */
65 for (i = 0; i < 4; i++) {
67 /* set to trigger level */
68 elcr[irq >> 3] |= (1 << (irq & 7));
69 /* activate irq remapping in PIIX */
70 pci_config_writeb(bdf, 0x60 + i, irq);
74 dprintf(1, "PIIX3/PIIX4 init: elcr=%02x %02x\n",
79 static void pci_bios_init_device(u16 bdf)
83 int i, pin, pic_irq, vendor_id, device_id;
85 class = pci_config_readw(bdf, PCI_CLASS_DEVICE);
86 vendor_id = pci_config_readw(bdf, PCI_VENDOR_ID);
87 device_id = pci_config_readw(bdf, PCI_DEVICE_ID);
88 dprintf(1, "PCI: bus=%d devfn=0x%02x: vendor_id=0x%04x device_id=0x%04x\n"
89 , pci_bdf_to_bus(bdf), pci_bdf_to_devfn(bdf), vendor_id, device_id);
91 case PCI_CLASS_STORAGE_IDE:
92 if (vendor_id == PCI_VENDOR_ID_INTEL
93 && (device_id == PCI_DEVICE_ID_INTEL_82371SB_1
94 || device_id == PCI_DEVICE_ID_INTEL_82371AB)) {
96 pci_config_writew(bdf, 0x40, 0x8000); // enable IDE0
97 pci_config_writew(bdf, 0x42, 0x8000); // enable IDE1
100 /* IDE: we map it as in ISA mode */
101 pci_set_io_region_addr(bdf, 0, 0x1f0);
102 pci_set_io_region_addr(bdf, 1, 0x3f4);
103 pci_set_io_region_addr(bdf, 2, 0x170);
104 pci_set_io_region_addr(bdf, 3, 0x374);
107 case PCI_CLASS_SYSTEM_PIC:
109 if (vendor_id == PCI_VENDOR_ID_IBM) {
111 if (device_id == 0x0046 || device_id == 0xFFFF) {
113 pci_set_io_region_addr(bdf, 0, 0x80800000 + 0x00040000);
118 if (vendor_id == PCI_VENDOR_ID_APPLE &&
119 (device_id == 0x0017 || device_id == 0x0022)) {
121 pci_set_io_region_addr(bdf, 0, 0x80800000);
126 /* default memory mappings */
127 for (i = 0; i < PCI_NUM_REGIONS; i++) {
131 if (i == PCI_ROM_SLOT)
132 ofs = PCI_ROM_ADDRESS;
134 ofs = PCI_BASE_ADDRESS_0 + i * 4;
135 pci_config_writel(bdf, ofs, 0xffffffff);
136 val = pci_config_readl(bdf, ofs);
138 size = (~(val & ~0xf)) + 1;
139 if (val & PCI_BASE_ADDRESS_SPACE_IO)
140 paddr = &pci_bios_io_addr;
141 else if (size >= 0x04000000)
142 paddr = &pci_bios_bigmem_addr;
144 paddr = &pci_bios_mem_addr;
145 *paddr = ALIGN(*paddr, size);
146 pci_set_io_region_addr(bdf, i, *paddr);
153 /* enable memory mappings */
154 pci_config_maskw(bdf, PCI_COMMAND, 0, PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
156 /* map the interrupt */
157 pin = pci_config_readb(bdf, PCI_INTERRUPT_PIN);
159 pin = pci_slot_get_pirq(bdf, pin - 1);
160 pic_irq = pci_irqs[pin];
161 pci_config_writeb(bdf, PCI_INTERRUPT_LINE, pic_irq);
164 if (vendor_id == PCI_VENDOR_ID_INTEL
165 && device_id == PCI_DEVICE_ID_INTEL_82371AB_3) {
166 /* PIIX4 Power Management device (for ACPI) */
168 // acpi sci is hardwired to 9
169 pci_config_writeb(bdf, PCI_INTERRUPT_LINE, 9);
171 pci_config_writel(bdf, 0x40, PORT_ACPI_PM_BASE | 1);
172 pci_config_writeb(bdf, 0x80, 0x01); /* enable PM io space */
173 pci_config_writel(bdf, 0x90, PORT_SMB_BASE | 1);
174 pci_config_writeb(bdf, 0xd2, 0x09); /* enable SMBus io space */
182 // Already done by coreboot.
185 dprintf(3, "pci setup\n");
187 pci_bios_io_addr = 0xc000;
188 pci_bios_mem_addr = 0xf0000000;
189 pci_bios_bigmem_addr = RamSize;
190 if (pci_bios_bigmem_addr < 0x90000000)
191 pci_bios_bigmem_addr = 0x90000000;
194 foreachpci(bdf, max) {
195 pci_bios_init_bridges(bdf);
197 foreachpci(bdf, max) {
198 pci_bios_init_device(bdf);